UEEA2333

Analogue Electronics
Topic 2b

Data Converter Circuits

Reference
Muhammad H. Rashid, (1999),
Microelectronic Circuits: Analysis and
Design, PWS Publishing Company, ISBN
053495174-0. Chapter 16.

PART 1

ADC and DAC

Most physical signals exist in analogue form
For processing in a computer, we need to convert the
signal to digital form
Analog-to-Digital Conversion (ADC) convert
analog signal to digital form
Digital-to-Analog Conversion (DAC) convert
digital signal to analog signal
ADC and DAC acts as the interface between analog
and digital domain

Signal Flow Schematic

Sample-and-Hold (S/H)
Analog input signal

Sampled analog signal

Digitized output signal

6

The Input Analog Waveform

Sample-and-Hold Analog Signal

Digitized Output

Analog-to-Binary Mapping

Analog
14 V

(VREF)

10

5.2
(Va)

Analog scale consists of an infinite no. of real no.

Binary scale consists of a discrete set of integers.
Given an analog number Va, and its
Binary
corresponding binary b, to obtain a linear
7(b )
mapping, equate the proportional ratio of each
6
number with respect to its full-scale maximum
5
value:
4
Va / VREF = b / bmax
3 (b)
Therefore, (Va and b are linearly related)
(depends..)
2
Va = (VREF / bmax) b
1
b = (bmax / VREF) Va
max

10

Principle of a Sample-and-Hold
Circuit
A S/H circuit is to sample an input signal and hold on to that level
for as long as required by the conversion to complete its process.
The capacitor CH is the holding device.
Turning on switch S1 (close it)
will rapidly charge up CH to
the sample voltage. After
turning off, CH will retain the
desired voltage level.
If the time constant RSCH is
very small, the output voltage
will be almost equal to the input voltage at the instant S1 turns off
(i.e. open).
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switch closed
switch open

vCN

12

Digital-to-Analog Converters (DAC)

A typical DAC contains four separate parts:

(1) A reference quantity, Vref

(2) Set of switches to simulate the binary coefficients
of b (i.e. B0, . . . , Bn-1)

(3) A resistive network

(4) An output summer

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Weighted-Resistor DAC

14

 This converter can convert a 4-bit digital word b (B3B2B1B0) to an

analog voltage that is proportional to the binary number b.
The logic voltages, which represent the individual bits B0, B1, B2,
and B3, are used to operate switches S0, S1, S2, and S3, respectively.
When Bi is 1, the corresponding switch is connected to a reference
voltage Vref; when Bi is 0, the switch is grounded.
The op-amp is connected as a current summer. The inverting
terminal is at virtual ground (vd 0). So, the total current IS is:
B3 B2 B1 B0
I S Vref

R3 R2 R1 R0
IS IF, so
VO RF I F
B B B B
RFVref 3 2 1 0
R3 R2 R1 R0
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 Choose the values of resistors with a proper weight ratio:

R
LSB least significant bit R0 0 R
2
R R
R1 1
2
2
R R
R2 2
2
4
R R
MSB most significant bit R3 3
2
8

Then, VO is proportional to the value of the binary B3B2B1B0:

Vref RF
Vref RF 3
2
1
0
b
VO
2 B3 2 B2 2 B1 2 B0
R
R
e.g. Vref = 5 V and R = 10RF, we get (and the graph on next slide):

VO 0.5 23 B3 2 2 B2 21 B1 20 B0
Major disadvantage: wide variety of resistor values required,
changes in value will reduce accuracy and stability of DAC.

16

Output voltage vs binary input (linear map)

17

R-2R Ladder Network DAC

Join resistors in series to get various resistance values.

18

Consider the circuit

with LSB = 1 only.
S0 is closed.

19

 The final circuit gives the output as:

Vref RF B0
VO
4
3R 2

for LSB 1 only

Network for MSB = 1. Similarly, applying Thevenins theorem

looking to the left of 0.

The simplified circuit shown gives the output as,

V R B
VO ref F 13
for MSB 1 only
3R 2

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 Summing up the contributions from all switches, by applying

the superposition theorem, gives

Vref RF B3 B2 B1 B0
VO
1 2 3 4
3R 2
2
2 2

Vref RF 3
2 B3 2 2 B2 21 B1 20 B0
48R
Generally for n bits,
VO

Vo

Vref RF
n

3R ( 2 )

e.g. Vref = 30 V and R = RF give

30
Vo (23 B3 2 2 B2 21 B1 20 B0 )
48
21

Output voltage vs binary input

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PART 2

23

Analog-to-Digital Converters (ADC)

There are many types of A/D converters, depending on the
type of conversion technique used:
(1) Counting
(2) Tracking (up-down)
(3) Successive approximation
(4) Single-ramp integrating
(5) Dual-ramp integrating
The successive-approximation technique is the one most
commonly used, mainly because it offers excellent tradeoffs in
resolution, speed, accuracy, and cost.

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Successive-Approximation ADC
A successive-approximation A/D converter operates by
successively dividing in half the voltage range of the converter.
The converter consists of
five parts:
(1) Analog comparator
(2) 4-bit DAC
(3) 4-bit register (memory)
(4) Logic control
(5) Ring counter

25

Ring Counter & Logic Control

Ring counter provides a timing (or clock) signal to synchronize
the operations of the converter.
Logic control fires activation signals to perform operations.
The combination of logic control, 4-bit register, and ring counter
is often known as the successive-approximation register (SAR).

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Comparator
If Va > Vb, the output of comparator becomes high (logic 1)
If Va < Vb, the output becomes low (logic 0)

Vcom

1 for Va Vb
sgn Va Vb
0 for Va Vb

A S/H circuit is commonly used to hold the input voltage

constant during the conversion process.
There is no need for a S/H if the input signal varies slowly and
has a low noise level.

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Operation of SuccessiveApproximation ADC

Problem Statement:
Show the steps in converting an analog voltage of, say
10 V, to a 4-bit number. Given VREF = 15 V.
To initiate conversion:
Set input Va = 10 V.
Clear the register.
So B3B2B1B0 = 0000.

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Step 1.
The 1st pulse from the ring counter sets B3 = 1 (while the rest
of the bits in the register remain as 0).
So B3B2B1B0 = 1000.
Vb = 8 V (since 10002 = 8)
Note that 8 is approximately half of 15 (i.e. full-scale).
(some design sets the bits to 01112=7, which is also fine.)
Compare with comparator, if Va Vb, B3 will stay at 1;
otherwise B3 will be set to 0.
At the end of step 1, B3 = 1 (since 10 > 8).
So now B3B2B1B0 = 1000.

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Step 2.
The 2nd pulse from the ring counter sets B2 = 1.
So B3B2B1B0 = 1100.
Vb = 12 V (since 11002 = 12)
Note that 4 (B2) is approximately half of 8.
Compare with comparator, if Va Vb, B2 will stay at 1;
otherwise B2 will be set to 0.
At the end of step 2, B2 = 0 (since 10 < 12).
So now B3B2B1B0 = 1000.

30

Step 3.
The 3rd pulse from the ring counter sets B1 = 1.
So B3B2B1B0 = 1010.
Vb = 10 V (since 10102 = 10)
Compare with comparator, if Va Vb, B1 will stay at 1;
otherwise B1 will be set to 0.
At the end of step 3, B1 = 1 (since 10 = 10).
So now B3B2B1B0 = 1010.

31

Step 4.
The 4th pulse from the ring counter sets B0 = 1.
So B3B2B1B0 = 1011.
Vb = 11 V (since 10112 = 11)
Compare with comparator, if Va Vb, B0 will stay at 1;
otherwise B0 will be set to 0.
At the end of step 3, B0 = 0 (since 10 < 11).
Finally B3B2B1B0 = 1010.
The desired number is stored in the register, for a readout.
With an N-bit ADC, the conversion takes N clock periods.
e.g. An 8-bit ADC with a 10-MHz clock will take,
8/(10 x 106) = 8 x 107 = 800 ns.

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Summary of the Steps Involved

in Successive Approximation

33

Resolution
The resolution of an ADC is defined in terms of the smallest
voltage increment that will cause a bit change. It represents the
value of its least significant bit (LSB). Resolution is specified in
volts and determined by,
Q = VREF/(2N1)
where VREF is the analogue full-scale voltage range.
Sometimes, resolution is expressed with respect to VREF :
Q = 1/(2N1), or 100/(2N1) %
Three primary sources of error intrinsic to any A/D converter
are:
Quantization error
When signal is rounded up/down to a digital level

Saturation error
When the input signal exceeds the upper/lower bounds of full-scale

Conversion error
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Quantization Error

= Quantization Error
35

 The analog input to digital

output relationship for a 0-3V,
2-bit ADC is shown right:
Resolution is,
Q = 3/(221) = 1 V
The difference between the
actual input (bottom scale)
and the digital binary level
(vertical scale) assigned by
the converter is referred to
as the quantization error.
This error behaves as noise
imposed on the digital signal.
With Q = 1 V in this example, a LSB is equivalent to 1 V.
In this encoding scheme, error voltage eQ is bounded between 0 and
a LSB above Ei (the input analog signal), so error, eQ(max) = Q.
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This scheme is widely used in digital readout devices.

 A second common scheme

makes the quantization error
symmetric about the input.
The analog voltage is shifted
internally within the ADC by
a bias voltage, Ebias, of an
amount equivalent to LSB.
The effect of such a shift is
shown on the second lower
axis (in the Figure).
This makes eQ bounded by
LSB about Ei, so the worst
error now is eQ(max) = Q.
Regardless of the scheme used, the span of the quantization error
remains 1 LSB and its effect is significant at small voltages.
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