Signal-Power Integrity and EMI Analysis for SingleChip and Multi-Chip-Module applications

Sidina Wane1, Aykut Erdem1, Alexis Le Grontec1, Olivier Tesson1, Serge Bardy1
Robert Kloczkowski3, Dolphin Abessolo2, Paul Mattheijssen2
2

NXP Semiconductors Caen, France, NXP Semiconductors Nijmegen, Netherlands, NXP Semiconductors Boston, USA
different integration levels (Chip, Package and Board),
functional and topological partitioning [1] strategies are
required to keep simulation burden within manageable
complexity. Effective Chip-Package-PCB system CoAnalysis, results in the hybridization of different simulation
techniques (frequency-domain, time-domain, and mixedsignal) in the framework of unified Co-design environment.

AbstractIn this paper, a global Chip-Package-PCB CoDesign and Co-Verification methodology is successfully applied
to Single-Chip Down-converter circuit and Multi-Chip-Module
in transmit mode. Full-wave electromagnetic and thermal CoAnalysis approach is adopted to investigate impact of critical RF
couplings, power dissipation and grounding strategies on systemlevel performances. The Single-Chip down-converter circuit
shows 43dB conversion gain, with 6.5dB noise figure and output
IP3 of 18dBm. The MCM design demonstrates 35dBm output
IP3, 25dBm output CP1, with 45dB image rejection with 25dB
voltage gain for a dissipated power of 2.2W.
KeywordsChip-Package-PCB
Co-Design,
Power-Signal
Integrity, MCM, EM couplings, Thermal Analysis
I.

INTRODUCTION

Power Integrity (PI), Signal Integrity (SI) and EMC/EMI

represent important requirements not only for physical design
and electrical-thermal modeling methods [1-2] but also for
measurement techniques [3]. For the physical design, growing
frequency of operation with increased bandwidth and
integration density motivate the development of cost-effective
Wafer-Level-Packaging (WLP) solutions. Among emerging
WLP solutions, Fan-Out-Package (FOP) eWLB (embedded
Wafer Level Ball Grid Array) is seen as a promising option
offering additional degree of freedom for routing I/O chips
with reduced package parasitic and attractive grounding
strategies compared to conventional leadframe or laminate
packages(e.g., HVQFN:Heat-sink Very thin Quad Flat No
lead). Fig.1 illustrates strong improvements in terms of
conversion gain and Noise Figure obtained using FOP solution
for satellite down-converter circuit. Typically a reduction of
2.5 dB is achieved on the Noise Figure together with an
improved gain up to 46 dB (below 43 dB with HVQFN
solution). Moreover, the image rejection has also been
improved by 3dB with the Fan-Out Package solution.

(a)

(b)

Beyond intrinsic technology enabling attributes, bridging the

gap between Chip, Package and PCB domains will help
pushing system integration to its ultimate performance limits.
Both physical design and electrical-thermal analysis of singlechip (SoC) and multi-chip module (MCM) applications
require global Co-Design methodology where constraints are
pushed from Chip-level to Package-level and even up to PCBlevel in an iterative forward and backward way to guarantee
compliance of final product with PI, SI, EMC/EMI
specifications. Because of complexity reasons, full-wave
simulation of complete Chip-Package-PCB system is
extremely challenging to achieve with available modeling
tools capabilities. In order to render accessible simultaneous
analysis of selected/identified complete paths across the

(c)
Fig.1 Comparison of measured noise-figure (a) and conversion gain
(b) between HVQFN and FOP package. Overview of proposed CPW
RFin access (left); example of a ground connection done with a
single copper traces (c) down to PCB (right) for TV satellite
application [6].

The resulting test-benches are used to verify DC startup,

optimize system-level RF-path isolation, optimize decoupling
capacitances based on the accuracy of the SMD models and

978-1-4673-5707-4/13/$31.00 2013 IEEE

992

check power-signal integrity and EMC/EMI constraints.

Custom probing method [4] is used for system-level ChipPackage-PCB debugging and verification (characterization of
EMI emissions, spurs, pulling/pushing, spectrum purity) both
in time and frequency domains.
In this paper, a global Chip-Package-PCB Co-Design and
Co-Verification methodology is applied to single-Chip downconverter circuit in Fig.2(a),(b) and to Multi-Chip-Module
(MCM in Fig.2(c)) in transmit mode. Full-wave
electromagnetic and thermal Co-Analysis approach is adopted
to investigate impact of critical RF couplings, power
dissipation and grounding strategies on system-level
performances. The MCM design demonstrates 35dBm output
IP3, 25dBm output CP1, 45dB image rejection and 25dB
voltage gain for a dissipated power of 2.2W.

(a)

receiver applications [6]. Its function is to convert the antenna

dish signal in range Ku band at 10.7-12.75GHz down to a
satellite TV IF band in the L-band range 950-2150 MHz.
Fig.3(a) shows the block diagram of the satellite downconverter circuit. 3D Chip-Package prototype model in
Fig.3(b) is built for EM-thermal co-simulations. The chip has
been designed in NXP's QUBiC4X BiCMOS technology. The
process uses 5 metallization layers, with top thick metal for
high quality on-chip inductors and interconnects. To meet the
strict requirement of the application in terms of specified
metrics such as phase noise, Noise Figure, IP3, spurs levels,
the Chip-Package parasitics need to be minimized (ground
inductance, on-chip inductive, capacitive and resistive
couplings). In order to prevent noisy coupling mechanisms
from acting as limiting factors for the targeted system-level
performances extensive EM simulations are carried out to
correctly evaluate effects of grounding strategies and on-chip
signal interference levels.

(b)

(a)
(b)
Figure 3: Down-converter satellite architecture (a), 3D prototype model of
designed Chip-Package model (b).

(c)
(d)
Fig. 2: Microphotograph (a) of single-Chip microwave Down-Converter and
associated Chip-Package prototyping model (b). Micro-photograph of
designed and fabricated MCM Tx application (c) and associated application
board (d).

II.

The VCO demonstrates typically -93dBc/Hz at 100kHz offset.

The close-in noise is around -90dBc in average over 10kHz100kHz range. The integrated phase noise in 10kHz-10MHz
bandwidth is in the order of 1 RMS. The obtained results
associated with very low current consumption represents
state-of-art phase noise performance.

MAIN RESULTS AND EXPERIMENTAL VERIFICATIONS

The proposed Chip-Package-PCB Co-Design methodology

has been successfully applied both to Single-Chip and MultiChip applications. The EM-Thermal Co-simulation approach
combines two model extractions:

The ESD (Electro-Static Discharge) protection network of the

down-converter satellite is a rail-based ESD protection scheme
using diodes and a Darlington bipolar, the crowbar, as active
main ESD supply clamp [7]. All the I/Os are therefore railbased ESD protected.
Since the technology does not feature 5 V transistors, a
dedicated 5V ESD supply clamp has been developed. The RCtriggered crowbar uses cascoded Darlington NPNs at the
power stage due to the 5V output requirement (see Fig. 4(a)).
During an ESD event, the trigger stage switches on the power
stage of the crowbar by pulling up both the Middle and bPA
nodes via the PMOST-transistor and the inverter, respectively.
The RC constants from the trigger stage and the power stage
of the crowbar define the slew rate detector and the ON-time
of the ESD clamp, respectively. The diode string defines a
Middle voltage (1/2Vcc) during normal operation. The
Darlington NPNs are properly sized to withstand high ESD
current and sufficiently clamp the voltage.A 100ns-TLP
(Transmission Line Pulse) setup with 10ns rise time has been
used to characterize performance of the supply ESD clamp

1) a passive network multi-port that includes all relevant

power/ground planes, interconnects, bond-wire connections,
SMDs, traces, etc. The associated multi-port model
representation [5] described in terms of S-parameters or
distributed SPICE-compatible RLCK equivalent circuit
models is back-annotated into circuit simulator (Cadence
Spectre or Agilent ADS).
2) a behavioral model of the digital baseband die switching
activity, the analog blocks being represented by transistor
level description or equivalent model reductions.
The active and passive Co-Verification is realized through the
building of test-benches used to verify DC startup, optimize
system-level RF-path isolation, optimize decoupling
capacitances based on the accuracy of the SMD models and
check power-signal integrity and EMC/EMI constraints.
A. Single-Chip Application: Satelite Down-Converter Circuit
The investigated Single-Chip carrier is composed of
microwave building blocks down-converter for satellite TV

993

used in the ESD protection network of the down-converter

satellite. Below measurements results clearly show that the
crowbar (Fig. 4(b)) can withstand higher than 3kV HBM in
terms of energy.

Although single model EM-thermal integral analysis of

unified Chip-Package-Board assembly design would be the
most accurate approach, this is not possible using existing
design tooling suites.

(a)

(b)

(a)
(c)
(d)
Fig. 5: View of the MCM laminate package (a), 3D EM model of the MCM
design (b), functional block diagram of the module (c) and layout of the
application board (d).

This means necessity of partitioning approach based on

distributed Co-Design. The proposed EM-Thermal Cosimulation methodology combines passive network multi-port
model (see Fig.6(a),(b)) obtained from EM simulations
(including all relevant power/ground planes, interconnects,
bond-wire connections, SMDs, traces, etc.) with behavioral
model of the digital baseband die switching activity and
analog blocks (through transistor level description or
equivalent model reductions). Broad-Band Equivalent Circuits
(BEC) [5] appears as a bridging connection for unified ChipPackage-PCB Co-Verification facilitating predictive modeling
analysis of system-level performances. Effects of packaging
on MCM performances are also evaluated since the KnownGood-Dies (KGD) are initially characterized with their
reference package (but the dies are naked in the module).

(b)
Fig. 4: A Simplified schematic of the RC-triggered crowbar (a). TLP
characterization (b) of a standalone supply ESD clamp (crowbar).

B. Multi-Chip Application:Wireless Infrastructure Tx Circuit

The proposed MCM system is a Tx RF subsystem consisting
of several IC having different functionality with frequency
ranges from 500 MHz to 4000 MHz. The subsystem, built on a
laminate substrate and packaged using HVQFN-56, consists of
the following entities: IQ Modulator, Synthesizer, RF DVGA,
Discrete SMD for DC decoupling. The routed design of the 4layer laminate package is shown in Fig.5(a). Built 3D EM
model of the MCM is depicted in Fig.5(b). The functional
block diagram of the module is indicated in Fig.5(c). Interstage Filters are introduced between the PLL and the IQModulator on one side and between the IQ-Modulator and the
VGA on the other side for limited spurs and harmonic
conversion/pulling.. This integration solution saves total
occupied area in the Tx RF section and saves total consumed
power. In addition, it saves engineering costs for the end
customer. For instance, no tuning and matching is required.
The application is compliant with wireless infrastructure
transmitter constraints known to be hard to meet especially
for cellular networks e.g., 2G- 4G networks, ISM, GPS,
WiMAX, automotive applications, requiring accurate up
conversion of baseband signals to RF. Today high
performance discrete components are used to build the Tx RF
subsystem.

(a)
(b)
Fig. 6: Chip-Package Co-Design Multi-Port as extracted from EM analysis
(a), representation of Input-Output Sub-Multi-Port couplings and associated
ground partitioning (b).

Reflection parameter and dynamic load impedance of the

VGA circuit is characterized for different gain settings. The
characterization results show importance of accounting for
actual load impedance of the VGA circuit in the co-simulation
test-bench since the 50: condition is not really fulfilled in the
broadband range of frequency. As a consequence, the
filter/matching network to incorporate between the IQmodulator and the VGA should be optimized after getting a

994

precise information about the buffer output impedance of the

VGA (same applies for the filter/matching between the PLL
and the IQ-modulator).

in Fig.7 underlining importance of proper grounding

strategies. Differences obtained with the 3D finite element
approach can be explained with the meshing resolution used to
describe the vias in order to speed up CPU time efforts and
guarantee manageable complexity. Fig.8 shows thermal power
dissipation over the laminate routed design. Hot thermal-spots
on the IQ-modulator and VGA chips indicate dissipated power
of 0.94 W and 0.93W on 5V supply respectively. On the PLL
synthesizer the dissipated power is 0.4W on 3.3V supply. A
thermal resistance of 20 K/W is extracted from simulations
and measurement showing good correlation.

The accuracy of the multi-port network model extraction

strongly depends on the used assumption: full-wave or quasistatic. Other important challenges concern partitioning of the
overall system into sub-blocks, grounding strategies as how to
properly define current return paths.

III.

In this paper, global Chip-Package-PCB Co-Analysis and CoVerification methodology has been successfully applied to the
design of Single-Chip and Multi-Chip-Module applications.
Thermal-Electromagnetic Co-Simulation is carried out to
lower energy dissipation, optimize system-level performances
and grounding strategies. Unified Static and full-wave electrodynamic analysis will allow for proper incorporation of ESD
analysis
in
global
Chip-Package-PCB
Co-Design
methodology.
The Single-Chip down-converter circuit shows 43dB
conversion gain, with 6.5dB noise figure and output IP3 of
18dBm implemented in a low cost 16-pin plastic package with
exposed die pad. The chip operates from the 5V supply
commonly available in satellite TV outdoor units with current
consumption of 52mA. The Multi-Chip design application
demonstrates 35dBm output IP3, 25dBm output CP1, with
45dB image rejection and 25dB voltage gain for a dissipated
power of 2.2W. Ongoing work concerns development of
custom probing method for system-level debugging and
verification including characterization of Near-Field and FarField EMI/EMC emissions, spurs, and pulling/pushing.

(a)

(b)
Fig. 7: Correlation between EM simulations and measurement for the
insertion-loss at RF-Out access (a). Effects of Domain-Decomposition
strategies on the transmission (b) parameter.

REFERENCES

For the EM modeling both Full-wave and Quasi-Static

solutions are simulated and compared for different grounding
strategies.

[1]

[2]

[3]
(a)

CONCLUSION

(b)
[4]

[5]

(c)
(d)
Fig.8: Thermal power dissipation on Metal-1(a), Metal-2(b), Metal-3(c),
Metal-4(d) levels of the laminate package.

[6]

Effects of Domain-Decomposition partitioning (Unified

Approach versus Partitioned approach) on the transmission
parameter (linking IQ-signal access and RF-Out) is illustrated

[7]

995

S. Wane, James C. Rautio, and Volker Mhlhaus,Topological and

Functional Partitioning in EM Analysis: Application to Wafer-Level
Chip-Scale Harmonic Filters, IEEE-MTT-S, Boston 2009.
S. Wane, and A. Kuo, Electromagnetic and thermal co-analysis for
distributed co-design and co-simulation of chip, package and board, in
Proceedings of the IEEE-RFIC 2008 Radio Frequency Integrated Circuit
Symposium Digest, 471474 (2008).
S. Braun, T. Donauer, and P. Russer, "A real-time time-domain EMI
measurement system for full-compliance measurements according to
CISPR 16-1-1," IEEE Transactions on Electromagnetic Compatibility,
vol. 50 no. 2, pp. 259-267, May 2008.
S. Wane and A. Erdem, EMI/EMC Near-Field and Far-Field Scanning
Method for Chip-Package-PCB Debugging and Verification, NXPSemiconductors internal report, June 2013.
T. Mangold and P. Russer, Full-wave modeling and automatic
equivalent-circuit generation of millimeterwave planar and multilayer
structures," IEEE Trans. Microwave Theory Techn., vo. 47, pp. 851858, June 1999.
P. Philippe, L. Praamsma, R. Breunisse, E. van der Heijden, F. Meng, S.
Bardy, F. Moreau, S. Wane and E. Thomas A Low Power
9.75/10.6GHz Down-Converter IC in SiGe:C BiCMOS for Ku-Band
Satellite LNBs , IEEE BCTM 2011.
W. D. Mack and R. G. Meyer, New ESD Protection Schemes for
BiCMOS processes with Application to Cellular Radio Designs,
ISCAS, pp. 2699-2702, 1992.