Kolli Hemakiran

Mo. +91-8095898984
Email : hemakiran18@gmail.com
_____________________________________________________________________
Career Objective
To be associated with a semiconductor industry that provides me boundless growth
opportunities and exposure to cutting-edge technologies and learning possibilities.
Experience (0.5Year)

5 months (June-2016 November-2016)trining at cvc pvt.ltd

Summary Of Qualifications

Good understanding of the ASIC and FPGA design flow

Experience in writing Test benches in System Verilog

Working Experience with APB

Very good knowledge in verification especially in System verilog

Experience in using industry standard EDA tools for the front-end design and
verification

VLSI Domain Skills

HDL
HVL
Verification Methodologies
Bus Protocol
EDA Tool:
Domain:
Knowledge

Verilog
SystemVerilog
Coverage Driven Verification
Assertion BasedVerification
AMBA APB
Questa sim and ISE
ASIC/FPGA Design Flow, Digital Design
RTL Coding, FSM based design, Simulation,
Code Coverage, Functional Coverage, Synthesis,

Professional Qualification

Cvc pvt.ltd Certified Advanced VLSI Design and Verification course

from cvc pvt.ltd, Bangalore with ' A ' Grade

Bachelor of Engineering, Rama Chandra College, Vatluru.

JNTU University, Kakinada, India. Discipline: Electronics and Communication
Engineering Percentage: 66.065 with Distinction
Year: April 2016
Intermediate : Nri Academy,Vijayawada
Percentage :91.2%,distinction
Year :May2012
S.S.C. : Sidhartha vidyalaya
Percentage : 84 % ,distinction
Year :May 2010

VLSI Project
AMBA-APB
Role: Design and verfication
HDL: Verilog
EDA Tools: Modelsim,Quartus
Methodology: System verilog
Description: APB (Advanced Peripheral Bus) is one of the components of the AMBA
bus architecture. APB is low bandwidth and low performance bus used to connect the
peripherals like UART, Keypad, Timer and other peripheral devices to the bus
architecture. This paper introduces the AMBA APB bus architecture design. The design is
created using the verilog HDL and is tested by a verilog testbench. This design is verified
using system verilog.
Engneering Project
Fault Tolerant parallel Filter Based On Error Correction Code:
HDL: Verilog
EDA Tools: Modelsim
Description: In some cases, the reliability of those systems is critical, and fault tolerant
filter implementations are needed. ... In this brief, that idea is generalized to show
that parallel filters can be protected using error correction codes (ECCs) in which
each filter is the equivalent of a bit in a traditional ECC.
Extra Curcullar Activities
Active member in helping hands of children
Blood donor

Personal Details

Name

: Hema Kiran

Nationality

: Indian

Language Known

: English, Telgu

Date of Birth

: 21th june,1995

Blood Group

: AB-ve

Hobbies

: Playing cricket, volleyball,

Address

: 271 Sri Venkateswara PG, Near HanumanStatue, Agara , Bangalore-560102

Declaration
I hereby declare that the information given here with is correct to best of my
knowledge and I will responsible for any discrepancy.
Place : Bangaluru

Hema kiran