2012 2nd International Conference on Power, Control and Embedded Systems

Characteristic comparison of connected DG

FINFET, TG FINFET and Independent Gate
FINFET on 32 nm technology
S . L . Tripathi, Ramanuj Mishra and R.A.Mishra

Abstract--This paper describes the comparative study of

different performance parameters for connected DG
FINFET, tri-gate FINFET and Independent Gate FINFET.
The characteristic parameters, which are drain current,
threshold voltage , DIBL and Subthershold slope were
evaluated with the help of 3-D TCAD Device simulator on
32nm technology. As the number of gates increases, the
electrostatic control on the channel increases leading to the
decrease in short channel effect. To overcome the short
channel effect a suitable threshold voltage is required with
the scaling trend in device dimension. The threshold voltage
variation is obtained by varying metal gate work function in
DG and TG FINFET while in IG FINFET the threshold
voltage is varied by changing one of the gate voltage.

ultimate CMOS device structure because the device

shows reduced short channel effect (SCE), higher current
drivability, nearly ideal subthreshold swing (SS), and
mobility enhancement[4],[5].In multi-gate devices the
FINFET is most suitable structure because it can have
simple self-aligned DG and TG structure with good
process compatibility and easier thickness control of FIN
body as in Fig 1(a) ,(b).

Index term--Independent gate(IG), Double gate(DG),

Tri-gate(TG),
Silicon-On-Insulator(SOI),
Work
function, Short channel effect, DIBL, Subthreshold
Slope,3-D Sentaurus TCAD tool
I. INTRODUCTION
The increasing need for higher current drive and better
short-channel characteristics, SOI MOS transistors are
evolving from classical, planar, single-gate devices into
three-dimensional devices with multiple gates (double,
triple etc)[1].The major short channel effects that degrade
the performance severely are degradation in subthreshold
slope(SS) and Drain induced barrier lowering (DIBL). For
device modeling purposes, the DIBL effect can be
accounted for by a threshold voltage reduction depending
on the drain voltage[2] and steep subthreshold slope is
required for faster transition between off (low current)
and on (high current) states[3]. The current drive
capability of multiple-gate SOI MOSFETs is essentially
proportional to the total gate width. For instance, the
current drive of a double-gate device is double that of a
single-gate transistor with same gate length and width[1].
Therefore, Multi-gate MOSFET is a promising device for

Fig1(a) 3-D FINFET structure

Fig1(b) Cross-sectional view of FINFET structure

978-1-4673-1049-9/12/$31.00 2012 IEEE

A . DG Vs Tri-Gate SOI FINFET

The Tri-gate FINFET is a thin-film, narrow silicon island
with a gate on three of its sides [6].The DG FINFET and
Tri-gate FINFET structures are almost same except for
the fact that in DG FINFET, the gate oxide layer is thicker
at the top portion of fin so that only two gate remains
effective for the channel control.(Fig2)
The tri gate FINFET provides a symmetric device
architecture where the channel is controlled by gate from
three sides of the Si film. Since the gate control is
increased, the scaling of Si film thickness in Tri-gate
FINFET is better implemented as compared to
DGFINFET.

applied to the other gate. This effect is similar to the body

effect in FDSOI MOSFETs.[8]. In DG and TG FINFET
we can set the appropriate threshold voltage, by altering
the work function of the metal gate of SOI FINFET. The
threshold voltage of a long-channel MOSFET, Vth, is
classically is defined by (1)[9]
2

(1)

where Qss represents the charges in the gate dielectric,

ms is the work function difference between the
semiconductor and the gate electrode, f is the difference
between the semiconductor Fermi level and the intrinsic
semiconductor Fermi level. For undoped ultra-thin body
devices equation(1) needs modification as in (2)[10]-[12]
2

Fig 2 (a) Double Gate FINFET

(b) Tri-Gate FINFET

B. IG-FINFET Vs DG and TG FINFET

In DG and TG FINFET the gates are electrically
connected but in IG FINFET the two gates are electrically
not connected(Fig3). Here in all the structures of FINFET
the metal gates are used in place of polysilicon gate. The
use of a metal gate eliminates the poly depletion problem
of polysilicon gate. It increases carrier mobility by
reducing the transverse electrical field at a given gate
overdrive.

(2)

Where, Vinv represents the additional surface

potential to 2f that is needed to bring enough
inversion charge for the transistor to reach threshold
into the channel. In this way, we are able to reduce short
channel effects, gate tunneling current and leakage current
with the control of Vth . In case of IG FINFET, the
threshold voltage of Gate 1, Vth(G1) can vary with the
bias voltage of Gate 2 according to the (3)[14]
(3)

With the appropriate value of Threshold voltage we can

easily limit the value of subthreshold slope as in (4),
which shows how effectively the flow of drain current of
a device can be stopped when Vgs is decreased below
Vth.[15]
1

(4)

Where Cd and Ci are depletion layer cpacitance and oxide

layer capacitancere

II. DEVICE STRUCTURE AND DIMENSIONS

Fig 3 IG FINFET device structure

The main feature of the IG-FINFET is that the threshold

voltage of one of the gates can be varied by the bias

To study the characteristics variation of Multi-gate SOI

FINFET a schematic top view of the SOI FINFET is
simulated using 3-D Sentaurus device simulator [16], is
shown in Fig2. 3-D simulations have been performed for
a wide range of proposed technology nodes (Table 1) with
proportional device dimensions and work function values

[13] to meet the requirements of ITRS. We used lightly

doped channel to avoid degrading of carrier mobility and
more Vth variations. The doping concentration of
source/drain region is kept high.

technique we can set the appropriate threshold voltage at

same gate voltage. In case of IG FINFET we can obtain
threshold voltage variation by varying one of the gate
voltage with respect to the other gate at constant voltage.
In this condition it shows behavior like the single gate
structure.
A. DG SOI FINFET and Tri-gate SOI FINFET:
Sentaurus TCAD simulation tool is used to investigate
the effect of work function of gates on the performance
of DG and TG FINFET. With effect of varying metal gate
work function we can set variation in threshold voltage.
The lowest current is obtained for highest gate work
function in Fig3(a)(b) and Fig4(a)(b) for DG and TG
FINFET respectively.

Fig2 2-D Schematic view of FinFET

TABLE I: SPECIFICATIONS USED FOR 3-D FINFET DEVICE

SIMULATIONS

Lg(Gate length)

32nm

Vdd

1V

Wfin(Fin width)

10nm

Channel doping

1E18

Hfin(Fin hight)

60nm

DRAINS/SOURCE
Doping

1E20

tox (Oxide
thickness)

1.1nm

Gate oxide

SiO2

Spacer length

16nm

N type dopant

Phosphorus

thickness
SOI isolation

20nm

P type dopant

Boron

Spacer

Si3N4

Gate contact
material

Metal

III. DEVICE SIMULATION AND RESULT

Sentaurus TCAD simulation tool is used for
characteristic comparison of
Double gate(DG),
independent double gate(IG) and Tri-gate FINFET. From
simulation we observed that by changing the work
function of the metal gates of DG and TG FINFET we
can change the threshold voltage. Hence by using this

DG FINFET: Figure3(a) shows the drain current as a

function of gate voltage for different metal gate work
function [15] This curve actually indicates the
transconductance of SOI MOSFETs at different work
function of metal gate. As we decrease work function of
metal gate from equation (1.2) the threshold voltage
reduces means at low gate voltage channel is formed so
drain current increases with increase in transconductance.

Fig3(a) Subthreshold characteristics of DG FINFETunder different gate

work function

The performance of DG FINFET can be is evaluated in

Table2 which shows that for low gate work function we
are getting low threshold voltage consequently high on
and off current. For high value of work function there is
small change in on current but large change in off current
with nearly ideal subthreshold slope.

Fig4(a) ID-VG Transfer characteristic of TG FINFETunder different

gate work function
Fig3(b) Transfer characteristics of DG FINFET under different gate
work function
TABLE:2 PERFORMANCE OF DG FINFET
DG
FINFET
GATE
WF(eV)

Vth

SS

Ion(mA)

Ioff(A)

4.4

-0.2577

65.05

0.545

3.33E-05

4.5

-0.1691

65.18

0.5143

7.54E-06

4.6

-0.0723

65.11

0.4766

5.69E-07

4.7

0.0398

65.21

0.4316

2.06E-08

4.8

0.1269

65.07

0.3785

6.21E-10

4.9

0.2342

65.06

0.3196

1.79E-11

0.3243

64.97

0.2566

5.07E-13

Fig4(b) Subthreshold characteristic of TG FINFET under different gate

work function

TG FINFET: We are getting better results for TGFINFET with increased control over the channel. It means
that we are getting highest threshold voltage consequently
lowest on/off current for highest work function of metal
gate.Fig4(a)(b) shows the transfer and subthreshold
characteristic of TG FINFET. For the same metal gate
work function it has higher on/off current than DG
FINFET. Fig4(c) shows the variation of threshold voltage
with the changing metal gate work function.We are
getting the range of Vth variation in (-3.5 to +3.5).

Fig4(c) Variation of threshold voltage with metal gate work function

B. IG SOI FINFET
The Id vs Vg characteristic has almost same nature for
different gate barrier Fig5(c). In subthreshold
characteristic a large change in subthreshold slope is
observed leading to the degradation in subthrshold
performence.Fig5(b)

Fig5(c) IG FINFET Id vsVg transfer characteristics for different back

gate voltage
Fig5(a) Graph between Back gate voltage and threshold voltage of
IGFINFET

Table3 shows the performance of IG FINFET for

different values of back gate voltage leading to the
threshold voltage variation.

Fig5(a)(b) shows the Vth and SS variation with different

back gate voltage.The transfer and subthreshold
caracteristics are plotted against the variation of front gate
voltage in Fig5(c)(d).

Fig5(d) IG FINFET Subthreshold characteristics

Fig5(b) IG FINFET graph between Back gate voltage and Subthreshold
Slope of FINFET

TABLE3: PERFORMANCE OF IG FINFET

IG FINFET(work function of both gate=4.4eV)
VG2

Vth

SS

Ion(mA)

Ioff(A)

0.3

-0.607

413.52

0.09376

9.82E-06

0.25

-0.568

0.2

-0.535

231.4

0.090562

4.33E-06

0.15

-0.456

0.1

-0.321

170.34

0.08734

1.13E-06

0.05

-0.1587
140.46

0.08407

2.12E-07

107.64

0.08072

5.22E-08

87.01

0.077332

1.88E-08

81.58

0.07391

8.82E-09

78.64

0.070419

3.99E-09

-0.067

-0.05

-0.0004

-0.1

0.0125

-0.15

0.0183

-0.2

0.0329

-0.25

0.05253

-0.3

0.0827

-0.35

0.0991

-0.4

0.104

C. Comparison of DG, IG and TG SOI FINFET

The DG and TG FINFET both have almost similar
characteristics while IG FINFET has different
nature.Fig6(a),(b).
While
comparing
IG-DG-TG
FINFETS metal gate work function of all FINFET was set
to 4.4ev and back gate bias of IG FINFET Vg2 = 0V. For
IG FINFET the change in threshold voltage is obtained at
cost of subthreshold slope performance degradation. For
DG and TG FINFET change in threshold voltage is
observed by varying suitable gate work function without
affection on its performance.

Fig6(a) Subthreshold characteristics of IG-DG & TG FINFET

TABLE4: COMPARISON OF IG ,DG , TG FINFET

Type

IG FINFET

TG FINFET

DG FINFET

Vth

SS

0.04899

115.48

0.020358627

142.22

-0.0483

211.2

-0.319

298

-0.124

62.71

-0.217

62.49

0.09158

62.51

0.1992

62.22

-0.1399

64.1

-0.23129

64.89

0.04463

63.98

0.14939

64.18

Fig 6(b) Transfer Characteristics of IG-DG & TG FINFET

IV. CONCLUSION
For IG FINFET subthreshold slope is not good if positive
voltage is applied to back gate. But IG FINFET with
forward positive bias gate is good when it has been using
as depletion mode . In case DG and TG FINFET we are

getting good range of Threshold voltage variation with

subthreshold slope nearly ideal value as shown in Table4.
Further, we have seen that we are getting better range of
threshold voltage variation with good subthreshold slope
in TG FINFET. The subthreshold slop is almost constant
over wide range of threshold voltage variation in both the
connected DG and TG FINFET. In this way we can easily
control the short channel effect and current drive
capability with suitable threshold voltage.
V. REFERENCES
[1] Jean-Pierre Colinge, Multiple-gate SOI MOSFETs Solid-State
Electronics 48 (2004) 897905
[2] L. Chang, S. Tang, T.-J. King, J. Bokor, and C. Hu, Gate-length
Scaling and Threshold Voltage Control of Double-gate MOSFETs Int.
Electron Devices Meeting Tech. Dig., pp. 719722, 2000.
[3] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, 15nm
Gate Length Planar CMOS Transistor, in
Int. Electron Devices Meeting Tech. Dig., pp. 937939, 2001.
[4] Y.-K. Choi, et al., IEDM 2001, pp. 421424.
[5] J. Kedzierski, et al., IEDM 2001, pp. 437440
[6] A. Breed and K.P. Roenker, Dual-gate (FinFET) and TriGate
MOSFETs: Simulation and design ISDRS-2003, pp. 150-151,
December 2003.
[7] W. Xiong, C. R. Cleavelin, T. Schulz, K. Schrufer, P. Patruno,J.P.
Colinge, MuGFET CMOS process with midgap gate material NATO
International
Advanced
Research
Workshop,
Nanoscaled
Semiconductor-on-Insulator Structures and Devices, 95 (2006)
[8] J.P. Colinge, Fully-depleted SOI CMOS for analog applications
IEEE Transactions on Electron Devices 45-5, 1010 (1998)
[9] W. Xiong, C. R. Cleavelin, T. Schulz, K. Schrufer, P. Patruno,J.P.
Colinge, MuGFET CMOS process with midgap gate material
Nanoscaled Semiconductor-on-Insulator Structures and Devices, 95
(2006)
[10] P. Francis, A. Terao, D. Flandre, F. Van de Wiele Modeling of
Ultra thin Double-Gate nMOS/SOI Transistors IEEE Transactions on
Electron Devices 41-5,715 (1994)
[11] Y. Tahara, Y. Omura, Empirical Quantitative Modeling of
Threshold Voltage of Sub-50-nm Double-Gate SOI MOSFETs Solid
State Device and Materials, 618 (2005)
[12] Y. Tahara, Y. Omura Empirical Quantitative Modeling of
Threshold Voltage of Sub-50-nm Double-Gate Silicon-on-Insulator
MetalOxide-Semiconductor Field-Effect Transistor Japanese Journal
of Applied Physics 45-4, 3074 (2006)
[13] A. Kranti and G. A. Armstrong, Performance assessment of
nanoscale double- and triple-gate FinFETs Semicond. Sci. Technol.,
vol. 21,pp. 409421, Feb. 2006.
[14 ] H. Lim, J.G. Fossum, Threshold voltage of thin-film silicon-oninsulator MOSFETs IEEE Transaction Electron Devices 30-10, 1244
(1983)
[15] B. Yu, H. Wang, A. Joshi, Q. Xiang, E. Ibok, and M.-R. Lin, 15nm
Gate Length Planar CMOS Transistor Int. Electron Devices Meeting
Tech. Dig., pp. 937939, 2001.
[16] Sentaurus Structure Editor Users Manual, Synopsys
International