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1847
I. INTRODUCTION
Fig. 1. 1-Gsample/s 6-b A/D converter intended for use in a disk-drive read
channel.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001
(2)
comparator. However, the preamplifiers in the array suffer from
random offsets. Collective averaging of the preamplifier outputs
across a properly designed resistor network lowers the impact
of the offsets, improving accuracy of the threshold comparison
without degrading bandwidth [13]. A comparator must quickly
recover from large overdrive when the changing input voltage
rapidly approaches the comparators threshold from far away.
To aid this, the gain of the comparators input differential pair
is about one, which widens its bandwidth. The resulting net amplification of 3 is not sufficient to overcome the dynamic random
offsets in the regenerative latch for 6-b accuracy. Resistor averaging is also used within the comparators to lower the impact
of offsets. Interpolation is not used in this work, because it degrades bandwidth [12], [13]. The second comparator array provides rail-to-rail logic swing for the digital back end consisting
of the SR latch and ROM-based digital encoder.
(4)
(5)
(1)
where represents the index of differential pairs in the array.
determines the width of the impulse response.
The ratio
An array of differential pairs injects two different types of
stimuli currents in the averaging network. First, differential
limited by the linear region of the
signal currents
differential pair enter the network. Second, noise currents
due to transistor random mismatches also enter the
averaging network. A well-designed averaging network should
filter out the random currents, without losing valuable signal
current, nor should the network lower bandwidth. Averaging is
(the number of differential pairs in the
optimum when
unclipped linear region of their characteristic) is greater than
[13].
the impulse response width of the network
Dummy preamplifiers are inserted to compare the input signals with thresholds beyond the actual full scale, so that the tails
of the averaging networks impulse response remain undistorted
at the ends of the full scale. A circular arrangement with suffi-
The second term in (5) is much less than 1, while the third term
is close to 1. Therefore, use of the averaging network raises
preamplifier bandwidth by 3 .
IV. CIRCUIT DESCRIPTIONS
A. Track-and-Hold
An input T/H improves the dynamic performance of an
ADC. By holding the analog sample static during digitization,
the T/H largely removes errors due to skews in clock delivery to
a large number of comparators, limited input bandwidth prior
to latch regeneration, signal-dependent dynamic nonlinearity,
and aperture jitter [11]. The on-chip T/H circuit shown in Fig. 5
precedes the flash quantizer. This simple circuit, consisting
of a passive nMOS switch connected to a sampling capacitor
through a dummy switch [16], [17], offers just the required
linearity. The dummy switch lowers the common-mode jump
after the track-to-hold transition. The main sources of distortion
Fig. 3.
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Fig. 4.
(6)
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001
Fig. 7.
in
(11)
(8)
Solving (8) for
results in
gives
(12)
(9)
and
In order to determine the relationship between
with fixed bias current and transistor size, substitute
and
into (9), where
.
Solving this gives
(10)
(13)
LSB
mV and
V, Fig. 7
With
shows the amplifier stage bandwidth requirement versus the
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Fig. 10.
Fig. 11.
gives
(16)
,
of an input differential pair
. Unlike
both sharing the diode-connected MOS load
a MOS triode region resistor, this load largely decouples the
signal gain and output common-mode voltage. Due to the circular and symmetric nature of the network, nonlinearity of the
diode loads does not offset zero-crossing at the output of the resistive averaging network.
is low and the differential output folIn reset mode,
lows the differential input. While the comparators input is being
lowers the first comsampled to its output, a shorting switch
parator voltage gain to less than one and erases memory of the
previous decision. A similar comparator has been reported previously [24], [25], which applies a short pulse to the reset switch
to improve voltage gain. However, it is impractical to generate
a short pulse at 1.3 GHz, when the clock transitions alone consume 40% of the period.
to turn on the
This comparator uses the standard
. Fixed gain-bandwidth product implies that
shorting switch
the low voltage gain during the comparators reset mode gives a
high output bandwidth for fast erase. However, the gain should
be large to overcome dynamic offset in the regenerative latch
[6], [26][29] of as much as 40-mV rms. Rather than raise the
voltage gain and degrade speed, we have discovered that resistor averaging across an array of regenerating latches lowers
dynamic offsets as well. Use of averaging in the latch stage increases regeneration time constant that necessitates cascaded
comparators to lower bit-error rate. However, the overall power
reduction and sampling rate increase due to averaging surpasses
this minor drawback as discussed in the following section.
D. Two Stages of Averaging
Fig. 13 shows the complete block diagram of the quantizer
with cascaded averaging. This flash ADC contains an array of
63 preamplifiers with nine dummies at each end of the array
for proper averaging at the extremes of the input full scale. The
differential averaging network consists of diode pMOS loads of
the preamplifiers and polysilicon resistors connected between
neighbors in the array. The averaging network in the comparator
array is similar.
Monte Carlo simulations verify the benefits of resistive averaging. The transistor threshold voltage and transconductance are
randomly distributed according to the sigma values provided by
the fabricator and modeled by (17) and (18). The Monte Carlo
transient simulations are performed on the two-stage averaging
resistor network in Fig. 13.
(17)
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Fig. 12.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001
(18)
In the ideal case with no transistor mismatch, the comparator
output changes polarity when a slow ramp input crosses the
corresponding threshold. With random variations added to the
transistors and 10% mismatch in the load capacitance, Fig. 14
shows that the time the comparator changes polarity is randomly
dispersed with respect to when the input crosses zero. For each
Monte Carlo simulation, the input voltage is measured when the
output changes its polarity. The sigma of input-referred random
offset is obtained by curve-fitting the corresponding input voltages to the Gaussian distribution. Fig. 14 is a composite plot of
60 Monte Carlo transient analyses.
Without averaging, the input-referred random offset in one
comparator chain is about 11 mV, as shown in Fig. 15(a). With
mV
(19)
mV),
with simulated preamplifier random offset (
mV), both averaging factors
latch random offset (
and
) of 3, and preamplifier gain (
).
(
We conclude that averaging after the preamplifier array and
dynamic comparator array reduces the overall input-referred
random offset by about 3 .
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)
steer the tail current from one side to the other, speeding up
to couple the nMOSFETs, one
regeneration. Without
to below
output node needs to drop its voltage from
to turn off the corresponding nMOS transistor. The SR latch is
the same structure as the second-stage comparator without the
tail current source.
F. Digital Encoder
(a)
(b)
(c)
Fig. 15. Results of Monte Carlo simulation. (a) Without any averaging.
(b) With averaging in the preamplifier stage only. (c) With averaging applied
both to the preamplifier and comparator stages.
(20)
This has important repercussions on the power consumption.
To raise the gain 3 in a resistor-loaded single-stage amplifier
whose output pole frequency, set by the junction capacitance, is
must be raised 3 . This implies
to be kept fixed, the FET
9 higher current. Therefore, cascaded averaging saves almost
an order of magnitude in preamplifier power.
E. Second-Stage Comparator
Fig. 16 shows the second-stage comparator. A single-phase
clock is applied from this stage throughout the digital back
end; multiple phases with the need to accommodate skews
would limit the highest clock frequency [30]. The second stage
provides rail-to-rail output to the SR latch. As in the case of the
preamplifier and the first-stage comparator, overdrive recovery
time also limits highest ADC clock frequency. During reset
mode, its output is reset through two parallel discharge paths
for fast overdrive recovery. In the next half clock cycle of
,
, and
)
regeneration, differential pair nMOSFETs (
Many digital encoding schemes have been developed to suppress glitch errors caused by the comparator metastability [31],
[32] and bubble errors in the thermometer code [7], [34][38].
Metastability errors occur when nonbinary comparator levels
drive the digital encoder and produce senseless outputs. Bubble
errors result from three major sources. First, the overall input-referred random offset greater than 0.5 LSB can switch the order
of the two adjacent thresholds and create a bubble error. Second,
for the comparators without a single front-end T/H, slew-dependent sampling and clock dispersion [39] increase bubble-error
probability. Finally, the propagation-delay variations through
the preamplifier stage as a result of limited bandwidth and fast
input frequency [7], [25] worsen the bit-error rate due to the
bubble errors.
In this work, the cascaded regeneration times of two ranks of
comparators and SR latch guarantee a metastable error rate of
at 1 Gsample/s. The front-end T/H eliminates
less than 10
the clock skew-dependent bubble errors. The reset switches in
the preamplifier and the first-stage comparators suppress the
bubble errors caused by inadequate overdrive recovery.
With the three major bubble error sources removed, a ROMbased encoder maps thermometer code output from the flash
array into quasi-Gray code (Fig. 17) [40], [41]. This arrangement requires only two-input NAND gates, yet suppresses bubble
errors equivalently to a conventional Gray encoder, which uses
slower three-input NAND gates. To operate at 1-GHz sampling
rate and beyond, the D-flip-flops are implemented with true
single-phase clocked (TSPC) circuits [42], [43]. The encoded
output is decimated by 16 on chip to enable easy acquisition
by a logic analyzer. The output buffers are differential circuits
driving 100- loads.
G. Clock Generator
In this ADC, clock jitter randomly modulates the periodic
sampling instants of the T/H. Nonuniform sampling raises the
noise floor of the digitized system, degrading signal-to-noise
ratio (SNR). Clock jitter is increasingly a concern relative to
the short period of high-speed ADCs. Given a sinusoidal input
waveform with amplitude and radian frequency , SNR due
to clock jitter only is
(21)
is the rms clock jitter [44]. According to (21), to obwhere
tain SNR of 38 dB (the ideal SNR for 6-b quantization of a
sinewave) at input frequency of 650 MHz, the rms clock jitter
should be less than 3 ps.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001
Fig. 16.
Fig. 17.
Fig. 18.
Low-noise methods taken from analog circuit design are applied to the clock generator (Fig. 18). The circuits convert a differential sinewave input, terminated in 50 to suppress off-chip
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Fig. 19.
Fig. 20.
Fig. 21.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001
(a)
Fig. 22.
(a)
Fig. 23.
(b)
(b)
Measured dynamic performance. (a) SNDR versus input frequency. (b) SNDR and SFDR versus conversion rate with 100-MHz input.
(a)
Fig. 24.
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(b)
Comparisons for (a) reported 5 effective number of bits (ENOB) limits of 6-b CMOS ADCs and (b) reported 5.5 ENOB limits of 6-b CMOS ADCs.
TABLE I
PERFORMANCE SUMMARY
VI. CONCLUSION
Fig. 24 compares the performance of this ADC with other
CMOS 6-b converters reported in recent years. It is apparent
how the ADC reported here advances the state of the art. The
key features of this work are now summarized. A T/H for this
6-b ADC enables beyond-Nyquist input up to 1.3-GHz conversion rate. Reset switches in the preamplifier and comparator arrays give fast overdrive recovery. The second comparator is the
fastest such CMOS circuit with rail-to-rail output. In this work,
averaging networks are used in three places: first, to lower the
impact of preamplifier static offset; second, to lower the latch
dynamic offset; and third, to improve the preamplifier bandwidth by 3 . These ideas have led to a compact CMOS ADC
with unprecedented dynamic performance.
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