2016 EMT475 04 Internal Memory

Academic Session 2016/2017
Semester 1
EMT 475/3
Computer Organization
& Architecture
Chapter 4 : Internal Memory
School of Microelectronic Engineering

Universiti Malaysia Perlis
Outline
Semiconductor Main Memory
Error Correction
Random Access Memory (RAM)
Flash Memory
Newer Nonvolatile Solid-State Memory Technologies

Outline
Error Correction
Flash Memory


Introduction
Semiconductor memory subsystems
including ROM, DRAM, SDRAM memories.
Memory cell
Basic element of semiconductor memory.
Three function terminals
Select, Control, Write/Read-carrying electrical
signal.
Error control techniques
to enhance the memory reliability

Semiconductor memory properties
Exhibits 2 stable states to represent binary 1 & 0
Capable of being written into (at least once), to set the
state.
Capable of being read to sense the state.


Memory Cell Operation
Select read/write operation

Control indicates the read/write operation

Semiconductor Memory Types
Memory Type
Random-access-memory (RAM)
Read-only memory (ROM)
Category
Erasure
Write
Mechanism
Volatility
Read-write
memory
Electrically,
byte-level
Electrically
Volatile
Read-only
memory
Programmable ROM (PROM)

Erasable PROM (EPROM)
Electrically Erasable PROM (EEPROM)

Flash Memory
Read-mostly
memory
Not possible
Masks
UV light
chip-level
Electrically,
byte-level
Electrically
Nonvolatile
Electrically,
block-level

Random-access memory (RAM)
Read data from memory & write new data into the memory
easy & fast.
Use electrical signals to
Volatile needs constant power supply to avoid data lost.
Temporary storage.
Two traditional RAM
Dynamic RAM (DRAM)
Static RAM (SRAM).
Note : Dynamic or static refers to the RAM technology.

Dynamic RAM
Bits stored as charge in
capacitors
Charges leak
Need refreshing even when
powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits

Slower
Main memory
Essentially analogue
Level of charge
determines value


Dynamic RAM Structure
2
0000
1
3
3
2
1111
1
Write operation
Read operation

10

DRAM Operation
Address line active when bit Read
read/written
Address line selected
Transistor switch closed
transistor turns on
(current flows)
Charge from capacitor fed
Write
via bit line to sense
amplifier
Voltage to bit line
Compares with
High =1, low = 0
reference value to
Then signal address line
determine 0 or 1
Transfers charge to
Capacitor charge must be
capacitor
restored
11

Static RAM
ON
OFF
OFF
ON
Transistor arrangement gives

stable logic state
State 1
C1 high, C2 low
T1 T4 off, T2 T3 on
State 0
C2 high, C1 low
T2 T3 off, T1 T4 on
Address line transistors T5 T6 is
switch
Write apply value to B &
compliment to B
Read value is on line B
12

Static RAM
OFF
ON
ON
OFF
Transistor arrangement gives

stable logic state
State 1
C1 high, C2 low
T1 T4 off, T2 T3 on
State 0
C2 high, C1 low
T2 T3 off, T1 T4 on
Address line transistors T5 T6 is
switch
Write apply value to B &
compliment to B
Read value is on line B
13

Comparison between SRAM vs DRAM
Static, SRAM
Dynamic, DRAM
Advantages
Disadvantages
Faster
Cache
Simpler to build, smaller
Needs refresh
More dense
circuit
Less expensive
Larger memory units

14

Read Only Memory (ROM)
Permanent storage
Nonvolatile
Microprogramming (see later)
Library subroutines
Systems programs (BIOS)
Function tables

15

ROM at Work
While RAM uses transistors to turn on/off access to a
capacitor at each intersection, ROM uses a diode to
connect the lines if the value is 1. If the value is 0, then
the lines are not connected at all.

16

Types of ROM
Written during manufacture
Very expensive for small
runs
Programmable (once)
PROM
Needs special equipment
to program
Read mostly
Erasable Programmable
(EPROM)
Erased by UV
Electrically Erasable
(EEPROM)
Takes much longer to
write than read
Flash memory
Erase whole memory
electrically

17

16-Mbit DRAM (4M x 4)

18

19

Chip Packaging - EPROM
For 1M words, a total of 20 address pins
(220 =1M) i.e A0-A19
D0-D7 ; 8 lines for data read out
Vcc power supply
Vss ground pin
CE (Chip enable) pin, if > 1 chip, CE
indicates which chip is meant to pick up
the address in the bus.
Vpp program voltage supplied-write
operation.
20

Chip Packaging - DRAM
Data pins are input/output RAM can
be updated
WE and OE indicates write or read
operation
DRAM is accessed by Row and Column
and the address is multiplexed, so
for 4M row/column combinations
only 11 pins are needed (211 x 211 =
222 = 4M)
NC (no connect).
21

256kByte Module
Organization

22

1-MB Memory Organization

23
Outline
Error Correction
Flash Memory

24
Error Correction
Categories
Hard failure
Permanent physical defect
e.g. unreliable store data, erratically switch
Harsh environment, manufacturing defects & wear
Soft failure
Random, nondestructive event
Power supply problem/alpha particles
Undesirable
Modern main memory system
Logic for detecting & correcting errors
25
Error Correction
Error Correcting Code Function
a) No errors
b) corrected errors
c) Errors
detected but
not possible to
correct it.
During fetch, new K

code bits generated
from the M data bits by
f and compared with
fetched code bits
Both data (M bits) and code generated

by f (K bits) are stored.

26
Error Correction
Error-correcting code
Simplest Hamming code (Richard Hamming, Bell Lab)
How long the code must be?
Bit-by-bit comparison using exclusive-OR of the two inputs
The result called syndrome word
K
Syndrome word range, 0 to 2 -1
For M data bits or K check bits
K
2 -1 M + K
Example : for M = 8,
3
K = 3: 2 -1< 8 + 3
4
K = 4: 2 -1> 8 + 4
8 data bits require 4 check bits

27
Outline
Error Correction
Flash Memory

28

Synchronous DRAM (SDRAM)
Access is synchronized with an external clock
Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock, CPU
knows when data will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data and fire it
out in block
DDR-SDRAM sends data twice per clock cycle (leading &
trailing edge)
29

256-Mb
SDRAM
A0 to A12
Address inputs
BA0, BA1
Bank address lines
CLK
Clock input
CKE
Clock enable
CS
Chip select
RAS
Row address strobe
CAS
Column address strobe
WE
Write enable
DQ0 to DQ15
Data input/output
DQM
Data mask

30

SDRAM Read Timing
CL
RL
BL

31

Direct Rambus DRAM (DRDRAM/Rambus DRAM/RDRAM)
Developed by Rambus inc.
Adopted by Intel for Pentium & Itanium
Main competitor to SDRAM (mid-1990s 2003)
Vertical package all pins on one side
Data exchange over 28 wires < cm long
Bus addresses up to 320 RDRAM chips at 1.6Gbps
Asynchronous block protocol
480ns access time
Then 1.6 Gbps
32

DRDRAM diagram

33

Double Data-Rate DRAM (DDR DRAM)
SDRAM can only send data once per clock
DDR SDRAM can send data twice per clock cycle
Rising edge and falling edge

34

DDR Generation
Prefetch buffer (bits)

Voltage level (V)
Front side bus data
rates (Mbps)

DDR1
2
2.5
200400
DDR2
4
1.8
DDR3
8
1.5
DDR4
8
1.2
4001066 8002133 21334266
35
Outline
Error Correction
Flash Memory

36
Flash Memory
Structure
Use both internal & external memory application

Range between EPROM & EEPROM (cost & functionality)
Use electrical erasing technology which can erase entire flash
memory in one or few seconds faster than EPROM
Possible erase memory by blocks
Uses only one transistor per bit higher density than EEPROM
37
Flash Memory
Operation
Added a floating gate (insulated by thin oxide layer)

Initial condition, the cell is representing binary 1
Write: by applying a large voltage across the thin oxide layer
electrons to tunnel through it & trapped on the floating gate,
the cell is representing binary 0
Read: by applying a large voltage in the opposite direction (read)
the electron removes from the floating gate to state of binary 1
38
Flash Memory
Types
NOR & NAND
NOR
NAND
Basic unit of access is a bit Organized in transistor arrays
(memory cell)
(16/32 transistors)
Connected in parallel to the bit Bit line goes low if all word
lines
lines are turned on
Read/write/erased individually
Similar in function to a NAND
Bit line goes low if any word
logic gate
line is turned on.
Similar in function to a NOR
logic gate
39
Flash Memory
NOR & NAND structure

40
Flash Memory
Comparison
Specification
NOR flash memory

(MLC NOR Flash (x16))
NAND flash memory

(MLC NAND Flash (x8))
Access speed
High
Low
Bit density
Low (16Mbit to 1Gbit)
High (1Gbit to 16Gbit)
Read speed
High (103 MB/s)
Moderate (18.6 MB/s)
Write speed
Low (0.47 MB/s)
High (2.4 MB/s)
Application
Internal
External
eXecute InPlace
Program/ Data mass storage

drives, memory cards

USB flash
41
Outline
Error Correction
Flash Memory

42
Newer Nonvolatile Memory Technologies

Memory
hierarchy

43

STT-RAM
Magnetic RAM (MRAM)
Non-volatile
Fast read/write (<10ns)
High programming
endurance (<1015)
Zero standby power
Use write mechanism called polarization-current-induced
magnetization switching
Good candidate for either cache or main memory

44

PCRAM
Based on chalcogenide
alloy material
Resistance differences
between amorphous &
crystalline phase
SET crystallized by electrical pulse
RESET amorphous by larger electrical current
Good candidate for replace or supplement DRAM for main memory

45

ReRAM
Also known as
RRAM
Operates by creating
resistance
rather than directly
storing charge.
Low power, far superior to flash memory in terms of endurance &
much smaller

46
Finish!
Q&A

47

2016 EMT475 04 Internal Memory

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2016 EMT475 04 Internal Memory

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Academic Session 2016/2017

School of Microelectronic Engineering

School of Microelectronic Engineering

School of Microelectronic Engineering

Semiconductor Main Memory

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

Select read/write operation

Semiconductor Main Memory

Programmable ROM (PROM)

Electrically Erasable PROM (EEPROM)

Semiconductor Main Memory

Semiconductor Main Memory

Need refresh circuits

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

Semiconductor Main Memory

Transistor arrangement gives

Semiconductor Main Memory

Transistor arrangement gives

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

Semiconductor Main Memory

Semiconductor Main Memory

School of Microelectronic Engineering

Semiconductor Main Memory

School of Microelectronic Engineering

School of Microelectronic Engineering

During fetch, new K

Both data (M bits) and code generated

School of Microelectronic Engineering

8 data bits require 4 check bits

School of Microelectronic Engineering

Random Access Memory (RAM)

Random Access Memory (RAM)

Bank address lines

Row address strobe

Column address strobe

School of Microelectronic Engineering

Random Access Memory (RAM)

School of Microelectronic Engineering

Random Access Memory (RAM)

Random Access Memory (RAM)

School of Microelectronic Engineering

Random Access Memory (RAM)

School of Microelectronic Engineering

Random Access Memory (RAM)

Prefetch buffer (bits)

School of Microelectronic Engineering

4001066 8002133 21334266