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A New CDMA Encoding/Decoding Method for on-Chip


Communication Network
Abstract:
As a high performance on-chip communication method, the code division multiple access
(CDMA) technique has recently been applied to networks on chip (NoCs). We propose a new
standard-basisbased encoding/decoding method to leverage the performance and cost of CDMA
NoCs in area, power assumption, and network throughput. In the transmitter module, source data
from different senders are separately encoded with an orthogonal code of a standard basis and
these coded data are mixed together by an XOR operation. Then, the sums of data can be
transmitted to their destinations through the onchip communication infrastructure. In the receiver
module, a sequence of chips is retrieved by taking an AND operation between the sums of data
and the corresponding orthogonal code. After a simple accumulation of these chips, original data
can be reconstructed. We implement our encoding/decoding method and apply it to a CDMA
NoC with a star topology. Compared with the state-of-the-art Walsh-code-based (WB)
encoding/decoding technique, our method achieves up to 67.46% power saving and 81.24% area
saving together with decrease of 30%50% encoding/decoding latency. Moreover, the CDMA
NoC with different sizes applying our encoding/decoding method gains power saving, area
saving, and maximal throughput improvement up to 20.25%, 22.91%, and 103.26%,
respectively, than the WB CDMA NoC. The proposed architecture of this paper analysis the
logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:

Existing System:
The previously proposed CDMA NoCs are based on a digital encoding and decoding method
requiring that the spreading codes have both the orthogonal and balance properties. To this end,

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the Walsh code is typically used. However, the Walsh-code-based (WB) encoding and decoding
method has inherent shortcomings, which are given as follows.
1) Design Complexity: In the encoding method, an arithmetic addition logic unit, whose logic
overhead increases with the number of senders, is used to mix coded data together. In the
decoding method, a key demux-accumulation-compare unit is used to retrieve the source data
from mixed data chips (in this brief, each bit of a spreading code is called a chip, and thus the
encoded data is called data chips). This unit is, however, area-consuming.
2) Low Code Utilization: In an S-chip Walsh code set, S must be equal to 2N, where N is a
natural number, and at most S 1 sequences can be used to encode the original data. This results
in a waste of sequences in the code set. For example, a 16-node network needs a 32-chip Walsh
code set, because a 16-chip Walsh code set can only provide 15 sequences for data encoding and
it thus cannot satisfy the requirement of 16 sequences, one for each node.
Disadvantages:

high area
high power

Proposed System:
The basic structure of applying CDMA technique to NoC with a star topology is shown in Fig. 1.
In this figure, a PE executes tasks of the application and network interface (NI) divides data
flows from PE into packets and reconstruct data flows by using packets from NoC.
In the sender, packet flits from NI are transformed to a sequential bit stream via a parallel-toserial (P2S) module. This bit stream is encoded with an orthogonal code in the Encoding module
(E in Fig. 1). The coded data from different encoding modules are added together in the Addition
module (A in Fig. 1). Then, the sums of data chips are transmitted to receivers. In the receiver,
Decoding modules (D in Fig. 1) reconstruct original data bits from the sums of data chips. Then
these sequential bit streams are transformed to packet flits by serial-to-parallel (S2P) modules.
Finally, these packet flits are transferred to NI.

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Fig. 1. Structure of CDMA NoC.


CDMA Encoder
Two different encoding methods, WB encoder and SB encoder, are compared in Fig. 2.
Fig. 2(a) shows the WB encoder architecture. An original data bit is first encoded with a Walsh
code by taking an XOR operation. Then, these encoded data are added up to a multibit sum
signal by taking arithmetical additions. Each sender needs an XOR gate, and multiple wires are
used to express the sum signal if we have two or more senders. Moreover, the number of wires
increases as the number of senders increases.

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Fig. 2. Block diagram of encoding scheme. (a) WB encoder. (b) SB encoder.


Fig. 2(b) shows our SB encoding scheme. An original data bit from a sender is fed into an AND
gate in a chip-by-chip manner, and it will be spread to n-chip encoded data with an orthogonal
code of a standard basis. The relationship between a bit and a chip is shown in Fig. 3. Then, the
encoded data from different senders are mixed together through an XOR operation, and a binary
sum signal is generated. Therefore, the output signal is always a sequence of binary signal
transferred to destination using one single wire. The progressions of both the encoding schemes
are depicted in Fig. 3.

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Fig. 3. Data encoding example. (a) WB encoding. (b) SB encoding.


Fig. 3(a) and (b) illustrates the WB encoding process with four-chip Walsh codes and the SB
encoding process with four-chip standard orthogonal codes, respectively.
CDMA Decoder
The WB decoding scheme is presented in Fig. 4(a). According to the chip value of Walsh code,
the received multibit sums are accumulated into positive part (if the chip value is 0) or negative
part (if the chip value is 1). Therefore, the two accumulators in the WB decoder separately
contain a multibit adder to accumulate the coming chips and a group of registers to hold the
accumulated value. Through the comparison module after the two accumulators, the original data
is reconstructed. If the value of positive part is large, the original data is 1. Otherwise, the
original data is 0.

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Fig. 4. Block diagram of decoding scheme. (a) WB encoder. (b) SB encoder


The SB decoding scheme is shown in Fig. 4(b). When the binary sum signal arrives at receivers,
an AND operation is taken between the binary sum and the corresponding orthogonal code in
chip-bychip manner.
Advantages:

Less area
Less power

Software implementation:

Modelsim
Xilinx ISE

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