Reg.

No:
S. VEERASAMY CHETTIAR COLLEGE OF ENGINEERING AND TECHNOLOGY
College Road, S.V.C Nagar, Puliyangudi- 627 855
Department of Electrical and Electronics Engineering
Academic Year 2015-2016(ODD Semester)
Internal Test-III
Subject Code/Title
: EE6301/ Digital Logic Circuits
Year/Semester
: II /III
Name of the Faculty/Dept : M.K.Anandkumar /EEE

Date: 17/10/15
Time: 9.00 AM to10.30AM
Maximum Marks: 50

(Answer ALL the Questions)

PART-A (5*2=10)

1.
2.
3.
4.
5.

What is a package in VHDL?

What are races?
Define Hazards.
What is Static 0 and 1 Hazards?
Write a short note on shared Row state assignment.
PART-B (8+16+16=40)

6. a) Design of fundamental Mode asynchronous sequential circuits.

(8)

OR
b) Write the VHDL code to realize D flipflop for sequential circuit

(8)

7. a) Write the VHDL code to realize a full adder using

(i)
Behavioral modeling
(ii)
Structural modeling
OR
b) Explain the various types of hazards in sequential circuit design and the methods to
eliminate them. Give suitable examples.
8. a) Explain the operators and it types.

(16)
(16)

OR
b) (i) Write the VHDL code to realize 4 bit binary counter for sequential circuit.
(ii) Write the VHDL code to realize Shift register for sequential circuit.

Faculty

(8)
(8)

HOD

(8)
(8)

Reg.No:
S. VEERASAMY CHETTIAR COLLEGE OF ENGINEERING AND TECHNOLOGY
College Road, S.V.C Nagar, Puliyangudi- 627 855
Department of Electrical and Electronics Engineering
Academic Year 2015-2016(ODD Semester)
Internal Test-III
Subject Code/Title
: EE6301/ Digital Logic Circuits
Year/Semester
: II /III
Name of the Faculty/Dept : M.K.Anandkumar /EEE

Date: 17/10/15
Time: 9.00 AM to10.30AM
Maximum Marks: 50

(Answer ALL the Questions)

PART-A (5*2=10)

1. What are the types of hazards?

2.
3.
4.
5.

Define PROM.
Define PAL.
How does an essential hazard occur?
Define PLA
PART-B (8+16+16=40)

6. a) Implement the switching function F=m(1,3,5,7,8,9,14,15) by a static hazard free 2 level

AND-OR gate network.
(8)
OR
b) What is RTL Design and Explain it?
(8)
7. a) Explain the various types of hazards in sequential circuit design and the methods to
eliminate them. Give suitable examples.
OR
b) i)Find a static and dynamic Hazard free realization for the following function
F(A,B,C,D)= m(1,5,7,14,15) using NAND gates
ii) F(A,B,C,D)= m(1,5,7,14,15) using NOR gates

(16)
(8)
(8)

8. a) (i) Write the VHDL code to realize 3 bit magnitude comparator using data flow modeling (8)
(ii) Write the VHDL code to realize SR flipflop for sequential circuit .
(8)
OR
b) Design a sequential circuit using T flip-flops.The stable table of the circuit is as given below:

Prsent state
a
b
c
d
e
f
g
h

Faculty

Next State
X=0
X=1
f
b
d
c
f
e
g
a
d
c
f
b
g
h
g
a

Output
X=0
0
0
0
1
0
1
0
1

X=1
0
0
0
0
0
1
1
0

HOD

(16)

SUBJECT CODE/NAME : EE6301 /DIGITAL LOGIC CIRCUITS

YEAR/SEM
: II/III
ACADEMIC YEAR
: 2015-16(ODD)

SUBJECT CODE/NAME :EE6303 /LINEAR INTEGRATED CIRCUITS

YEAR/SEM
: II/III
ACADEMIC YEAR
: 2015-16(ODD)