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Logic Circuits and Switching Theory

Laboratory 2 Digital Logic Gates


2.1 Objectives
The purpose of this lab is to:
Recognize the operation, characteristic and specification of TTL logic gates (AND,
OR, INV, NAND, NOR and XOR);
Determine experimentally the truth table of logic gates, and
Measure the electrical characteristics and propagation delay of TTL and CMOS gates.

2.2 Prelab Assignment


1. Determine the truth table of the following gates: AND, OR, INV, NAND, NOR and
XOR and show them as as Table 2.1 to Table 2.6
2. Using the specification sheet of a TTL gate and a CMOS gate, obtain the following
operating condition and characteristic: VIH , VIL , VOH , VOL , tpLH , tpHL and fan-out.
Show it as Table 2.7

The Prelab assignment must be completed before starting the experiment.


NO PRELAB ASSIGNMENT, NO EXPERIMENT!

R. Stephen L. Ruiz

2015

Logic Circuits Laboratory

Table 2.1 AND Gate

Table 2.4 NAND Gate

Table 2.2 OR Gate

Table 2.3 Inverter Gate

Table 2.5 NOR Gate

Table 2.6 XOR Gate

Table 2.7. Gate Characteristics.


Parameter
TTL
CMOS
VIH
VIL
VOH
VOL
tpLH
tpHL
Fan-out
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Logic Lab 2. Logic Gates

2.3 Equipment and Circuit Components


2.3.1 Equipment and accessories
Logic Trainer

Dual Trace Oscilloscope

Logic Probe

Breadboard

Logic Pulser

Cables and Connecting Wires

2.3.2 Circuit Components


AND, OR, INV, NAND, NOR and XOR logic trainer gates
74LS04 TTL Hex Inverter
74HC04 CMOS Hex Inverter
10 K-ohms potentimeter

2.4 Lab Experiment


2.4.1 Truth Table
1. Using the logic gates in the logic trainer, obtain the truth table of an AND, OR, INV,
NAND, NOR and XOR gates. The truth table is obtained by connecting the inputs
of the gate to data switches and the output to an LED indicator. Compare the results
with the truth table listed in Table 2.1 to 2.6.

2.4.2 Electrical Characteristics


1. (VOH , VOL ) Connect a 5VDC supply (pin 14) and GND (pin 7) to a 74LS04 IC. Using
one inverter in the IC package, ground the input (pin 1) and measure the output (pin
2) voltage with the oscilloscope. Connect the input to logic 1 (5VDC) and repeat
the measurement.
2. (VIL , VIH ) Connect a variable 0-5VDC voltage supply to the input. Monitor the
output with a logic probe. Vary the voltage from zero to 5VDC and from 5VDC to
zero. Observe the output. Measure the range of input voltage where the output is at
logic 0. Repeat the measurement for the output at logic 1.
3. Using a 74HC04 perform the same measurements and record the result.

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Logic Circuits Laboratory

2.4.3 Propagation Delay


1. Using a 74LS04 IC, connect all six inverters in cascade. Apply clock pulses to the
input of the first inverter. Connect one channel of the oscilloscope to the input of the
first inverter and the second channel to the output of the last inverter.
2. Set the time base to the lowest time-per-division setting. Measure the time delay on the
oscilloscope trace. This is the time from 50% of the input to 50% of the output. Divide
the total delay by six, to get the average propagation delay per inverter. Measure the
delay when the output is changing from LOW to HIGH (tpLH ) and when the output
is changing from HIGH to LOW (tpHL ). The propagation delay is the average of the
LOW to HIGH and the HIGH to LOW delays
Measure the rise (tR )and fall (tF )time. The rise and fall times represents the amount
of time it takes a signal to change state. For this measurement, use the 10% and 90%
points of the oscilloscope trace.
3. Using a 74HC04 perform the same measurements and record the result.
4. Construct a 5 inverter ring oscillator using a 74LS04 IC. From this circuit determine
the average propagation delay by measuring the period of oscillation.
5. Replace the IC of the ring oscillator with a 74HC04 and determine the average propagation delay.

Logic Lab 2. Logic Gates

2.5 Data and Result


2.5.1 Truth Table

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Date:

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Logic Circuits Laboratory

2.5.2 Electrical Characteristic

2.5.3 Propagation Delay

(Add additional sheets as needed)


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Date:

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Logic Lab 2. Logic Gates

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2.6 Lab Report


To be considered complete, the Lab report must contain the following:
Cover page
I. Objectives
II. Theoretical/Conceptual Framework
TTL/CMOS Logic gates.
III. Equipment and Circuit Components
IV. Set-up/Schematic drawings
Diagrams and figures necessary to illustrate the experimental set-up.
V. Procedures
Description of implemented tests procedures
VI. Data and Results
Presentation of experimental data, observations and measurements. Tables, diagrams
and figures as appropriate.
VII. Analysis and Discussion
Analysis and insights gained through the conducted experiment.
VIII. Conclusion
Conclusions reached as a result of performing the lab experiment
IX. Comments
Comments and suggestions that might lead to easier and deeper understanding of the
topic covered by the activities.
X. Appendix
Photo copy of specifications sheets of a TTL and a CMOS gate.
XI. References
Bibliographic listing of reference materials used in the report specially in the theoretical framework.

Do not copy text from your references verbatim. This is a form of cheating, is
absolutely prohibited and could merit a grade of 5.0 for the course.
Email your comments and suggestions to improve this material.
R. Stephen L. Ruiz

rslruiz@gmail.com