A

Compal confidential

Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_PM+ICH7-M core logic
2006-01-13
3

REV:1.0

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

Cover Sheet
Size
Document Number
Custom L A - 2 8 2 1 P
Date:

Rev
1.0

Saturday, January 14, 2006

Sheet
E

of

52

Compal confidential

AngelFire 3.0

File Name : LA-2821P

A ccelerometer
L I S 3 LV02DQ

F a n Control
p a ge 4

M o bile Yonah

p a g e 27

T h ermal Sensor
A DM1032AR

u F C PGA-478 CPU
p a g e 4,5,6

C l o c k Generator
I CS954306

p a ge 4

A ccelerometer
L I S 3 LV02DQ

p a g e 15

p a g e 27

FSB
H _ A # ( 3..31)

5 3 3 / 6 6 7 MHz

H _ D # (0..63)

D D R 2 -400/533/667
M X M III connector

P CI-E x 16

Intel Calistoga MCH

945PM

p a g e 18

CRT / TV-OUT

p a g e 7 , 8 , 9,10,11,12

LCD CONN

U S B2.0

p a ge 17

B A N K 0 , 1, 2, 3

p a g e 13,14

Dual Channel

P CBGA 1466

p a ge 16

D D R 2 -SO-DIMM X2

U SB conn x2
( Docking) p a g e

35

U S B2.0 HUB /
page
F P Conn

30

U SB conn x2

D MI

F i n g erPrinter AES2501
p a g e 30
U SBx1
N e w Card USBx1

p a g e 30

p a g e 24

B T Conn

P CI-E BUS

A C - L I N K/Azalia

Intel ICH7-M

p a g e 30

USB conn x2
(Sub Board) p a g e

P CI BUS

M D C1.5
29

p a g e 34

p a g e 28

MAX9710ETPp a g e

A u dio CKT
1 0 /100/1000 LAN
B C M 5753M

L ED
p a g e 32

M i n i-Card

CardBus Controller

p a g e 25,26

AD1981HD

mBGA-652

T I PCI7612

p a g e 27

A MP & Audio Jack

p a g e 23,24

S PI

S A T A HDD Connector

S A T A Master

p a g e 20

R J 4 5 /11 CONN

p a g e 20

p a g e 26

1 394 port

S l o t 0/Smart Card

p a g e 23

p a g e 24

S P I ROM
SST25LF080A
p a g e 23

6 in1 Slot
p a g e 23

P A T A Slave

Docking CONN.

P A T A ODD Connector
p a g e 20

L P C BUS
P o w e r OK CKT.
p a g e 37

P o w e r On/Off CKT.

Security Module

S MSC Super I/O

LPC47N217
p a g e 31

SMSC KBC 1021

p a g e 32

p a g e 34

F lash ROM
SST49LF008A
p a g e 32

p a g e 33

T o u c h Pad CONN.

D C / D C Interface CKT.

p a g e 34

29

p a g e 1 9 ,20,21,22

R T C CKT.

I nt.KBD
p a g e 34

C O M1
( Docking )

p a g e 35

L PT
( Docking )

p a g e 35

* R J - 4 5 ( LED*2)
* R J - 1 1 ( P a s s Through)
* C RT
* C O M P O S I T E V ideo Out
* T V OUT
* D VI
* L I N E IN
* L I N E OUT
* P C I - E x2
* S e r i a l Port
* P a r a l l e l Port
* P S / 2 x2
* U S B x2
p a g e 34
* D C JACK

p a g e 36

T r a c k Point CONN.
p a g e 34

Compal Secret Data

S e c u r i t y C l a s s ification

P o w e r Circuit DC/DC

2 0 0 5 /03/10

Issued Date

P a g e 3 8 , 3 9 , 4 0 , 4 1 ,42,43,44,45,46,47

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

B l o c k Diagram
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

of

52

S y mbol Note :

V oltage Rails
P o w er Plane

Description

S 0 - S1

S3

VIN

A d a p t e r power supply (18.5V)

N/A

N/A

N/A

A C o r b a t t e ry power rail for power circuit

N/A

N/A

N/A

C o r e voltage for CPU

ON

OFF

OFF

ON

OFF

OFF

+ VCCP

1 . 0 5 V p o w e r r a i l for Processor I/O and MCH/ICH core power

: m e a n s Digital Ground

S5

B+
+ C P U_CORE

+ 0.9VS

0 . 9 V s w i t ched power rail for DDRII Vtt

ON

OFF

OFF

+ 1.5VS

1 . 5 V s w i t c h ed power rail for PCI-E interface

ON

OFF

OFF

+ 1.8V

1 . 8 V power rail for DDRII

ON

ON

OFF

+ 1.8VS

1.8V sw itched power rail

ON

OFF

OFF

+ 2.5VS

2 . 5 V s w i t ched power rail for MCH video PLL

ON

OFF

OFF

+ 2 . 5VALW

3 . 3 V a l ways on power rail

ON

ON

O N*

+ 3VALW

3 . 3 V a l ways on power rail

ON

ON

O N*

+ 3VS

3.3V sw itched power rail

ON

OFF

OFF

+ 5VALW

5 V a l w ays on power rail

ON

ON

O N*

+ 5VS

5 V s w i tched power rail

ON

OFF

OFF

+ R T C_VCC

RT C power

ON

ON

ON

: m e a n s Analog Ground

12/12

: M o d i f i e d Area Mark(Compare with EAL60).

*
*
*

Bus

P C I Device ID

1
0
0
0
0
0
0
0
0
0
0
0
0

A zalia
PCI-E
U SB1.1/2.0
P C I t o PCI (DMI to PCI)
A C 97 MODEM
A C 9 7 Audio
P A T A/SATA
L P C I/F
S MBUS
C P U I/F
D MA
P MU

I DSEL #

D8

AD24

D27

AD11

D28

AD12

D29

AD13

D30

AD14

D30

AD14

D30

AD14

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

D31

AD15

*
*
*
*
*
*
*
*
*
*
*

E x t e r n al PCI Devices
D E V I CE

P C I Device ID

M i ni-PCI

D4

I DSEL #
AD20

R E Q/GNT #
0

C A RD BUS

D6

AD22

C DEG

: M o d i fied Area Mark.

: C -BOM impact

I n t e rnal PCI Devices

D E V I CE

N o t e : L a yout Related Memo

: Q u e s tion Area Mark.(Wait check)

N o t e : O N * m e a n s that this power plane is ON only with AC power available, otherwise it is OFF.

L AN

: L a y o u t Note related Area Mark.

PI RQ

*
*

@ : m e a n s j ust reserve , no build

S P I @ : m e a n s j u s t b uild when SPI I/F BIOS function reserve.
F W H @ : m e a n s j u s t build when FWH I/F BIOS function reserve.
N O X D P @ : m e a n s j u s t build when XDP function disable.
X D P @ : m e a n s j u s t b u i l d w h e n X D P f u nction enable. When this time, docking PCI express will not work.
T P M 1 . 2 @ : m e a n s j u s t build when TPM1.2 function enable.
T P M @ : m e a n s j u s t build when TPM function enable.
S C @ : m e a n s j u s t build when SmartCard function enable.
S A T A @ : m e a n s j u s t build when SATA I/F HDD enable.
N O S A T A @ : m e a n s j u s t build when SATA I/F HDD disable.
N C @ : m e a n s j u s t build when New Card function enable.
N O N C @ : m e a n s j u s t build when New Card function disable.
M D C 1 . 5 @ : m e a n s j u s t build when MDC1.5 function enable.
7 6 1 2 @ : m e a n s j u s t build when TI PCI7612 chip selected.
7 6 1 1 @ : m e a n s j u s t b u ild when TI PCI7611MLS chip selected.
2 5 0 @ : m e a n s j u s t b u i l d when SMsC LPC47N250 chip selected.
1 0 2 1 @ : m e a n s j u s t b u ild when SMsC KBC1021 chip selected.
1 9 8 1 H D @ : m e a n s j u s t build when AD1981HD chip selected.
4 5 @ : m e a n s n e e d b e m o u n ted when 45 level assy or rework stage.
A C C E L @ : m e a n s j u s t b uild when Accelerometer chip LIS3LV02DQ selected.
N O D P @ : m e a n s j u s t b u i l d when No DP design Clock Gen. selected.
D P @ : m e a n s j u s t b u i l d when DP design Clock Gen. selected.
L P N O @ : m e a n s j u s t b u i l d when No LP design ICS Clock Gen. selected.
L P @ : m e a n s j u s t b u i l d when LP design ICS Clock Gen. selected.
D B @ : m e a n s j u s t b u i l d when Mini-PCI E Debug Card function enable.

* : m e a n s d e f i n e for SMT build when this stage

I2C / SMBUS ADD RESSING

D E V I CE

HEX

A D D R ESS

D D R SO-DIMM 0

A0

1 0100000

D D R SO-DIMM 1

A4

1 0100100

C L O C K GENERATOR (EXT.)

D2

1 1010010

U S B HUB

5C

0 1011100

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

Notes List
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

of

52

H_A#[3..31]

H_D#[0..63]

JP8A

+3VS

5/10

7
R443

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#[0..4]

YONAH

A D D R GROUP

D A T A GROUP

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
7
7

H_ADSTB#0
H_ADSTB#1

H_ADSTB#0
H_ADSTB#1

CLK_CPU_BCLK
CLK_CPU_BCLK#

15 CLK_CPU_BCLK
15 CLK_CPU_BCLK#

H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#

7 H_ADS#
7 H_BNR#
7 H_BPRI#
7 H_BR0#
7 H_DEFER#
7 H_DRDY#
7 H_HIT#
7 H_HITM#

R448
56_0402_5%
+VCCP

7
7
7

H_LOCK#
H_RESET#

H_RS#[0..2]

H O S T CLK

C O N TROL

H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

XDP_DBRESET#
H_DBSY#
H_DPSLP#
H_DPRSTP#
H_DPWR#
XDP_BPM#4
XDP_BPM#5
H_PROCHOT#

21

XDP_DBRESET#
7 H_DBSY#
20 H_DPSLP#
20,45 H_DPRSTP#
7 H_DPWR#

45

H_PROCHOT#

+VCCP

R447
56_0402_5%
20
7

H_PWRGOOD
H_CPUSLP#

R27
R28

@ 1K_0402_5%
51_0402_5%

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

M ISC

H_PWRGOOD
H_CPUSLP#
XDP_TCK
XDP_TDI
XDP_TDO
TEST1
TEST2
XDP_TMS
XDP_TRST#

L E G A CY CPU

7,20

H_THERMTRIP#

+VCCP

JP31

T h i s s h a l l p l a c e n e a r CPU
R524
56_0402_5%

XDP_TDI

XDP_BPM#5
XDP_BPM#4
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0

H_PWRGOOD

@ 1K_0402_5%

R442
H_PWRGOOD_R
1K_0402_5%

XDP_TMS

R523

56_0402_1%

XDP_TDO

R525

56_0402_5%

XDP_BPM#5

R526

56_0402_5%

XDP_TRST#

R521

56_0402_5%

XDP_TCK

R522

56_0402_5%

CLK_CPU_XDP
CLK_CPU_XDP#
+ V C C P 1K_0402_1%
H_RESET#_R
R441
H_RESET#
XDP_DBRESET#_R
XDP_DBRESET#
R444
200_0402_1%
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
R191
0_0402_5%

+VCCP
C 5 3 9 0.1U_0402_16V4Z
ICH_SMBDATA
ICH_SMBCLK
XDP_TCK

CLK_CPU_XDP 15
CLK_CPU_XDP# 15

SAMTE_BSH-030-01-L-D-A
C

T h e r m a l S e n s o r ADM1032AR-2
+3VS

C69
0.1U_0402_16V4Z
R24
U5
ICH_SMBCLK
H_THERMDA

ICH_SMBDATA

H_THERMDC

THERM_SCI#

10K_0402_5%

C68

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

THERM_SCI#

21

THERM#

R25

7
7
7
7

ADM1032AR-2_MSOP8

+3VS

A d d r e s s : 1 0 0 1 _ 1 01

10K_0402_5%

H_DSTBN#[0..3]

H_DSTBP#[0..3]

ICH_SMBCLK
ICH_SMBDATA

13,14,15,18,21,25,27 ICH_SMBCLK
13,14,15,18,21,25,27 ICH_SMBDATA

+5VS

PWM Fan Control circuit

JP6
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_NMI

T H E RMAL
D I ODE

H_THERMDA
H_THERMDC
H_THERMTRIP#

H _ T H E R M D A , H _ T H E R M DC routing together.
T r a c e w i d t h / S p acing = 10 / 10 mil

XDP_DBRESET#_R

ITP-XDP Connector

2200P_0402_50V7K

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_STPCLK#
H_SMI#

D1

H_A20M# 20
H_FERR# 20
H_IGNNE# 20
H_INIT# 20
H_INTR 20
H_NMI 20

CH751H-40_SC76

+3VS

H_STPCLK# 20
H_SMI# 20

FOX_PZ47903-2741-42_YONAH

C63

4.7U_0805_10V4Z

0.1U_0402_16V4Z

ACES_85205-0200

FAN

U31
33

C65

FAN_PWM

THERM#

Q69
AO6402_TSOP6

@ ZD1
RLZ5.1B_LL34

TC7SH00FUF_SSOP5
A

+VCCP

R439
H_DPSLP#

@ 56_0402_5%

@ 56_0402_5%
R440
H_DPRSTP#

R30

OCP#
Q6
@ MMBT3904_SOT23
C

H_PROCHOT#

@ 56_0402_5%
OCP#

21,47

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

Y o n a h C PU in mFCPGA479
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

of

52

+VCCP

+VCC_CORE
R42
100_0402_1%
VCCSENSE

+1.5VS

C70
0.01U_0402_16V7K

R41
100_0402_1%
VSSSENSE
R39
2K_0402_1%

C l o s e t o C P U pin AD26
w i t h i n 5 0 0mils.

+VCC_CORE
JP8B

JP8C

YONAH

C l o s e t o CPU pin
w i t h i n 5 0 0mils.

YONAH

C P U _BSEL

C P U _ BSEL2

C P U _ BSEL1

C P U _ BSEL0

1 33

1 66

45
45
45
45
45
45
45

H_PSI#

H_PSI#

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
V_CPU_GTLREF

15
15
15

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

COMP0
COMP1
COMP2
COMP3

R473
54.9_0402_1%

R470
27.4_0402_1%

R36
54.9_0402_1%

+VCC_CORE

R35
27.4_0402_1%

VCCSENSE
VSSSENSE

+VCCP

45

P O W E R , G R O U N G , R E S ERVED SIGNALS AND NC

V_CPU_GTLREF

R37
1K_0402_1%

C72
10U_0805_10V4Z

L e n g t h m a t c h w i t hin 25 mils
T h e t r a c e w i d t h 1 8 mils space
45 VCCSENSE
7 m ils
45 VSSSENSE

P O W E R , GROUND

R e s i s t o r p laced within
0 . 5 " o f C P U pin.Trace
s h o u l d b e at least 25
m i l s a w a y from any
o t h e r t o g g ling signal.

FOX_PZ47903-2741-42_YONAH

FOX_PZ47903-2741-42_YONAH

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

Y o n a h C PU in mFCPGA479
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

of

52

+VCC_CORE

P l a c e t h e s e c a p a c i t o r s on L8
( N o r t h s i d e , S e c o n d a r y Layer)

C412

C413

C414

C415

C416

C417

C425

C479

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C411

C481

C480

C486

C418

C482

C483

C484

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

C441

C423

C432

C422

C446

C424

C445

C485

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

+VCC_CORE

P l a c e t h e s e c a p a c i t o r s on L8
( N o r t h s i d e , S e c o n d a r y Layer)

+VCC_CORE

P l a c e t h e s e c a p a c i t o r s on L8
( S o r t h s i d e , S e c o n d a r y Layer)

+VCC_CORE

P l a c e t h e s e c a p a c i t o r s on L8
( S o r t h s i d e , S e c o n d a r y Layer)

C442

C435

C436

C443

C444

C427

C426

C431

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

M i d F r e q u e n c e Decoupling

+VCC_CORE
330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

@ 820U_E9_2_5V_M_R7

S o u t h S i d e S e c o n d a ry
C408

N o r t h S i d e S e c o n d a ry
+

C409

C67

C66

C117

C125

C119

@ 330U_D2E_2.5VM_R9

+ C120

ESR <= 1.5m ohm

C a p a c i t o r > 1980uF

@ 820U_E9_2_5V_M_R7

@ 330U_D2E_2.5VM_R9

330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

+VCCP

C434
220U_D2_2VK_R9

C437

C429

C421

C438

C428

C433

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

P l a c e t h e s e i n side
s o c k e t c a v i t y o n L8
( N o r t h s ide
S e c o n d a r y)

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C P U B ypass capacitors
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

of

52

H_ADSTB#0
H_ADSTB#1

CLK_MCH_BCLK#
CLK_MCH_BCLK

4
4

CLK_MCH_BCLK# 15
CLK_MCH_BCLK 15
H_DSTBN#[0..3] 4

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_DSTBP#[0..3]

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

21
21
21
21

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

21
21
21
21

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

13
13
14
14

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

13
13
14
14

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

13
13
14
14

+1.8V

R395
24.9_0402_1%

PAD

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

M_ODT0
M_ODT1
M_ODT2
M_ODT3

CLK_MCH_3GPLL 15
CLK_MCH_3GPLL# 15

GMCH_C40
GMCH_D41
CLKREQC#

5/16

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

GMCH_A27
GMCH_A26

CLKREQC#

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

15
15
15

15

V_DDR_MCH_REF

H_RESET# 4
H_ADS# 4
H_TRDY# 4
H_DPWR# 4
H_DRDY# 4
H_DEFER# 4
H_HITM# 4
H_HIT# 4
H_LOCK# 4
H_BR0# 4
H_BNR# 4
H_BPRI# 4
H_DBSY# 4
H_CPUSLP# 4

21,45

DPRSLPVR

19,20,21,23,25,27,32,33

VGATE_INTEL
21,33 PM_POK

PM_BMBUSY#
PM_EXTTS#0
PM_EXTTS#1
H_THERMTRIP#
PWROK
PLTRST_R#
100_0402_1%

0_0402_5%

PLT_RST#
19

21,45

PM_BMBUSY#

R65
4,20

H_THERMTRIP#
R408
MCH_ICH_SYNC#

R597
R590

@ 0_0402_5%
0_0402_5%

PWROK
CALISTOGA_A2_FCBGA1466

+3VS

Layout Note:
V _ D D R _ M C H _ R EF
t r a c e w i d t h a nd
s p a c i n g i s 2 0 / 2 0.

H_RS#0
H_RS#1
H_RS#2
H_RS#[0..2]

PAD
PAD

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_ODT0
M_ODT1
M_ODT2
M_ODT3

PAD

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
T1
T2
CFG5 11
T4
CFG7 11
T3
CFG9 11
T7
CFG11 11
CFG12 11
CFG13 11
T6
T5
CFG16 11
T8
CFG18 11
CFG19 11
CFG20 11

80.6_0402_1% SMRCOMPN
SMRCOMPP
80.6_0402_1%

R413

4
4
4
4

CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_OCDOCMP0
M_OCDOCMP1

21

H_RESET#
H_ADS#
H_TRDY#
H_DPWR#
H_DRDY#
H_DEFER#
H_HITM#
H_HIT#
H_LOCK#
H_BR0#
H_BNR#
H_BPRI#
H_DBSY#
H_CPUSLP#

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

R419
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
CFG3
PAD
CFG4
PAD
CFG5
CFG6
PAD
CFG7
CFG8
PAD
CFG9

CFG

21
21
21
21

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

CLK

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

13
13
14
14

21
21
21
21

PM

R350
54.9_0402_1%

H_REQ#[0..4]

H_ADSTB#0
H_ADSTB#1

H_VREF
H_XRCOMP
H_XSCOMP
H_YRCOMP
H_YSCOMP
H_SWNG0
H_SWNG1
R339
24.9_0402_1%

13
13
14
14

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

D e s c r i p t i o n at page11.

U4B

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H _ X S COMP/H_YSCOMP trace
w i d t h and spacing is 5/20.

DDR MUXING

+VCCP

DMI

R381
54.9_0402_1%

H_A#[3..31]

U4A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

NC

H_D#[0..63]

HOST

RESERVED

Layout Note:
R o u t e a s s h o rt
as possible

R353
PM_EXTTS#0
10K_0402_5%
R362

PM_EXTTS#1
+1.8V

CALISTOGA_A2_FCBGA1466

@ 10K_0402_5%8/24
M_OCDOCMP0
M_OCDOCMP1

R409

R15
GMCH_A27
10K_0402_5%

@ 100_0402_1%

L a y o u t Note:
H _ X R C O M P / H _ Y R C O M P / H_VREF / H_SWNG0 /
H _ S W N G 1 t r a c e w i d t h and spacing is 18/20.

R14

R17

221_0603_1%

R351

R360

100_0402_1%

H_SWNG0

V_DDR_MCH_REF

GMCH_A26
R412
R411

R400

40.2_0402_1%

40.2_0402_1%

10K_0402_5%
R342
GMCH_D41
10K_0402_5%
R343

0.1U_0402_16V4Z
C359

R18

R338
GMCH_C40

H_SWNG1
100_0402_1%

0.1U_0402_16V4Z
C328

R344

100_0402_1%

0.1U_0402_16V4Z

C330

200_0402_1%

10K_0402_5%

@ 100_0402_1%

13,14

H_VREF

R348

+VCCP

221_0603_1%

+VCCP
+VCCP

V_DDR_MCH_REF

C385
0.1U_0402_16V4Z

13,14,44

DDR_THERM#

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

Compal Electronics, Inc.

Title

C a l i stoga (1/6)
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

PM_EXTTS#0
0_0402_5%

S t u f f R 1 2 0 2 & R 1 2 03 for A1 Calistoga

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDR_THERM#

Saturday, January 14, 2006

Sheet
1

of

52

U4D

13

DDR_A_DM[0..7]

DDR_A_DQS[0..7]

13

13

DDR_A_DQS#[0..7]

DDR_A_MA[0..13]

U4E

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

13 DDR_A_CAS#
13 DDR_A_RAS#
13 DDR_A_WE#
T11 PAD
T12 PAD

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
SA_RCVENIN#
SA_RCVENOUT#

DDR_A_D[0..63]

13
14
14
14
14

14

14

14

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM[0..7]

DDR_B_DQS[0..7]

D D R _B_DQS#[0..7]

DDR_B_MA[0..13]

14 DDR_B_CAS#
14 DDR_B_RAS#
14 DDR_B_WE#
T9 PAD
T10 PAD

DDR_B_BS#0
DDR_B_BS#1
DDR_B_BS#2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
SB_RCVENIN#
SB_RCVENOUT#

CALISTOGA_A2_FCBGA1466

DDR_B_D[0..63]

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR SYS MEMORY B

13

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

DDR SYS MEMORY A

13
13
13

14

CALISTOGA_A2_FCBGA1466

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C a l i stoga (2/6)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

of

52

P E G C O MP trace width
a n d spacing is 18/25 mils.

U4C

+1.5VS_PCIE
R331
24.9_0402_1%

PEGCOMP
P E G _RXP[0..15] 18

LVDS

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

+1.5VS

TV

10K_0402_5%
10K_0402_5%

CRT

R363
R355

PCI-EXPRESS GRAPHICS

PEG_RXN[0..15]

18

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

+VCCP

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

C22
C24
C26
C30
C32
C34
C37
C41
C45
C47
C49
C51
C53
C56
C58
C61

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXP15
PEG_M_TXP14
PEG_M_TXP13
PEG_M_TXP12
PEG_M_TXP11
PEG_M_TXP10
PEG_M_TXP9
PEG_M_TXP8
PEG_M_TXP7
PEG_M_TXP6
PEG_M_TXP5
PEG_M_TXP4
PEG_M_TXP3
PEG_M_TXP2
PEG_M_TXP1
PEG_M_TXP0

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

C20
C23
C25
C28
C31
C33
C35
C38
C43
C46
C48
C50
C52
C54
C57
C60

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEG_M_TXN15
PEG_M_TXN14
PEG_M_TXN13
PEG_M_TXN12
PEG_M_TXN11
PEG_M_TXN10
PEG_M_TXN9
PEG_M_TXN8
PEG_M_TXN7
PEG_M_TXN6
PEG_M_TXN5
PEG_M_TXN4
PEG_M_TXN3
PEG_M_TXN2
PEG_M_TXN1
PEG_M_TXN0

PEG_M_TXP[0..15]

18

PEG_M_TXN[0..15]

18

CALISTOGA_A2_FCBGA1466

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C a l i stoga (3/6)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

of

52

U4H
+VCCP

+ 1 . 5 VS_PCIE
R410

W = 40 mils

1 0 U _ 0 8 0 5 _6.3V6M
0 _ 0 8 0 5_5%

C297

C315

2 2 0 U _ D 2 _ 4VM_R25

1 0 U _ 0 8 0 5 _ 6.3V6M

9/ 15

+ 1 . 5 V S_3GPLL
+2.5VS

2 2 0 U _ D 2 _2VK_R9

C329
0.1U_0402_16V4Z

C42

+ 1 . 5VS

C380

+ 2 . 5VS

J5
M C H _ C R TDAC

+VCCP
P A D - S H O R T 2x2m
J4
+ 2 . 5VS

P A D - N o S H ORT 2x2m
R333
0 _ 0 8 0 5_5%

c l ose pin G41

+ 1 . 5 V S_HPLL
R356
0 _ 0 8 0 5_5%

P O W E R

C368
2.2U_0805_16V4Z

C339
4.7U_0805_10V4Z

+ 1 . 5 V S_MPLL

PCI-E/MEM/PSB PLL decoupling

+1.5VS

+ 1 . 5 V S _3GPLL

+1.5VS

+ 1 . 5VS
R398

+ 1 . 5 V S _TVDAC

+1.5VS

R396

R332
@ 0 . 0 2 2 U _ 0 4 02_16V7K

0 . 5 _ 0 8 0 5_1%

C371

0 _ 0 8 0 5_5%

C378

C387

1 0 U _ 0 8 0 5 _ 6.3V6M

+1.5VS

0 _ 0 8 0 5_5%

C324

C316

C319

@ 0 . 1 U _ 0 4 0 2 _16V4Z

@ 0 . 0 2 2 U _ 0 4 02_16V7K

0 . 1 U _ 0 4 0 2 _16V4Z

@ 1 0 U _ 0 8 0 5 _ 6.3V6M

+ 1 . 5 V S_TVDAC
+ 1 . 5 V S_MPLL

C317
0.47U _ 0 6 0 3 _ 1 0 V 7 K

M C H _A6
C322
0.1U_0402_16V4Z

R22

4 5mA Max.

+1.5VS

0 _ 0 8 0 5_5%

4 5mA Max.

+ 1 . 5VS

0 _ 0 8 0 5_5%

C320
1 0 U _ 0 8 0 5 _ 6.3V6M

C373
0 . 1 U _ 0 4 0 2 _16V4Z

C62

C374

1 0 U _ 0 8 0 5 _ 6.3V6M

C59

0 . 1 U _ 0 4 0 2 _16V4Z

1 0 U _ 0 8 0 5 _6.3V6M

C377
0.1U_0402_16V4Z

+1.5VS

C55
0.47 U _ 0 6 0 3 _ 1 0 V 7 K
MCH_AB1

M C H _ D2
C318
0.22U _ 0 6 0 3 _ 1 0 V 7 K

C336
0.22U _ 0 6 0 3 _ 1 0 V 7 K

+ 1 . 5 V S_HPLL
R23

+3VS

+ 1 . 5VS

C A L I S T O G A _ A 2_FCBGA1466

Compal Secret Data

S e c u rity Classification
2005/03/10

I ssued Date

C o m p a l Electronics, Inc.
2006/03/10

D eciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R ADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A RTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MA Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Calistoga (4/6)
L A - 2 821P
D a te:

1.0

S a t u r d a y , J a n u a r y 14, 2006

S h eet
1

10

of

52

Stra p Pin Table

C F G [ 3 : 1 7 ] h a v e i n t e r n a l p u l l up
+VCCP

U4F

+VCCP

+1.5VS

C F G [ 1 9 : 1 8 ] h a v e i n t e r n a l p u l l d own

+1.8V

U4G

VCCSM_LF4
VCCSM_LF5
C395
0.47U_0603_10V7K

C389
0.47U_0603_10V7K

C375
0.22U_0603_10V7K

C333
0.22U_0603_10V7K

C367
0.22U_0603_10V7K

011
001

C F G [2:0]
C FG5

0 = R eserved
1 = M o b i l e Yonah CPU *( D e f ault)
0 = L a n e R e v ersal Enable *
1 = N o r m a l Operation ( D e f ault)

C FG7
C FG9

1 = C a listoga *
0 = R eserved
00
01
10
11

C F G [ 13:12]

10U_0805_6.3V6M

C388

0.1U_0402_16V4Z

C384

0.1U_0402_16V4Z

P O W E R

0.1U_0402_16V4Z

C382

P O W E R

C343
1U_0603_10V4Z

10U_0805_6.3V6M

C381

0.1U_0402_16V4Z

+1.8V

C338

C F G18

0 = 1.05V *( D e f ault)
1 = 1.5V

C F G19

0 = N o r m a l Operation
( D e f ault)
1 = D M I L a n e Reversal* Enable
0 = N o S D V O Device Present *
( D e f ault)
1 = S D V O D e vice Present

C F G20

C406
0.47U_0603_10V7K

C64

P l a c e n e a r pin BA23

C407

C405

+ C402
@ 220U_D2_4VM

CFG5

CFG7

CFG9

CFG11

CFG12

CFG13

CFG16

0 = O n l y P C IE or SDVO is
o p e r a tional. *( D e f ault)
1 = P C I E / S D V O are operating
s i mu.

R349

2.2K_0402_5%

R340

2.2K_0402_5%

R354

2.2K_0402_5%

R341

2.2K_0402_5%

R365

2.2K_0402_5%

R371

2.2K_0402_5%

R359

2.2K_0402_5%

R370
R368
R369

@ 1K_0402_5%
@ 1K_0402_5%
@ 1K_0402_5%

10U_0805_6.3V6M
10U_0805_6.3V6M

@ w a i t DB-1 test verify

@ 330U_D2E_2.5VM_R9

+3VS
C404
0.47U_0603_10V7K

Reserved
X O R Mode Enabled
A l l Z Mode Enabled
N o r m al Operation *( D e f ault)

0 = D y n a m i c ODT Disabled
1 = D y n a m i c ODT Enabled * ( D e f ault)

( P C I E / S D VO select)

220U_D2_2VK_R9

=
=
=
=

C F G16

S D V O _ C TRLDATA

C386

(Accor d i n g t o I n t e l N a p a S c h e m a t i c C h e c k l i s t & C R B
Rev1. 5 0 2 d o c u m e n t 2 . 2 K o h m p u l l - d o w n r e s i s t o r n o r e q u e s t )

C F G11
P l a c e n e a r p in AT41 & AM41

C337

= 6 67MT/s FSB
= 5 33MT/s FSB

0 = D MI x 2
1 = D MI x 4 * ( D e f ault)

+VCCP
+1.8V

CALISTOGA_A2_FCBGA1466

C398
0.47U_0603_10V7K

C390
0.47U_0603_10V7K

VCCSM_LF2
VCCSM_LF1

7
7
7

CFG18
CFG19
CFG20

P l a c e n e a r pin BA15

P l a c e n e a r pin AV1 & AJ1

CALISTOGA_A2_FCBGA1466

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C a l i stoga (5/6)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

11

of

52

U4I

U4J

P O W E R
P O W E R
C

CALISTOGA_A2_FCBGA1466

CALISTOGA_A2_FCBGA1466

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C a l i stoga (6/6)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

12

of

52

+1.8V
8

+1.8V
V_DDR_MCH_REF

DDR_A_DQS#[0..7]

DDR_A_MA[0..13]

DDR_A_D0
DDR_A_D4

DDR_A_DM0
DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D5
DDR_A_D6

DDR_A_D2
DDR_A_D3

L a yout Note:
P l ace near JP34

7,14,44

C92

D D R _A_DQS[0..7]

V_DDR_MCH_REF

C97

DDR_A_DM[0..7]

DDR_A_D7
DDR_A_D1

0.1U_0402_16V4Z

JP9

DDR_A_D[0..63]

2.2U_0805_16V4Z

DDR_A_D12
DDR_A_D13

DDR_A_D8
DDR_A_D14

DDR_A_DM1

DDR_A_DQS#1
DDR_A_DQS1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D10
DDR_A_D11

DDR_A_D9
DDR_A_D15

DDR_A_D21
DDR_A_D17

DDR_A_D20
DDR_A_D16

DDR_A_DQS#2
DDR_A_DQS2

DDR_THERM#
DDR_A_DM2

DDR_A_D22
DDR_A_D19

DDR_A_D18
DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_D29
DDR_A_D28

DDR_A_DM3

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D27
DDR_A_D30

DDR_A_D26
DDR_A_D31

DDR_CKE0_DIMMA

DDR_CKE1_DIMMA

M_CLK_DDR0 7
M_CLK_DDR#0 7

+1.8V

C95

C91

0.1U_0402_16V4Z

DDR_CKE0_DIMMA
8

L a yout Note:
P l a c e o n e cap close to every 2 pullup
r e s i stors terminated to +0.9V

DDR_A_BS#2

8 DDR_A_BS#0
8 DDR_A_WE#

+0.9V
7

8 DDR_A_CAS#
DDR_CS1_DIMMA#
M_ODT1

C114

C113

0.1U_0402_16V4Z

C112

0.1U_0402_16V4Z

C110

0.1U_0402_16V4Z

C111

0.1U_0402_16V4Z

C115

0.1U_0402_16V4Z

C84

0.1U_0402_16V4Z

C82

0.1U_0402_16V4Z

C81

0.1U_0402_16V4Z

C80

0.1U_0402_16V4Z

C78

0.1U_0402_16V4Z

C79

0.1U_0402_16V4Z

C83

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_CAS#
DDR_CS1_DIMMA#

M_ODT0
DDR_A_MA13

DDR_A_MA5
DDR_A_MA8
RP7
DDR_A_MA1
DDR_A_MA3

56_0404_4P2R_5% RP18 56_0404_4P2R_5%

DDR_A_MA7
DDR_A_MA6

RP15 56_0404_4P2R_5% RP12 56_0404_4P2R_5%

DDR_A_RAS#
DDR_A_MA9
DDR_CS0_DIMMA#
DDR_A_MA12
DDR_A_BS#0
DDR_A_MA10

DDR_A_D34
DDR_A_D38

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_DM4

RP9
DDR_A_CAS#
DDR_A_WE#

56_0404_4P2R_5% RP16 56_0404_4P2R_5%

DDR_A_MA0
DDR_A_BS#1

RP8
DDR_CS1_DIMMA#
M_ODT1

56_0404_4P2R_5% RP14 56_0404_4P2R_5%

M_ODT0
DDR_A_MA13

4,14,15,18,21,25,27
4,14,15,18,21,25,27

ICH_SMBDATA
ICH_SMBCLK

DDR_A_D40
DDR_A_D44

DDR_A_DM5

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D42
DDR_A_D43

DDR_A_D47
DDR_A_D46

DDR_A_D52
DDR_A_D53

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_DM6

DDR_A_D51
DDR_A_D55

DDR_A_D50
DDR_A_D54

DDR_A_D56
DDR_A_D61

DDR_A_D60
DDR_A_D57

DDR_A_DM7

DDR_A_DQS#7
DDR_A_DQS7

M_CLK_DDR1 7
M_CLK_DDR#1 7

DDR_A_D62
DDR_A_D63

ICH_SMBDATA
ICH_SMBCLK
+3VS
C96
0.1U_0402_16V4Z

56_0404_4P2R_5% RP19 56_0404_4P2R_5%

DDR_CKE1_DIMMA
DDR_A_MA11

FOX_ASOA426-M4R-TR

SO-DIMM A
R E VERSE

Top side
Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

D D R I I - SODIMM SLOT1
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

DDR_A_D37
DDR_A_D32

DDR_A_D58
DDR_A_D59

RP10 56_0404_4P2R_5% RP17 56_0404_4P2R_5%

DDR_A_MA4
DDR_A_MA2

DDR_A_BS#1 8
DDR_A_RAS# 8
DDR_CS0_DIMMA#
M_ODT0

M_CLK_DDR1
M_CLK_DDR#1

L a yout Note:
P l a c e these resistor
c l osely JP34,all
t r a c e length Max=1.5"

RP13 56_0404_4P2R_5%
DDR_A_BS#2
DDR_CKE0_DIMMA

M_ODT1

R40
10K_0402_5%

RP11

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_D45
DDR_A_D41

+0.9V

DDR_CKE1_DIMMA

DDR_A_BS#2

DDR_A_D39
DDR_A_D35

7,14

R38
10K_0402_5%

0.1U_0402_16V4Z

C93

0.1U_0402_16V4Z

C105

C464

0.1U_0402_16V4Z

C462

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C463

2.2U_0805_16V4Z

C461

2.2U_0805_16V4Z

C467

2.2U_0805_16V4Z

DDR_THERM#

Saturday, January 14, 2006

Sheet
1

13

of

52

DDR_B_DQS#[0..7]
8

DDR_B_D[0..63]

DDR_B_DM[0..7]

DDR_B_D4
DDR_B_D1

DDR_B_D0
DDR_B_D5

DDR_B_DM0
DDR_B_DQS#0
DDR_B_DQS0
D

DDR_B_D6
DDR_B_D2

DDR_B_D7
DDR_B_D3

L a yout Note:
P l ace near JP34

7,13,44

C103

D D R _B_MA[0..13]

V_DDR_MCH_REF

C99

V_DDR_MCH_REF
JP29

0.1U_0402_16V4Z

D D R _B_DQS[0..7]

+1.8V

2.2U_0805_16V4Z

+1.8V

DDR_B_D12
DDR_B_D13

DDR_B_D8
DDR_B_D9

DDR_B_DM1

DDR_B_DQS#1
DDR_B_DQS1

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_D10
DDR_B_D11

DDR_B_D14
DDR_B_D15

DDR_B_D21
DDR_B_D20

DDR_B_D16
DDR_B_D18

DDR_B_DQS#2
DDR_B_DQS2

DDR_THERM#
DDR_B_DM2

DDR_B_D22
DDR_B_D23

DDR_B_D17
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D28

DDR_B_DM3

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_B_D29
DDR_B_D27

DDR_CKE2_DIMMB

DDR_CKE3_DIMMB

M_CLK_DDR3 7
M_CLK_DDR#3 7

+1.8V

C454

C106

0.1U_0402_16V4Z

C455

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C94

C107

0.1U_0402_16V4Z

C466

2.2U_0805_16V4Z

C460

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C108

2.2U_0805_16V4Z

C109

2.2U_0805_16V4Z

L a yout Note:
P l a c e o n e cap close to every 2 pullup
r e s i stors terminated to +0.9V

DDR_CKE2_DIMMB
8

+0.9V

8
8

DDR_B_BS#0
DDR_B_WE#

8 DDR_B_CAS#
DDR_CS3_DIMMB#
7

M_ODT3

C471

C472

0.1U_0402_16V4Z

C473

0.1U_0402_16V4Z

C474

0.1U_0402_16V4Z

C475

0.1U_0402_16V4Z

C476

0.1U_0402_16V4Z

C477

0.1U_0402_16V4Z

C90

0.1U_0402_16V4Z

C89

0.1U_0402_16V4Z

C88

0.1U_0402_16V4Z

C87

0.1U_0402_16V4Z

C86

0.1U_0402_16V4Z

C85

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_B_BS#2

L a yout Note:
P l a c e these resistor
c l osely JP10,all
t r a c e length Max=1.5"

RP34
DDR_B_MA1
DDR_B_MA3

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_BS#1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_CAS#
DDR_CS3_DIMMB#

M_ODT2
DDR_B_MA13

RP35 56_0404_4P2R_5% RP6

RP3
DDR_B_MA0
DDR_B_BS#1
RP2

56_0404_4P2R_5% RP33 56_0404_4P2R_5%

DDR_B_MA5
DDR_B_MA8
56_0404_4P2R_5% RP5

DDR_B_RAS#
DDR_CS2_DIMMB#
RP36 56_0404_4P2R_5% RP4

DDR_B_D37
DDR_B_D36

DDR_B_D33
DDR_B_D32

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_DM4

56_0404_4P2R_5%
DDR_B_MA4
DDR_B_MA2

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D42
DDR_B_D47

DDR_B_D43
DDR_B_D46

DDR_B_D48
DDR_B_D53

DDR_B_D49
DDR_B_D52

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_DM6

DDR_B_D51
DDR_B_D50

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_D56
DDR_B_D57

DDR_B_DM7

DDR_B_DQS#7
DDR_B_DQS7

M_CLK_DDR2 7
M_CLK_DDR#2 7

DDR_B_D62
DDR_B_D63

ICH_SMBDATA
ICH_SMBCLK

R33
+3VS

+3VS
C453

56_0404_4P2R_5% RP1

DDR_B_DM5

RP37
DDR_CS3_DIMMB#
M_ODT3

56_0404_4P2R_5%
M_ODT2
DDR_B_MA13

0.1U_0402_16V4Z

56_0404_4P2R_5% RP31

FOX_ASOA426-M2RN-7F

SO- DIMM B
STANDA RD

10K_0402_5%

Bottom side

DDR_B_BS#2
DDR_CKE2_DIMMB

Compal Secret Data

S e c u r i t y C l a s s ification

56_0404_4P2R_5%

2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

D D R I I - SODIMM SLOT2
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

DDR_B_D44
DDR_B_D45

R34

DDR_B_CAS#
DDR_B_WE#

4,13,15,18,21,25,27 ICH_SMBDATA
4,13,15,18,21,25,27 ICH_SMBCLK

DDR_B_BS#1 8
DDR_B_RAS# 8
DDR_CS2_DIMMB#

DDR_B_D38
DDR_B_D39

DDR_B_D58
DDR_B_D59

56_0404_4P2R_5% 5/16
DDR_B_MA6
DDR_B_MA11

M_ODT3

10K_0402_5%

56_0404_4P2R_5% 5/16
DDR_B_MA7
DDR_CKE3_DIMMB

DDR_CKE3_DIMMB

M_ODT2 7

M_CLK_DDR2
M_CLK_DDR#2

RP32 56_0404_4P2R_5%
DDR_B_MA9
DDR_B_MA12

DDR_B_BS#0
DDR_B_MA10

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8

DDR_B_D40
DDR_B_D41

+0.9V

7,13

DDR_B_BS#2

DDR_B_D35
DDR_B_D34
B

DDR_THERM#

Saturday, January 14, 2006

Sheet
1

14

of

52

+CK_VDD_MAIN1

F S LC

F S LB

F S LA

CLKSEL2

CLKSEL1

CLKSEL0

C PU
M Hz

S RC
M Hz

P CI
M Hz

1 33

1 00

3 3.3

1 66

1 00

3 3.3

+3VS

R502

0_0805_5%
C452

C451

C449

C468

10U_0805_10V4Z

.01U_0402_16V7K

.01U_0402_16V7K

.01U_0402_16V7K

C496

C430

C495

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

R548
2.2_0805_1%

C470

C465

C450

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+CK_VDD_MAIN2
R454
CK_VDD_REF

+3VS

T a b l e : ICS954306

R453

0_0805_5%

1_0805_1%
CK_VDD_48

F S B F r e q u e n c y Selet:
S t uff

C L K_Ra

C L K_Rb

C L K_Rc

N o Stuff

C L K_Rd

C L K_Re

C L K_Rf

P l a c e crystal within
5 0 0 mils of CK410

R506

C P U Driven

* ( D e f ault)

+CK_VDD_DP
+3VS

NODP@ 0 _ 0 8 0 5 _ 5 %
C457
R508

S t uff

C L K_Rd

C L K_Re

C L K_Rf

+VCCP

5 3 3MHz
N o Stuff

C L K_Ra

C L K_Rb

S t uff

C L K_Rd

C L K_Rf

N o Stuff

C L K_Ra

C L K_Rb

10U_0805_10V4Z
DP@

0_0805_5%

C439
+CK_VDD_DP

C L K_Rc

+CK_VDD_MAIN1

Y6
14.31818MHZ_20P_6X1430004201

CLK_XTAL_IN

6 6 7MHz

CK_VDD_48

CLK_XTAL_OUT

C469

C L K_Rc

+CK_VDD_DP
0.1U_0402_16V4Z
R474
CLKIREF
0_0402_5%
C448

C L K_Re
DP@

+VCCP

C440

C447

R527

0_0402_5%

R517

0_0402_5%

R o u t i n g the trace at least 10mil

0.1U_0402_16V4Z

R475
CK_VDD_REF

R550
8.2K_0402_5%

CPU_BSEL0

R476

MCH_CLKSEL0

21 CLK_48M_ICH
24 C L K _ 4 8 M _ C B

R538

12_0402_5%

MCH_BCLK

FSA
12_0402_5%
FSB

MCH_BCLK#

R551

CLK_48M_ICH
CLK_48M_CB

R477

R576
1K_0402_5%

R575
0_0402_5%

CPU_BCLK#

0.1U_0402_16V4Z

C L K_Rd

FSA

DP@

21

C L K_Ra

CLK_14M_ICH

CLK_14M_ICH

R478

11/21

CLKREF1

R489
33_0402_5%

R510

CLK_CPU_BCLK
24_0402_5%
CLK_CPU_BCLK#
24_0402_5%
CLK_MCH_BCLK
24_0402_5%
CLK_MCH_BCLK#
24_0402_5%

PCIE_MXM
LPNO@ 4.7K_0402_1%

R472

CLKIREF

R552
PCIE_MXM#

37,45

1K_0402_5%

CPU_BSEL1

R565
0_0402_5%

R541
PCI_ICH
R534
33_0402_5%
R496
12_0402_5%
CLKREF0

CLK_14M_KBC
CLK_14M_SIO

@ R539

R498

+3VS
CLK_PCI_EC

0_0402_5%

C L K_Re

32

CLK_PCI_TCG

23

CLK_PCI_PCM

PCIE_SATA
R558
PCIE_SATA#
R559

33

C L K_Rb

PCIE_LOM#

CLK_PCI_ICH

33 CLK_14M_KBC
31 CLK_14M_SIO
MCH_CLKSEL1

PCIE_LOM

CLK_ENABLE#

CLK_PCI_ICH

R564
1K_0402_5%

R553
R540

CLK_ENABLE#

19

R566

FSB

H_STP_CPU#
H_STP_PCI#

21 H_STP_CPU#
21 H_STP_PCI#

+VCCP

11/14

12_0402_5%
PCI_MINI
PCI_CLK3

10K_0402_5%
@ 10K_0402_5%
33_0402_5%

R513
R532
R528

PCI_EC

33_0402_5%

R519

PCI_CLK5

33_0402_5%

R533

PCI_PCM

CLKREQB#
R507

R542
PCIE_DOCK#
4,13,14,18,21,25,27

+VCCP

4,13,14,18,21,25,27

ICH_SMBDATA

ICH_SMBDATA

R543

ICH_SMBCLK

ICH_SMBCLK

CPU_BSEL2

MCH_CLKSEL2

R491
1K_0402_5%

31

CLK_PCI_SIO

27

CLK_PCI_DB

CLK_MCH_BCLK#

@ 10K_0402_5%
CLKREQA#

CLKREQA#

CLK_PCIE_MXM
24_0402_5%
CLK_PCIE_MXM#
24_0402_5%

+3VS

R518

12_0402_5%

R531

DB@

PCI_CLK3

12_0402_5%

CLK_PCIE_LOM
24_0402_5%
CLK_PCIE_LOM#
24_0402_5%
CLK_PCIE_SATA
24_0402_5%
CLK_PCIE_SATA#
24_0402_5%
CPPE#
10K_0402_5%

CLK_PCIE_LOM

25

CLK_PCIE_SATA

20

CLK_PCIE_SATA#

R554
CLK_PCIE_LOM#
R555

+3VS

R537

@ 49.9_0402_1%

@ 49.9_0402_1%
@ 49.9_0402_1%
@ 49.9_0402_1%
@ 49.9_0402_1%

CLK_PCIE_SATA
R567
CLK_PCIE_SATA#
R568

20

@ 49.9_0402_1%
@ 49.9_0402_1%

19,35

CLK_PCIE_DOCK

35

CLK_PCIE_DOCK#

NOXDP@10K_0402_5%

CLKREQD#
R 4 5 5 NOXDP@0 _ 0 4 0 2 _ 5 %
CPU_XDP#
CLK_CPU_XDP#
R481
XDP@ 3 3 _ 0 4 0 2 _ 5 %
PCIE_MCARD
CLK_PCIE_MCARD
R482
24_0402_5%
PCIE_MCARD#
CLK_PCIE_MCARD#
R483
24_0402_5%

P i n 4 4 / 4 5 f u nction select

@ 49.9_0402_1%

CLK_PCIE_LOM

25

CLK_PCIE_LOM#

CPPE#

CLK_PCIE_DOCK
24_0402_5%
CLK_PCIE_DOCK#
24_0402_5%

R451

X D P @ : m e a n s j u s t build when XDP function enable.

W h e n t h i s t i m e , d ocking PCI express will not work.

+3VS

@ 49.9_0402_1%

R562
CLK_PCIE_MXM#
R563

18

35

CLK_MCH_3GPLL
R466
CLK_MCH_3GPLL#
R467

@ 49.9_0402_1%

CLK_PCIE_MCARD
R464
CLK_PCIE_MCARD#
R465

@ 49.9_0402_1%
B

@ 49.9_0402_1%

R468

@ 49.9_0402_1%

R469

@ 49.9_0402_1%

R462

@ 49.9_0402_1%

R463
CLK_PCIE_DOCK
R556
CLK_PCIE_DOCK#
R557

@ 49.9_0402_1%

CLK_PCIE_ICH#

CLK_CPU_XDP
CLK_CPU_XDP#

+3VS

CLKREQD#

@ 49.9_0402_1%

CLK_PCIE_ICH

N O X D P @ : m e a n s j u s t build when XDP function disable.

L C D ( L o w ) / SRC(High)
c l o c k select

CLK_MCH_BCLK
R459
CLK_MCH_BCLK#
R460

CLK_PCIE_MXM

18

CLK_PCIE_MXM#

0_0402_5%

C L K_Rf

@ 49.9_0402_1%

18,25

CLK_PCIE_MXM

CLK_PCIE_ICH
CLK_PCIE_ICH 21
24_0402_5%
PCIE_ICH#
CLK_PCIE_ICH#
CLK_PCIE_ICH# 21
R487
24_0402_5%
R461
NOXDP@10K_0402_5%
+3VS
CLKREQC#
CLKREQC# 7
R 4 7 9 NOXDP@0 _ 0 4 0 2 _ 5 %
CPU_XDP
CLK_CPU_XDP
CLK_CPU_XDP 4
R480
XDP@ 3 3 _ 0 4 0 2 _ 5 %
MCH_3GPLL
CLK_MCH_3GPLL
CLK_MCH_3GPLL 7
R484
24_0402_5%
MCH_3GPLL#
CLK_MCH_3GPLL#
CLK_MCH_3GPLL# 7
R485
24_0402_5%

C L K_Rc
@ R493

CLK_MCH_BCLK 7

CLK_CPU_BCLK
R457
CLK_CPU_BCLK#
R458

R486

1K_0402_5%

R492
0_0402_5%

PCIE_ICH

R490
R494
8.2K_0402_5%
CLKREF1

CLK_CPU_BCLK#

11/14
PCIE_DOCK

CLK_CPU_BCLK

+3VS

R561
1K_0402_5%

P l ace near U25

P l a ce these components
n e a r each pin within 40
mils.

27P_0402_50V8J

R o u t i n g the trace at least 10mil

CPU_BCLK
@ R560
56_0402_5%

27P_0402_50V8J

U30

@ 49.9_0402_1%
@ 49.9_0402_1%

27

CLK_CPU_XDP#

CLK_PCIE_MCARD
CLK_PCIE_MCARD#

I f L P Chip stuff, all 49.9_0402

c o u l d be removed .

27
27

@ 10K_0402_5%
A

R535

R501

10K_0402_5%

NOXDP@10K_0402_5%

CLK_ENABLE#
R549

ICS954306BGLFT_TSSOP64
PCI_ICH

PCI_MINI

* I n t e r n a l P u l l - U p R e sistor
* * I n t e r n a l P u l l - D o w n R e sistor

300_0402_5%
R536

R504

@ 10K_0402_5%

XDP@ 10K_0402_5%

J14

/19 = 100MHz
*HL io gw h: :P Pi in n1 18 8/19
= 96MHz

H i g h : P i n 4 4 /45 = CLKREQ

*L o w : P i n 4 4 / 4 5 = CPUCLK2_ITP

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date
@ PAD-No SHORT 2x2m

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C l o c k generator
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

15

of

52

+5VS

+RCRT_VCC
F1

CRT Connector

+CRTVDD

D3
BLUE
GREEN
RED

W = 4 0 m i ls
1.1A_6VDC_FUSE

CH491D_SC59
C420

12/02

0.1U_0402_16V4Z

C293

+5VS

18

M_HSYNC

C294

C76
0_0603_5%
R26
@ 18P_0402_50V8J
0_0603_5%

18

M_VSYNC

0.1U_0402_16V4Z

U24
SN74AHCT1G125GW_SOT353-5
HSYNC

RED_R

@ 150_0402_1%

0_0603_5%
R29

@
0.1U_0402_16V4Z

C73

GREEN_R
BLUE_R

C75
+3VS

@ 18P_0402_50V8J
FOX_DZ11A91-L7
@ 18P_0402_50V8J

R312
D_HSYNC
0_0603_5%
R310

VSYNC

D_HSYNC

35

D_VSYNC

35

D_VSYNC

+CRTVDD +CRTVDD

0_0603_5%
U23
SN74AHCT1G125GW_SOT353-5
C326
@ 5P_0402_50V8C

C325

R446

@ 5P_0402_50V8C

R445

2.2K_0402_5%

2.2K_0402_5%

R308
G

R306

R664
@1 5 0 _ 0 4 0 2 _ 1 %

R449
2.2K_0402_5%

+5VS

R666

R31
RED

RED

C77
5P_0402_50V8C

35

R665

@1 5 0 _ 0 4 0 2 _ 1 %

R450
2.2K_0402_5%

JP7
GREEN

GREEN

C71
5P_0402_50V8C

35

BLUE

BLUE

C74
5P_0402_50V8C

35

BSS138_SOT23

P l a c e c l oce to MXM connector JP39

D_DDCCLK

D_DDCCLK

M_DDCCLK
Q67

35

M_DDCDATA

18

M_DDCDATA
Q68

D_DDCDATA

D_DDCDATA

35

51K_0402_5% 51K_0402_5%

M _ D D C C L K 18

BSS138_SOT23

P l a c e c l oce to MXM connector JP39

TV-Out Connector
L

P l a c e c l o ce to TV-Out connector JP1

+3VS
D7
D6
D8
@ DAN217_SC59 @ DAN217_SC59 @ DAN217_SC59

JP10

18,35

M_LUMA

18,35
18,35

M_CRMA
M_COMP

M_LUMA

R545

0_0603_5%

M_LUMA_R

M_CRMA
M_COMP

R516
R529

0_0603_5%
0_0603_5%

M_CRMA_R
M_COMP_R
SUYIN_33007SR-07T1-C

C478
@ 18P_0402_50V8J

C459

C488

P l a c e c l o ce to TV-Out connector JP1

@ 18P_0402_50V8J
@ 18P_0402_50V8J

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

C R T & TVout Connector

Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

16

of

52

M X M LVDS CONN

L CD POWER CIRCUIT

B+_LCD
C286

0.1U_0603_50V4Z

LCDVDD

C287

R307

KC FBM-L11-201209-221LMA30T_0805
+3VS

100_0402_1%

M_TXB2+ 18
M_TXB2- 18

LCDVDD
18

J2

LID_SW#
ALS_EN

18
18

47K_0402_5%

0.047U_0402_16V7K
C288

+5VS_INV
M_LCD_CLK
M_LCD_DAT

C12

C289

4.7U_0805_10V4Z

@ 4.7U_0805_10V4Z

Q56
DTC124EK_SC59

M_TXACLK+ 18
M_TXACLK- 18

INV_PWM
@ PAD-No SHORT 2x2m

R315

M_TXB0+ 18
M_TXB0- 18

PAD-SHORT 2x2m
21,34 LID_SW#
19 ALS_EN

1M_0402_5%
C298

G
S

M_PWM

33

Q55
2N7002_SOT23

M_TXB1+ 18
M_TXB1- 18

J1

R309

M_TXBCLK+ 18
M_TXBCLK- 18

B+

JP3

68P_0402_50V8J
L13

+3VALW
Q1
AO3413_SOT23

LCDVDD

M_TXA2+ 18
M_TXA2- 18

18

M_ENAVDD

M_ENAVDD

0.1U_0402_16V4Z

M_TXA1+ 18
M_TXA1- 18
M_TXA0+ 18
M_TXA0- 18
ACES_87216-5002

Q10
DTA114YKA_SC59

47K

+5VS_INV

10K

+5VS

+3VS
U11A
SN74LVC08APW_TSSOP14
D

LID_SW#
18

Q13
BSS138_SOT23

M_ENBLT

S
R80
R86
100K_0402_5%
100K_0402_5%

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

LCD CONN.
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

17

of

52

P E G _RXP[0..15]

PEG_M_TXN[0..15]

PEG_M_TXP[0..15]

+1.8VS

B+

+5VS

+1.8VS

MXM_CD0#

JP5A
C292
+

C11

PEG_RXN0
PEG_RXP0

4.7U_0805_10V4Z

P W R _ G D 33,36,37,45,47
15,25 CLKREQA#

9/15

15 CLK_PCIE_MXM#
15 CLK_PCIE_MXM

R311

@ 0_0402_5%
21

+3VS

CLK_PCIE_MXM#
CLK_PCIE_MXM

PEG_M_TXN0
PEG_M_TXP0
MXM_CD0#
MXM_CRMA

VGA_RST#

VGA_RST#

MXM_LUMA

M X M A d d r e s s : 1 0 0 _ 1 1 00
0 _ 0 4 0 2 _ 5 % MXM_SMBDATA
0 _ 0 4 0 2 _ 5 % MXM_SMBCLK
MXM_THERM#
21 MXM_THERM#
M_HSYNC
16 M_HSYNC
M_VSYNC
16 M_VSYNC
M_DDCCLK
16 M _ D D C C L K
M_DDCDATA
16 M_DDCDATA

@ 8.2K_0402_5%
PEG_RXN15
PEG_RXP15

PEG_M_TXN15
PEG_M_TXP15

PEG_RXN14
PEG_RXP14

MXM_CD1# 21,47

2 1 , 25,28,29,33,35,36,40,43,44
25,33,40,41,42,47 ADP_PRES

PEG_M_TXN13
PEG_M_TXP13

PEG_RXN12
PEG_RXP12
PEG_RXN11
PEG_RXP11
PEG_RXN10
PEG_RXP10
PEG_RXN9
PEG_RXP9

+3VS
R305
@ 8.2K_0402_5%

M_RED
M_GRN
M_BLU
M_TXBCLK- 17
M_TXBCLK+ 17

PEG_M_TXN14
PEG_M_TXP14

PEG_RXN13
PEG_RXP13

MXM_COMP

ICH_SMBDATA R 3 2 0
ICH_SMBCLK R 3 1 9

4,13,14,15,21,25,27 ICH_SMBDATA
4,13,14,15,21,25,27 ICH_SMBCLK
R303

21

PEG_M_TXN1
PEG_M_TXP1

100U_25V_M

MXM_CD0#

JP5B
PEG_RXN1
PEG_RXP1

0.1U_0603_50V4Z
C9

PEG_RXN[0..15]

+5VALW
SLP_S3#
R313

SLP_S3#
0_0402_5%

M_TXB2- 17
M_TXB2+ 17

PEG_M_TXN12
PEG_M_TXP12

M_TXB1- 17
M_TXB1+ 17

PEG_M_TXN11
PEG_M_TXP11

M_TXB0- 17
M_TXB0+ 17

PEG_M_TXN10
PEG_M_TXP10

M_TXACLK- 17
M_TXACLK+ 17

PEG_M_TXN9
PEG_M_TXP9

PEG_RXN8
PEG_RXP8

PEG_M_TXN8
PEG_M_TXP8

PEG_RXN7
PEG_RXP7

M_TXA2- 17
M_TXA2+ 17

PEG_M_TXN7
PEG_M_TXP7

PEG_RXN6
PEG_RXP6

M_TXA1- 17
M_TXA1+ 17

PEG_M_TXN6
PEG_M_TXP6

PEG_RXN5
PEG_RXP5

35

PEG_M_TXN5
PEG_M_TXP5

PEG_RXN4
PEG_RXP4

PEG_M_TXN4
PEG_M_TXP4

PEG_RXN3
PEG_RXP3

DVI_TX1DVI_TX1+

35 DVI_TX135 DVI_TX1+

PEG_M_TXN2
PEG_M_TXP2

M_LCD_DAT 17
M _ L C D _ C L K 17
M_ENAVDD 17
M_PWM 17
M_ENBLT 17
DVI_DDC_DAT 35
D V I _ D D C _ C L K 35

DVI_TX2DVI_TX2+

35 DVI_TX235 DVI_TX2+

PEG_M_TXN3
PEG_M_TXP3

PEG_RXN2
PEG_RXP2

M_TXA0- 17
M_TXA0+ 17

DVI_DETECT
DVI_CLKDVI_CLK+

DVI_DETECT
35 DVI_CLK35 DVI_CLK+

+2.5VS

DVI_TX0DVI_TX0+

35 DVI_TX035 DVI_TX0+

+3VS

ACES_88990-2D28_GF

C4
ACES_88990-2D28_GF
4.7U_0805_10V4Z

P l a c e those components as close as

M X M I I I c o nnector within 500 mils.

TV-Out Termination/EMI Filter

MXM_LUMA

MXM_LUMA

MXM_CRMA

MXM_CRMA

MXM_COMP

MXM_COMP

R316

R314

R317

150_0402_1% 150_0402_1% 150_0402_1%

C17

82P_0402_50V8J

C18

C R T Termination/EMI Filter

P l a c e c l oce to MXM connector JP39

L4

L8
CHB1608U301_0603

M_LUMA

L9
CHB1608U301_0603

M_CRMA

L7
CHB1608U301_0603

M_COMP

C19

82P_0402_50V8J

C13

C15

82P_0402_50V8J

16,35

M_RED

M_CRMA

16,35

M_GRN

M_COMP

16,35

M_LUMA

L1
RED_LL

D_RED

HLC0 6 0 3 C S C C 3 9 N J T _ 0 6 0 3
L5
GREEN_LL

D_GREEN

HLC0 6 0 3 C S C C 3 9 N J T _ 0 6 0 3
L2
M_BLU

BLUE_LL

R10

R11

R2

82P_0402_50V8J

150_0402_1%

150_0402_1%

150_0402_1%

D_BLUE

C7

35

D _ B L U E 35

HLC0 6 0 3 C S C C R 1 1 J T _ 0 6 0 3
C3

35

D_GREEN

HLC0 6 0 3 C S C C R 1 1 J T _ 0 6 0 3
L3

HLC0 6 0 3 C S C C 3 9 N J T _ 0 6 0 3

C14

D_RED

HLC0 6 0 3 C S C C R 1 1 J T _ 0 6 0 3
L6

C2

18P_0402_50V8J 18P_0402_50V8J
18P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

Place those component s as close

as MXMIII connector within 500 mils.
Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

M X M III CONN
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

18

of

52

+5VS
+3VS

R89
R617

8.2K_0402_5% PCI_DEVSEL#

R613

8.2K_0402_5% PCI_STOP#

R616

8.2K_0402_5% PCI_TRDY#

R611

8.2K_0402_5% PCI_FRAME#

R619

8.2K_0402_5% PCI_PLOCK#

R625

8.2K_0402_5% PCI_IRDY#

330_0402_5%
ALS_EN

R622

8.2K_0402_5% PCI_SERR#

R623

8.2K_0402_5% PCI_PERR#

R615

8.2K_0402_5% PCI_REQ4#

R618

8.2K_0402_5% PCI_REQ3#

23

U10B

P C I_AD[0..31]

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VS

9/2

R106

8.2K_0402_5% PCI_PIRQA#

R107

8.2K_0402_5% PCI_PIRQB#

R105

8.2K_0402_5% PCI_PIRQC#

R635

8.2K_0402_5% PCI_PIRQD#

R626

8.2K_0402_5% PCI_PIRQE#

R628

8.2K_0402_5% PCI_PIRQF#

R624

8.2K_0402_5% PCI_PIRQG#

R632

@ 8.2K_0402_5% PCI_PIRQH#

R631

8.2K_0402_5% PCI_REQ0#

R610

8.2K_0402_5% PCI_REQ1#

R607

8.2K_0402_5% PCI_REQ2#

R627

8.2K_0402_5% CPPE#

ALS_EN

17

23
23

ALS_EN#

PCI_PIRQC#
PCI_PIRQD#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

P CI

Q15
2N7002_SOT23

G
S

PCI_REQ2#
PCI_GNT2#
PCI_REQ3#

PCI_REQ2#
PCI_GNT2#

PCI_REQ4#
ICH_GPIO48
CPPE#
ALS_EN#

23
23

+3VS
CPPE#

15,35
U9

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PCI_RST#

PCI_RST#

23,24

@ TC7SH08FU_SSOP5
R71
0_0402_5%

PCI_IRDY#
23
PCI_PAR
23
PCI_DEVSEL# 23
PCI_PERR# 23

+3VS

PCI_SERR# 23,33
PCI_STOP#
23
PCI_TRDY#
23
PCI_FRAME#
23

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

Interrupt

PCI_PCIRST#

23
23
23
23

R675
R676

PCI_PLTRST#
0_0402_5%

0_0402_5%

CLK_PCI_ICH 15
PCI_PME#
23

11/23

U11D
SN74LVC08APW_TSSOP14
R66
@0 _ 0 4 0 2 _ 5 %

I/F

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_PIRQE#

23

PCI_PIRQG#

23

PLT_RST#

R636
0_0402_5%

MISC

ACCEL_INT

MCH_ICH_SYNC#

PLT_RST#

7,20,21,23,25,27,32,33

27

ICH7M_B0_BGA652
8.2K_0402_5% ICH_GPIO48

R612
B

P l a c e closely pin A9
CLK_PCI_ICH
R621

ALS_EN#

@ 10_0402_5%
R83
SPI@

1K_0402_5%

C145
@ 8.2P_0402_50V

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

I C H 7 -M(1/4)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

19

of

52

C158

18P_0402_50V8J

ICH_RTCX1

Y1
R96

S A T A CONN

10M_0402_5%
U10A

LPC_AD[0..3]

C157

R629

CMOS_CLR1

+RTCVCC

ICH_INTVRMEN
SM_INTRUDER#

LPC_DRQ#0
LPC_DRQ#1

1M_0402_5%
LPC_FRAME#

C PU

L AN

GATEA20
H_A20M#

GATEA20
H_A20M#

H_CPUSLP_R#

PAD

DPRSLP# R 5 8
H_DPSLP#
R54
H_FERR#

28

AC97_BITCLK_MDC

AC97_BITCLK_CODEC
34

AC97_SYNC_CODEC
34

28

R100

H_PWRGOOD

33_0402_5%

R113

H_IGNNE#
FWH_INIT#
H_INIT#
H_INTR

33_0402_5%

AC97_RST#_MDC

33_0402_5%

R269

33_0402_5%

R253

AC97_BITCLK
AC97_SYNC

R630

AC97_RST#

AC97_RST#_CODEC

33_0402_5%
28
34

28

AC97_SDOUT_CODEC
34

+3VALW

R240

AC97_SDOUT_MDC

AC97_SDIN0
AC97_SDIN1

AC97_SDIN0
AC97_SDIN1

33_0402_5%

R245

33_0402_5%

R247

AC97_SDOUT

24.9_0402_1%
4.7K_0402_5%
8.2K_0402_5%

R609
R608

H_SMI#
H_NMI

OCTEK_SAT-22DN1G_NR

33
R592

4
4

56_0402_5%

H_STPCLK#

I DE

PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#

H_THERMTRIP#

4,7

R 1 0 3 1 must be placed close to U26.AF26

w i t h i n 2 " and R1030 must be placed close
t o R 1031 within 2".

H_STPCLK#

11/18
+5VS

32

SATA_TXP0_C

L Near ICH7(U26) side.

RTC1

IDE_LED#

IDE_LED#

BATT1

JP28

+5VS

RTC2

W =20mils

R499
R503

3900P_0402_50V7K
SATA_RXN0

C173

3900P_0402_50V7K
SATA_RXP0

SATA_RXP0_C

+5VS

+5VS
+5VS
+5VS

C 1 0 4 0.1U_0402_16V4Z
OCTEK_CDR-50DU1

C147

C98

C100

C101

C102

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

P C B - MB

L
C175

100K_0402_5%

+5VS

Place

c o m p o n e n t's closely IDE CONN. JP37

PLT_RST#
R88

SATA_RXN0_C

PDIAG# R 5 0 9
PD_A2
PD_CS#3
W = 8 0 m i ls

+3VS

7,19,21,23,25,27,32,33

PD_DACK#

SEC_CSEL
@ 4.7K_0402_5%
470_0402_5%

8/24

E&T_7651

ZZZ

R T C B A TTERY

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15
PD_DREQ
PD_IOR#

+5VS
+5VS

1K_0402_5%

1U_0603_10V4Z

45@ C R 2 0 2 5

ODD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

CH751H-40_SC76
D32

DAN202U_SC70

3900P_0402_50V7K
SATA_TXP0

c o m p o n e n t's closely IDE CONN. JP45

PD_IOW#
PD_IORDY
PD_IRQ
PD_A1
PD_A0
PD_CS#1
IDE_DSP#

10K_0402_5%

R423

3900P_0402_50V7K
SATA_TXN0

0.1U_0402_16V4Z

Place

JP13

+3VL

100_0402_5%
C403

C149

C156

0.1U_0402_16V4Z

ODD CONN

D35

C150

C151

0.1U_0402_16V4Z

PD_DREQ

+RTCVCC

SATA_TXN0_C

C153

10U_0805_10V4Z

R512

7/6

C148

L
H_STPCLK#

ICH7M_B0_BGA652

R430

+5VS
R591
24.9_0402_1%

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

R101

+3VS

10K_0402_5%
KB_RST#

0_0402_5%
THRMTRIP_ICH#

R620
@0 _ 0 4 0 2 _ 5 %

+5VS

H_IGNNE# 4
PAD
T26 9/8
H_INIT# 4
+3VS + V C C P
H_INTR 4

R598

CLK_PCIE_SATA#
CLK_PCIE_SATA

CLK_PCIE_SATA#
CLK_PCIE_SATA

H_PWRGOOD

R60

332K_0402_1%
15
15

H_DPRSTP# 4,45
H_DPSLP# 4
+VCCP

PD_CS#1
PD_CS#3

R103

ICH_INTVRMEN

+3VS

T14

56_0402_5%

H_SMI#
H_NMI

S A TA

@ 332K_0402_1%

27,31,32,33
10K_0402_5%

H_FERR#

PD_A0
PD_A1
PD_A2

SATA_RXN0_C
SATA_RXP0_C
SATA_TXN0_C
SATA_TXP0_C

SATA_RXN0
SATA_RXP0

33
4

0_0402_5%

KB_RST#

IDE_LED#

+RTCVCC

R102

AC-97/AZALIA

28

33_0402_5%

AC97_SYNC_MDC

31

LPC_FRAME#
R61

34

SATA_TXP0
SATA_TXN0

LPC_DRQ#0
LPC_DRQ#1

SHORT PADS
C159
1U_0603_10V4Z

JP20

27,31,32,33

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

ICH_RTCRST#

R645
20K_0402_5%

+RTCVCC

ICH_RTCX2

L PC

18P_0402_50V8J

R TC

32.768KHZ_12.5P_1TJS125BJ2A251

3 3 _ 0 4 0 2 _ 5 % ODD_RST#
PLT_RST_B#

U11B
SN74LVC08APW_TSSOP14

27,31
A

L Near Device(JP45) side.

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

I C H 7 -M(2/4)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

20

of

52

P l a c e closely pin B2
+3VALW

+3VALW

L
R75

R 2 1 3 , R 233 change from 2.2Kohm to

1 0 K o h m when Q23,Q24,R206,R204 stuffed.

R81

2.2K_0402_5%

2.2K_0402_5%

0_0402_5%
0_0402_5%

ICH_SMB_CLK
ICH_SMB_DATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

R77

+3VS

+3VALW
R587
ICH_RI#
8.2K_0402_5%

@ 2N7002_SOT23
Q11

Q14
@ 2N7002_SOT23

PAD

T27

PAD
M24_RST# R 5 8 6

T49

11/14

1/4

GPIO27_SB

23,31,32,33

8.2K_0402_5%
PM_CLKRUN#

25

PAD
PAD

R73

PM_CLKRUN#

PM_CLKRUN#

+3VALW

10K_0402_5%
SIRQ

GPIO28_SB
0_0402_5%

R604
1K_0402_5%

@ 10K_0402_5%
THERM_SCI#

R63

T31
T32

CLK_14M_ICH
CLK_48M_ICH

DPRSLPVR

+3VALW

PCIE_WAKE#

0_0402_5%
R600

10K_0402_5%
25 LP_EN#

R594
R606

7,45

10K_0402_5%
OCP#

VGATE_INTEL
7,33 PM_POK

25 PCIE_RXN1
25 PCIE_RXP1
25 PCIE_TXN1
25 PCIE_TXP1

10K_0402_5%
LID_SW#

+3VALW

ON/OFFBTN#

ICH7M_B0_BGA652

PM_POK

7,33

0.1U_0603_16V7K
0.1U_0603_16V7K

18

R67
0_0402_5%

MXM_THERM#

C133
C134

PCIE_RXN1
PCIE_RXP1
PCIE_C_TXN1
PCIE_C_TXP1

C127
C128

PCIE_RXN2
PCIE_RXP2
PCIE_C_TXN2
PCIE_C_TXP2

11/22

R76
10K_0402_5%

D14
PREP#

ISO_PREP#

35 PCIE_RXN4
35 PCIE_RXP4
35 PCIE_TXN4
35 PCIE_TXP4

CH751H-40_SC76

0.1U_0402_16V4Z
0.1U_0402_16V4Z

C129
C130

PCIE_RXN4
PCIE_RXP4
PCIE_C_TXN4
PCIE_C_TXP4

+3VS

GPIO39_SB

34

PM_RSMRST#

33

PLT_RST#

PLT_RST#

7,19,20,23,25,27,32,33

U11C
SN74LVC08APW_TSSOP14

R97

R 1 2 9 2/R1293 should be placed

l e s s than 100 mils from U26.

SPI_CLK
SPI_CS#

32 S P I _SI
32 SPI_SO

SPI_CS#
10K_0402_5%
R110
SPI_SI
SPI@ 10K_0402_5%
R111
SPI_SO
SPI@ 10K_0402_5%
SPI@

SPI_CLK
SPI_CS#

R98

SPI_SI
SPI_SO

R99

29
29
30
30
18

R 1 2 84,R1285 and R1286 should

b e p l aced close to U26.

USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#

SPI@

47_0402_5%

SPI@

47_0402_5%

S PI

32
32

+3VALW

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
MXM_CD0#

U SB

R74
10K_0402_5%
DPRSLPVR

THERM_SCI#

R602 @ 0_0402_5%

LOM_LOW_PWR

25

CABLE_DETECT

25,26

J16

25

PAD-SHORT 2x2m

DOCK_ID

35

R 1 0 1 5 n e e d be removed when ICH7M ES2 samples used,

b u t n e e d b e s tuffed when ICH7M ES1 samples used.

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI_RXN0 7
DMI_RXP0 7
DMI_TXN0 7
DMI_TXP0 7

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI_RXN1 7
DMI_RXP1 7
DMI_TXN1 7
DMI_TXP1 7

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN2 7
DMI_RXP2 7
DMI_TXN2 7
DMI_TXP2 7

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RXN3 7
DMI_RXP3 7
DMI_TXN3 7
DMI_TXP3 7

CLK_PCIE_ICH#
CLK_PCIE_ICH

CLK_PCIE_ICH# 15
CLK_PCIE_ICH 15
R 5 8 8 24.9_0402_1%

W i thin 500 mils

+1.5VS

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

RP20
USB_OC#3
USB_OC#0
USB_OC#1
USB_OC#2

30
30
32
32
29
29
29
29
30
30
30
30
35
35
35
35

10K_1206_8P4R_5%
R638
10K_0402_5%
USB_OC#4
R644
10K_0402_5%
USB_OC#5
R642
10K_0402_5%

R 6 4 1 22.6_0402_1%

MXM_CD0#
R643
22K_0402_5%

W i thin 500 mils

MXM_CD1#_R

MXM_CD1#

MXM_CD1#_R
@ 0_0402_5%
S

R639
D

MXM_CD1#

Compal Secret Data

S e c u r i t y C l a s s ification

Compal Electronics, Inc.

@ 2N7002_SOT23
Q109

+3VALW

1/4

2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

I C H 7 -M(3/4)
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

1/4

ICH7M_B0_BGA652
18,47

+3VALW

USBRBIAS

33

CH751H-40_SC76

+3VL

M24_RST#
VGA_RST#

+3VALW
D13
LOW_BAT#

ON/OFFBTN#

R605
@0 _ 0 4 0 2 _ 5 %
T29 PAD

DMI_IRCOMP
18

R601
8.2K_0402_5%

R633
10K_0402_5%

7,45

GPIO9_SB
T28 PAD
CB_IN#
GPIO12_SB
T30 PAD
LID_SW#
LID_SW# 17,34
LANLINK_STATUS#_SB
LANLINK_STATUS#_SB
GPIO15_SB
T25 PAD
XMIT_OFF
XMIT_OFF 27
BT_OFF
BT_OFF 30
NPCI_RST#
NPCI_RST# 31,33

N e e d u p d ate symbol

P C I - E X PRESS

R78

PREP#

18,25,28,29,33,35,36,40,43,44
44
36,44

PLT_RST#

G P IO

11/14

PWROK_ICH7

0.1U_0402_16V4Z
0.1U_0402_16V4Z

27 PCIE_RXN2
27 PCIE_RXP2
27 PCIE_TXN2
27 PCIE_TXP2

+3VS

10K_0402_5%
26,35

0_0402_5%
@0 _ 0 4 0 2 _ 5 %

15
15

U10D

11/21

R64
R59

R599
@ 100K_0402_5%

RUNSCI_EC#
ISO_PREP#
LP_EN#

33 RUNSCI_EC#
35 ISO_PREP#

10K_0402_5%
LINKALERT#

10K_0402_5%
R596
XDP_DBRESET#

@ 4.7P_0402_50V8C

SLP_S3#
SLP_S4#
SLP_S5#

DPRSLPVR

PM_RSMRST#
R 6 3 4 10K_0402_5%

D I R E C T M E D I A INTERFACE

R589

C542

@ 4.7P_0402_50V8C

ICH_LOW_BAT#

R603
27

C541

T16 PAD

SLP_S3#
SLP_S4#
SLP_S5#

PWROK_ICH7

V_3P3_LAN

32

CLK_14M_ICH
CLK_48M_ICH

ICH_SUSCLK

ICH_PCIE_WAKE#
SIRQ
THERM_SCI#

23,31,32,33 SIRQ
4 THERM_SCI#

Q8
BSS138_SOT23

HDD_STP

FWH_WP#
FWH_TBL#

LOM_PCIE_WAKE#

+3VALW

@ 10_0402_5%

R72
100_0402_5%

PM_POK

GPIO26_SB

+3VS

R68

OCP#
H_STP_PCI#
H_STP_CPU#

G P IO

ICH_SMB_CLK

+3VS

PM_BMBUSY#

PM_BMBUSY#

4,47 OCP#
15 H_STP_PCI#
15 H_STP_CPU#

ICH_SMB_DATA

ICH_SMBCLK

ICH_SMBCLK

S YS

@ 2.2K_0402_5%

ICH_SMBDATA

ICH_SMBDATA

4,13,14,15,18,25,27

SB_SPKR
LPC_PD#
XDP_DBRESET#

28 SB_SPKR
32,33 LPC_PD#
4 XDP_DBRESET#

R84

4,13,14,15,18,25,27

R640

@1 0 _ 0 4 0 2 _ 5 %
U10C

S MB

ICH_SMBCLK
ICH_SMBDATA

R79

R637

R82

S A TA
G P IO

10K_0402_5%

Clocks

10K_0402_5%

@ 2.2K_0402_5%

CLK_14M_ICH

R593

P O W E R MGT

R595

P l a c e closely pin AC1

CLK_48M_ICH

Saturday, January 14, 2006

Sheet
1

21

of

52

+VCCP
U10F

U10E

ICH_V5REF_RUN

+1.5VS

0.1U_0402_16V4Z

ICH_V5REF_SUS

C519

C513

C131

+
D

0.1U_0402_16V4Z
+5VS

+3VS
C132

C506

C505

9/15

C507
1U_0603_10V4Z

220U 6.3V M

220U 6.3V M
R614
100_0402_5%

D15

9/15

CH751H-40_SC76

0.1U_0402_16V4Z

0.1U_0402_16V4Z

P l a c e closely pin
D 28,T28,AD28.

ICH_V5REF_RUN
C517

C515

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VS
+VCCP

+3VS

C518
C523

+5VALW +3VALW

0.1U_0402_16V4Z

0.1U_0402_16V4Z
+3VS

R90
10_0402_5%

C512
0.1U_0402_16V4Z

D17

C511

CH751H-40_SC76

0.1U_0402_16V4Z
C520
22U_0805_6.3V

ICH_V5REF_SUS
C

+3VS

C535
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C525
0.1U_0402_16V4Z

C522
0.1U_0402_16V4Z

C532

+3VS

C536
0.1U_0402_16V4Z

+3VALW
C533

C528

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C529

C538

0.1U_0402_16V4Z

0.1U_0402_16V4Z

P l a c e c l o sely pin AG28 within 100mlis.

+3VALW

R585

0.5_0805_1%

0_0805_5%

C504
0.01U_0402_16V7K

R584

+1.5VS_DMIPLL

C503
22U_0805_6.3V

+1.5VS

+1.5VS_DMIPLLR

C531
0.1U_0402_16V4Z

+RTCVCC

C508
0.1U_0402_16V4Z

+1.5VS_DMIPLL
+1.5VS

C534
B

+1.5VS

P l a c e closely pin AG5.

+3VS

C521
0.1U_0402_16V4Z

C527

+1.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.5VS
C146
C 5 3 0 0.1U_0402_16V4Z
ICH_K7
PAD

1U_0603_10V4Z

ICH_C28
ICH_G20

P l a c e closely pin AG9.

+3VALW
C537
0.1U_0402_16V4Z

PAD
PAD

T19
T13
T15

+1.5VS

+1.5VS

C516
C543

T18
T17

0.1U_0402_16V4Z

PAD
PAD

ICH_AA2
ICH_Y7

0.1U_0402_16V4Z

J18

ICH7M_B0_BGA652
ICH_SUSLAN

+3VALW
PAD-SHORT 2x2m
A

J17

ICH7M_B0_BGA652
C540

0.1U_0402_16V4Z

+3VS
PAD-No SHORT 2x2m

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

I C H 7 -M(4/4)
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

22

of

52

+3VS_CBPLL

+3VS

+3VS

+VCC_MS

+VCC_SD

1U_0603_10V4Z

1U_0603_10V4Z C234

C169

0.01U_0402_16V7K
C230

C174

J6

J7

0_0805_5%
C185
PAD-No SHORT 2x2m

1/13

PAD-SHORT 2x2m

C165

R128

C178

22K_0402_5%

100K_0402_5%

4.7K_0402_5%

L12
+VDD_PLL33
+VDD_PLL

+VDDPLL33
CHB1608U301_0603
+VDDPLL
C 2 3 2 0.1U_0402_16V4Z

10U_0805_10V4Z
R114

K e e p + VDD_PLL33/+VDDPLL33/+VDD_PLL
/ + V D DPLL at least 10 mils

R125

R115

R 2 2 8 6.34K_0402_1%

+3VS

C241

X_OUT
24.576MHZ_16P_1BG24576CK1A
10P_0402_50V8J
MC_PWRON#
PWR_CTRL_1/SM_R/B#
SD_CD#
MS_CD#
SM_CD#

PCI7612/7 412

MSCLK_SDCLK_SMELWP#

22_0402_5%
MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0
SDCLK_SMRE#
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

24
24

9/10
+3VS

9/10

D22
JP24

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

SD_DAT3 0 _ 0 4 0 2 _ 5 % R 1 2 2 MSD3_SDD3_SMD3
SD_DAT2 0 _ 0 4 0 2 _ 5 % R 1 2 3 MSD2_SDD2_SMD2
SD_DAT1 0 _ 0 4 0 2 _ 5 % R 1 1 9 MSD1_SDD1_SMD1
SD_DAT0 0 _ 0 4 0 2 _ 5 % R 1 2 0 MSD0_SDD0_SMD0
SDWP#_SMCE#
0_0402_5%
R 1 2 1 MSBS_SDCMD_SMWE#
0_0402_5%
R 1 1 8 MSCLK_SDCLK_SMELWP#

5 IN 1 CONN

P l a c e the parts close to JP41

MSCLK_SDCLK_SMELWP#
SM_PHYS_WP#
@ 3 3 _ 0 4 0 2 _ 5 % MSBS_SDCMD_SMWE#
SDCMD_SMALE

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSCLK_SDCLK_SMELWP#
MS_CD#
MSBS_SDCMD_SMWE#

+VCC_SM_XD
SM_CD#
SM_RB#
SDCLK_SMRE#
SDWP#_SMCE#
SM_CD#

C164

+VCC_MS+VCC_SM_XD

0.1U_0402_16V4Z

CLK_PCI_PCM
0_0402_5%
PRST#
R150
GRST#
R136
CB_PME#
@ 0_0402_5%

R117
0_0402_5%
SC_CLK_R
SC_RST
24 SC_RST
0
_
0
4
0
2
_5%
R143
+SC_PWR
SC_DATA
24 SC_DATA
SC_OC#
R129
@ 10K_0402_5%
S M _ PHYS_WP#/SC_FCB
R130
@ 10K_0402_5%
SM_RB#/SC_RFU

+VCC_SD

SD_CD#

R116

PCI_AD22
R161
100_0402_5%

SC_CLK

SC_CLK

19

Q27
2N7002_SOT23

SD_CD#
@ RB751V_SOD323
SM_CD#
@ RB751V_SOD323

D21
PCI_PME#

SMCLE

SMCLE
SC_CD#

SC_CD#

G
Q30
S
@ 2N7002_SOT23

Q20
@ 2N7002_SOT23

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

R175

Q22
2N7002_SOT23

FM_LED#
R148

CB_PME#

10K_0402_5%
D

X_IN

@ 10K_0402_5%

R165

MC_PWRON#
S

SDCLK_SMRE#

SD_CD#
G

X_OUT
Y2

MS_CD#

10K_0402_5%

X_IN

R164

MSBS_SDCMD_SMWE#

R230
@ 4.7K_0402_5%

SM_RB#
+3VS

XTPB1+
XTPB1-

10K_0402_5%

XTPBIAS1

+3VS

R127

100K_0402_5%

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

9/6

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

10U_0805_10V4Z

+3VS

R126

100K_0402_5%
SDWP#_SMCE#

10P_0402_50V8J
R237
@ 1M_0402_5%

47K_0402_5%

+3VS

C242

R154

0.1U_0402_16V4Z

U16B

+3VS

12/8

1U_0603_10V4Z
C219

0.1U_0402_16V4Z

R173
10U_0805_10V4Z
C227

0_0805_5%

R229

P C I _ CBE#[0..3]

P C I_CBE#[0..3]

+VCC_MS
+VCC_SM_XD
SI2301BDS_SOT23
Q28
S

+VCC_MS
+VCC_SD
SI2301BDS_SOT23
Q21

P C I_AD[0..31]

P C I_AD[0..31]

19

+3VS_CBVCCP

19

R151
43K_0402_5%
PCM_SPK

PCI_PAR
19
PCI_FRAME#
19
PCI_TRDY# 19
PCI_IRDY#
19
PCI_STOP#
19
PCI_DEVSEL#
19
PCI_PERR#
PCI_SERR#
PCI_REQ2#
PCI_GNT2#

XD_CD#

TAITW _ R 0 0 7 - 0 1 0 - N 3

R116,R142,R182
S t u f f when 7611 used

56.2_0603_1%

19
19,33
19
19

R195

PCM_SPK
R145
R133
R132
R144
R137

PM_CLKRUN#

CLK_PCI_PCM
220_0402_5%
220_0402_5%

R146
R134

220_0402_5%

R135

12/15

56.2_0603_1%

28

PCI_PIRQC# 19
PCI_PIRQD# 19
PCI_PIRQG# 19
SIRQ 21,31,32,33
PCI_PIRQE#
19

C207

XTPBIAS0
XTPB0XTPB0+
XTPA0XTPA0+

+3VS

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
FM_LED#

R201

1U_0603_10V4Z

CLK_PCI_PCM 15
PCI_RST# 19,24
PLT_RST# 7,19,20,21,25,27,32,33

JP17
3

R187
R124
PRST#

R183

56.2_0603_1%
GRST#

AMP_440168-2

0_0402_5%

56.2_0603_1%

21,31,32,33
C189

R149

R186

270P_0603_50V8J

5.1K_0603_1%

@1 0 _ 0 4 0 2 _ 5 %
R231
PCI7612ZHK_PBGA257

PCM_SPK

C168

43K_0402_5%

@ 15P_0402_50V8J

+3VS

+VCC_MS +3VS

U12
SM_RB#/SC_RFU

R141

SC_RFU
0_0402_5%
SM_RB#
R142
@ 0_0402_5%

S M _ PHYS_WP#/SC_FCB R 1 4 0
R152

XD_CD#

R131
7612@ 0 _ 0 4 0 2 _ 5 %

SC_FCB
0_0402_5%
SM_PHYS_WP# R 1 5 3
@ 0_0402_5%
7612@0 _ 0 4 0 2 _ 5 %

R159
XD_CD#/SM_PHYS_WP#
7612@ 0 _ 0 4 0 2 _ 5 %
SM_CD#
R182
@ 0_0402_5%

SC_RFU

24

C L O SE TO CHIP

C L O SE TO CHIP

SC_FCB

24

XTPBIAS1
XTPB1+
XTPB1-

R91
10K_0402_5%

MC_PWRON#
TPS2061IDGN_MSOP8~N

XD_CD#/SM_PHYS_WP#

C152

10U_0805_10V4Z

C154

0.01U_0402_16V7K

R193
1K_0402_5%

R200

C212
1U_0603_10V4Z

24

Compal Secret Data

2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

T I P C I 7 6 12 PCI/CardReader
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

1K_0402_5%

PWR_CTRL_1/SM_R/B#

S e c u r i t y C l a s s ification

+VDDPLL

Saturday, January 14, 2006

Sheet
E

23

of

52

U19

+S1_VCC

19,23

PCI_RST#

CB_DAT
CB_CLK
CB_LATCH
PCI_RST#

+3VS

+S1_VPP
+SC_PWR

S1_REG#
S1_A12
S1_A8
S1_CE1#

N e a r to PCMCIA slot.
+S1_VCC
+S1_VCC

C211

C210

10U_0805_10V4Z

0.1U_0402_16V4Z

9/8
JP23
+S1_VPP

C201

C200

10U_0805_10V4Z

0.1U_0402_16V4Z

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#

PCI7612/7412

C231
S1_CD1#

S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5

100P_0402_50V8J
C197
S1_CD2#

TPS2224ADBR_HTSSOP24

S1_A13
S1_A23
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16_C
S1_A16
R227
3 3 _ 0 4 0 2 _ 5 % S1_RDY#
CPS
+3VS
CLK_48M_CB
15 C L K _ 4 8 M _ C B
S1_A22
S1_BVD2
R189
CPS
S1_RST
4.7K_0402_5%

SC_DATA

SC_DATA

23

100P_0402_50V8J
S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23
S1_D2
S1_A18
S1_D14

+SC_PWR

SC_RST

S1_A15
S1_A22
S1_A16_C

+3VS

43K_0402_5%
R160
@ 43K_0402_5%
R166

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

CLK_48M_CB

C258

0.1U_0402_16V4Z
C233

+5VS
U16A
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

0.1U_0402_16V4Z

C202

C228
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C229

10U_0805_10V4Z
C235

C203
0.1U_0402_16V4Z

C182
0.1U_0402_16V4Z

C179
0.1U_0402_16V4Z

C187
0.1U_0402_16V4Z

C195
0.1U_0402_16V4Z

C170
0.1U_0402_16V4Z

+3VS

0.1U_0402_16V4Z

SC_CLK

SC_RST

23

SC_CLK

23

SC_CD#
SC_FCB

23
23

SC_RFU

23

+S1_VPP
+S1_VCC

XD_CD#/SM_PHYS_WP#

XD_CD#/SM_PHYS_WP#

CB_DAT
CB_CLK
CB_LATCH

CB_CLK

23

33

R147

S1_RDY#
S1_A21
S1_WE#

SC_CD#
SC_FCB

S1_A20
S1_A14
S1_A19
S1_A13
S1_A18
S1_A8
S1_A17

SC_RFU

@ 10_0402_5%
S1_A9
S1_IOWR#
S1_A11
S1_IORD#
S1_OE#
S1_VS1
S1_A10

C166
@ 10P_0402_50V8J
PCI7612ZHK_PBGA257
+SC_PWR

R208

+SC_PWR

S1_CE2#
S1_CE1#
S1_D15
S1_D7
S1_D14
S1_D6
S1_D13

C218

@ 10K_0402_5%

0.1U_0402_16V4Z
S1_D5
S1_D12
S1_D4
S1_D11
S1_D3
S1_CD1#

R168
@ 22K_0402_5%
SC_CLK

C180
@ 56P_0402_50V8J

SC_DATA

R169

SC_RST

C199

@ 22K_0402_5%

@ 100P_0402_50V8J

R190

R176

C184
@ 22K_0402_5%
@ 470P_0402_50V7K

@ 22K_0402_5%

TYCO_1123088-1_LT

P l a c e the parts close to JP9

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

T I P C I 7 612 CB/SmartCard
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

24

of

52

7,19,20,21,23,27,32,33

PLT_RST#

J10

+3VALW

L a y o u t Notice : Place as close

c h i p as possible.

PAD-NO SHORT 2x2m

D36

R20

9/7

C544

11/21

4.7K_0402_5%

U25A

PLT_RST#_LAN

B CM5753
9/7

M e dia

R391

10K_0402_5%

5751_GPIO1
ICH_LAN_SMBCLK
ICH_LAN_SMBDATA

V_3P3_LAN

P o wer
C o n trol

V_3P3_LAN

V_3P3_LAN

R678

R673

26

R21

11/14

LP_EN#
G
2N7002_SOT23

ADP_PRES

M u s t h aving maximized
c o p p e r under pin 2 & 4 of Q13

D
V_3P3_LAN

V_1P2_LAN
BCP69_SOT223
Q54

G
2N7002_SOT23 S

4.7K_0402_5%

REGSUP12

9/13
1 8 , 21,28,29,33,35,36,40,43,44

Q3

@ 0_0402_5%

18,33,40,41,42,47

R19
47K_0402_5%

@ RB751V_SOD323

NIC_PD

NIC_PD

LOM_LOW_PWR

SLP_S3#

Q4
2N7002_SOT23

REGSUP12
VAUX_1.2_CTL

C304

C303

C309

C300

S
4.7U_0805_10V4Z

0.1U_0402_16V4Z

V_1P2_LAN

10U_0805_6.3V6M

VAUX_1.2_CTL

0.1U_0402_16V4Z

V_2P5_LAN
V_3P3_LAN
V_3P3_LAN

R335

H o t Plug
S u p port

10K_0402_5%

26
26
26
26
26
26
26
26

R407

R e g u lator
C o n trol

11/23

+3VALW

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-

@ 0.1U_0402_16V7K

Q5

M isc

5751_EECLK
5751_EEDAT

LAN_TX3+
LAN_TX3LAN_TX2+
LAN_TX2LAN_TX1+
LAN_TX1LAN_TX0+
LAN_TX0-

C366
4.7U_0805_10V4Z

R329

ICH_SMBCLK 4,13,14,15,18,21,27
ICH_SMBDATA 4,13,14,15,18,21,27

C308
0.1U_0402_16V4Z

S
ICH_SMBCLK
ICH_SMBDATA

V_3P3_LAN

Q2
SI2301BDS_SOT23

@0 _ 0 4 0 2 _ 5 %
0_0402_5%
0_0402_5%

ICH_LAN_SMBCLK R 3 6 7
ICH_LAN_SMBDATA R 3 3 6

@ 1K_0402_5%
@ 1K_0402_5%

R330

5/16

R366
R337

V_3P3_LAN

SI2301BDS_SOT23
Q57
220K_0402_5%

C307
0.1U_0402_16V4Z

C358
0.1U_0402_16V4Z

C357
0.1U_0402_16V4Z

R663

PCIE_RXN1

21

PCIE_RXP1

21

PCIE_TXN1

21

PCIE_TXP1

21

11/21

V_3P3_LAN

R345
NIC_PD
10K_0402_5%
G

4.7K_0402_5%

PCIE_C_RXN1
C342
0.1U_0402_16V4Z
PCIE_C_RXP1
C344
0.1U_0402_16V4Z

Q78

LAN_ACT#

LAN_ACT#

V_3P3_LAN

11/15

R646

R364

10K_0402_5%

4.7K_0402_5%

0.1U_0402_16V4Z

P l a c e close U6 pin M13

V_2P5_LAN

Q108

@ 4.7K_0402_5%

C352

S
R655
R657
R648

NIC_PD#

1/9

@ 10U_1206_6.3V6M

+3VS V_3P3_LAN

@ BSS84_SOT23

G
R658

@ 0_0402_5%
@ 0_0402_5%
@ 10K_0402_5%

+ C372

C364

0.1U_0402_16V4Z

100U_B_6.3VM

D
NIC_PD

11/21

Q76
@ 2N7002_SOT23

25MHZ_16P_XSL025000FK1H
R373

0_0402_5%

R656
@ 100K_0402_5%

11/18

B ias

XTALI

C299

4.7U_0805_10V4Z

@ 0_0402_5%

C l ock

200_0402_1%

21

R326
XTALO
R347
Y4

LOM_PCIE_WAKE#

D
Q107
@ BSS84_SOT23
R654

NIC_PD_N

R679
10K_0402_5%

V_3P3_LAN

CLK_PCIE_LOM# 15
CLK_PCIE_LOM 15

PLT_RST#_LAN

T EST

26,35

LOM_WAKE#

R 3 2 8 4.7K_0402_5%

L ED

26,35

2N7002_SOT23
R680
@ 0_0402_5%
LANLINK_STATUS#
LANLINK_STATUS#

C306

LOM_WAKE#
CLK_PCIE_LOM#
CLK_PCIE_LOM

P C I-E

LANLINK_STATUS#

LANLINK_STATUS#_SB
D

21

10K_0402_5%

10K_0402_5%

P l a ce close U6 pin N13

BCM5753KFBG C0_FPBGA196~D
C331

C334

27P_0402_50V8J

27P_0402_50V8J

Layout Notice : No high

s p e e d signal should be
r outed near RDAC or on
a d j acent layer to RDAC

1.2K_0402_1%

11/18

11/21
V_3P3_LAN
C379

V_3P3_LAN
C376

@ 0.1U_0402_16V4Z

R406
1K_0402_5%

R404
1K_0402_5%

U28

R405
1K_0402_5%

U27
0.1U_0402_16V4Z

V_3P3_LAN

21

+3VS

R416

LOM_LOW_PWR

LOM_LOW_PWR

@ 100K_0402_5%

11/21

@ SN74LVC1G17DBVR_SOT23-5
R660

5751_GPIO1
5751_EECLK
5751_EEDAT

@0 _ 0 4 0 2 _ 5 %

11/18

R659

11/18

C396

0_0402_5%

V_3P3_LAN

@ 0.1U_0402_16V4Z
R667

D34

+3VALW

1N4148_SOD80

AT24C256_SO8

@ 10K_0402_5%
NIC_PD_N

R661
R662

+3VS

121K_0402_1%
C550

0_0402_5%

CLKREQA#

R334

+3VS

R425

CKT Notice : CABLE IN, CABLE_DETECT=0

CABLE OUT, CABLE_DETECT=1

R424
10K_0402_5%

U38
SN74LVC1G17DBVR_SOT23-5

10K_0402_5%
R426

0.1U_0402_16V7K
A

15,18

21,26

CABLE_DETECT

CABLE_DETECT

R361

@ 0_0402_5%

R668
0_0402_5%

C400
@ 2.2K_0402_5%

@ 2.2K_0402_5%
0.1U_0402_16V4Z

@ 2N7002_SOT23
Q60

ICH_SMBDATA

ICH_LAN_SMBCLK
Q65
@ 2N7002_SOT23

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

+5VS

2 0 0 6 /03/10

D e c i p h e red Date

21

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

B C M 5 753M
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

LP_EN#

G
Q66
2N7002_SOT23

ICH_LAN_SMBDATA

ICH_SMBCLK

NIC_PD_N

LP_EN#

Saturday, January 14, 2006

Sheet
1

25

of

52

T22
R672

LAN_TX0-

MDO0-

LAN_TX0+

MDO0+

L a yout Notice : 1.2V decoupling CAP.

P l a c e as close chip as possible.

V_2P5_LAN
0_0603_5%
+3VS

V_2P5_LAN

V_1P2_LAN

C311
0.1U_0402_16V4Z

C335
0.1U_0402_16V4Z

C310
0.1U_0402_16V4Z

C21
0.1U_0402_16V4Z

G
VMAINPRSNT

C332
0.1U_0402_16V4Z

MDO2-

C312
0.1U_0402_16V4Z

LAN_TX2-

C301
R318
75_0402_1%
1000P_1808_3KV7K

VMAINPRSNT_R
S

MCT1

1:1
C345
0.1U_0402_16V7K

TRM_CT

C40
0.1U_0402_16V4Z

R325

MDO1+

C44
0.1U_0402_16V4Z

25

10K_0402_5%
LAN_TX1+

C323

NIC_PD

11/22

C327

9/10
D

C16
0.1U_0402_16V4Z

MDO1-

C27
4.7U_0805_10V4Z

1:1
LAN_TX1-

R323
75_0402_1%

0.1U_0402_16V4Z

MCT0

0.1U_0402_16V4Z

C348
0.1U_0402_16V7K

TRM_CT

Q106
@ BSS84_SOT23
R653
LAN_TX2+

0_0402_5%

MDO2+
1:1

C346
0.1U_0402_16V7K

TRM_CT

MCT2

LAN_TX3-

MDO3-

LAN_TX3+

MDO3+

R322
75_0402_1%

11/14

V_1P2_LAN

U25B

B CM5753
1:1
TRM_CT
C347
0.1U_0402_16V7K

MCT3
24HST1041A-3B_24P

L a y o ut Notice : Filter place as close

ch ip as possible.
C302
R321
75_0402_1%
1000P_1808_3KV7K
V_3P3_LAN
V_2P5_LAN

D i g i a l power

R393
0.1U_0402_16V4Z
C

C363 R389
R388
C362 R387
R386
C361 R385
R384
C360 R383
R382

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%

LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

LAN_TX0LAN_TX0+
LAN_TX1LAN_TX1+
LAN_TX2LAN_TX2+
LAN_TX3LAN_TX3+

XTALVDD

0_0603_5%

25
25
25
25
25
25
25
25

C353
0.1U_0402_16V4Z
R376

V_3P3_LAN XTALVDD V_2P5_LAN

AVDD1

0_0603_5%

G ND

C340
0.1U_0402_16V4Z
1K_0402_5%

L a yout Notice : Place

t e r m i n ation as close as
B C M 5 7 5 3 M as possible

R358

LAN_AUXPWR
VMAINPRSNT

11/14

R392
AVDD2

0_0603_5%
C356

PCIE_SDS_VDD

0.1U_0402_16V4Z

T o RJ-45 CONN.
25,35

25,35 LAN_ACT#
LANLINK_STATUS#

21,25

CABLE_DETECT

L17

JP4

LAN_ACT# 1 5 0 _ 0 4 0 2 _ 5 %
LANLINK_STATUS#
R12
MDO3+
MDO3+
MDO3MDO3MDO2+
MDO2+
MDO2MDO2MDO1+
MDO1+
MDO1MDO1MDO0+
MDO0+
MDO0MDO0-

BLM11A601S_0603
C370

LAN_ACT#_R
R13
LANLINK_STATUS#_R
150_0402_5%

4.7U_0805_10V4Z

AVDDL
C355
0.1U_0402_16V4Z

V_3P3_LAN

L18
BLM11A601S_0603
C369

GPHY_PLLVDD

R324

C354
@ 4.7K_0402_5%

4.7U_0805_10V4Z

0.1U_0402_16V4Z
T20

CABLE_DETECT
L10
C10

ACES_87212-1400
BLM11A601S_0603
C36

0.1U_0402_16V4Z

4.7U_0805_10V4Z

PCIE_PLLVDD

V_3P3_LAN

0.1U_0402_16V4Z

T 5 9 , T 6 0 place together

PCIE_SDS_VDD

R327

@ 4.7K_0402_5%

C321
T21
PAD

0.1U_0402_16V4Z
R16

@ 4.7K_0402_5%

R374

@ 4.7K_0402_5%

Q64
FDN338P_SOT23

R380

V_3P3_LAN

4.7U_0805_10V4Z

V_3P3_LAN_LED

100K_0402_5%

AVDDL

V_2P5_LAN
L16

PCIE_PLLVDD
GPHY_PLLVDD

G
S Q63
2N7002_SOT23

A n alog
p o wer

AVDD1
AVDD2

D
PREP#

PAD

C39

L15
BLM11A601S_0603
C313

21,35

D i s c o nnected

35
35
35
35
35
35
35
35

V_1P2_LAN

K e e p JP5.1/2/3 at least 10mils

D o n ' t care

V_3P3_LAN_LED

P LL

B IAS
BLM11A601S_0603
C351

BCM5753KFBG C0_FPBGA196~D

0.1U_0402_16V4Z

Compal Secret Data

S e c u r i t y C l a s s ification
Issued Date

2 0 0 5 /03/10

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

M a g n e t ic & RJ45/RJ11
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

26

of

52

+3VS

+3VS

+3VS_ACL

+3VS

1/6

C167

C214

C217

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

C171

+1.5VS

C493

0.1U_0402_16V4Z

4.7U_0805_10V4Z

C492

C489

0.01U_0402_16V7K

0.1U_0402_16V4Z

+3VALW

C494

C491

4.7U_0805_10V4Z

0.1U_0402_16V4Z

+3VS_ACL_IO

R56

R55

@ 0_0805_5%

ACCEL@ 0 _ 0 6 0 3 _ 5 %

+3VS_ACL_IO

D11
ACCEL@ C H 7 5 1 H - 4 0 _ S C 7 6
U6
ACCEL@ 0 _ 0 4 0 2 _ 5 %
R44

1/6

Mini-Express Card

+3VS_ACL

ACCEL_INT

19
PCIE_WAKE#
CH_DATA
CH_CLK
CLKREQD#

21

PCIE_WAKE#
30 CH_DATA
30 C H _ C L K
15 CLKREQD#

ICH_SMBDATA
ICH_SMBCLK

ACCEL@ 0 _ 0 4 0 2 _ 5 %

4,13,14,15,18,21,25
4,13,14,15,18,21,25

+3VS_ACL

21
21

R48

PCIE_RXN2
PCIE_RXP2

CLK_PCI_DB

PCIE_RXN2
PCIE_RXP2

DB_LPC_FRAME#
DB_LPC_AD3
DB_LPC_AD2
DB_LPC_AD1
DB_LPC_AD0

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

15 CLK_PCIE_MCARD#
15 CLK_PCIE_MCARD
15

R546
R547

DB_LPC_RST#
CLK_PCI_DB
0_0402_5%
PCIE_C_RXN2
PCIE_C_RXP2
0_0402_5%

PLT_RST#
J12

21
21

PAD-SHORT 2x2m
J11

ICH_SMBCLK 4,13,14,15,18,21,25
ICH_SMBDATA 4,13,14,15,18,21,25

C136

C121

C135
ACCEL@ LIS3LV02DQ_QFN28

8/30

9/8

WW_LED#
WL_LED#
WP_LED#

DB_PWR
DB_PWR_LED#
DB_NUM_LED#
DB_CAPS_LED#

5/26

ACCEL@ 0.1U_0402_16V4Z

M u s t b e p l a c ed in the center of the system.

p i n 2 9 i s t h e center EMI pad which STMicro
r e c o m m e n d e d not to be connected

FOX_AS0B226-S40N-7F

R92

WL_LED#

32
32

32

WW_LED#

R497

@ 0_0402_5%

WP_LED#

R500

@ 0_0402_5%

WL_LED#

H29
H28
HOLE_MC HOLE_MC

+3VALW

USB20_N1_R_MC
USB20_P1_R_MC

0_0402_5%

ACCEL@ 10U_0805_6.3V6M

@ 0.01U_0402_16V7K

+3VALW
PAD-No SHORT 2x2m

PCIE_TXN2
PCIE_TXP2

PCIE_TXN2
PCIE_TXP2

7,19,20,21,23,25,32,33

1/4
V_3P3_LAN

XMIT_OFF#

ACCEL@ 10K_0402_5%
+3VS_ACL
R43

+3VS

JP30

R45
ACCEL@ 0 _ 0 4 0 2 _ 5 %

R50

+1.5VS

R112

@ 10K_0402_5%

Mini-Card Stand Off

@ 100K_0402_5%

R104

9/16
21

XMIT_OFF

XMIT_OFF#
0_0402_5%

D
Q17
@ 2N7002_SOT23

M u s t b e placed close to JP44.

20,31,32,33 LPC_FRAME#
20,31,32,33 LPC_AD3
20,31,32,33 LPC_AD2
20,31,32,33 LPC_AD1
20,31,32,33 LPC_AD0
20,31 PLT_RST_B#
33,34 NUM_LED#
33,34 CAPS_LED#
32,33,35 STB_LED#

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST_B#
NUM_LED#
CAPS_LED#
STB_LED#
+3VL

R452
R471
R456
R488
R495
R544
R530
R520
R514
R511

DB@
DB@
DB@
DB@
DB@
DB@
DB@
DB@
DB@
DB@

0 _ 0 4 0 2 _ 5 % DB_LPC_FRAME#
0 _ 0 4 0 2 _ 5 % DB_LPC_AD3
0 _ 0 4 0 2 _ 5 % DB_LPC_AD2
0 _ 0 4 0 2 _ 5 % DB_LPC_AD1
0 _ 0 4 0 2 _ 5 % DB_LPC_AD0
0 _ 0 4 0 2 _ 5 % DB_LPC_RST#
0 _ 0 4 0 2 _ 5 % DB_NUM_LED#
0 _ 0 4 0 2 _ 5 % DB_CAPS_LED#
0 _ 0 4 0 2 _ 5 % DB_PWR_LED#
0 _ 0 6 0 3 _ 5 % DB_PWR

9/12

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

M i n i - C a r d /Mini-PCI/Accelerometer
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

27

of

52

VDDA_CODEC

VDDA_CODEC

1 8 , 21,25,29,33,35,36,40,43,44

+5VAMP

R287

12/02

SLP_S3#
U17

10K_0402_5%
C276

23

49.9K_0402_1%
C264

MONO_IN_HD
0.1U_0402_16V4Z

+ C198

+ C213

C193

C194

1U_0603_10V4Z

100P_0402_50V8J

C269

22U_B_10V

2 2 U _ B _ 1 0 V 0.1U_0402_16V4Z
MIC5205YM5_SOT23-5

C216

0.1U_0402_16V4Z 150K_0402_1%
R283

PCM_SPK

R213

R277
10K_0402_5%

Q48
2N7002_SOT23

C205

R206

0.01U_0402_16V7K
0.01U_0402_16V7K

143K_0402_1%

R198
0_1206_5%

VDDA_CODEC

P l a c e R 1 9 8 b e t w e e n D G ND & AGND & close to U17

R288
10K_0402_5%
C279
D
21

SB_SPKR

R279

0.1U_0402_16V4Z 150K_0402_1%

G
S

Q51
2N7002_SOT23

+3VS
VDDA_CODEC

R225
0.1U_0402_16V4Z 0.1U_0402_16V4Z

0.1U_0402_16V4Z +3VS_CODEC

SENSE_A

R293
SENSE_A_A
39.2K_0402_1%
R294
SENSE_A_B
20K_0402_1%
R286
SENSE_A_C
10K_0402_1%

0_0805_5%
C265

C224

C225

C222

C266

C251

C239

C238

0.1U_0402_16V4Z

10U_1206_16V4Z
U21

SENSE_A_A

29

SENSE_A_B

29

VDDA_CODEC

C282

0.1U_0402_16V4Z 10U_1206_16V4Z

0.1U_0402_16V4Z
1U_0603_10V4Z

PAD T48
PAD T44

29
35
35

C283

1U_0603_10V4Z

INT_MICL_C

C270

1U_0603_10V4Z

INT_MICR_C

4.7K_0402_5% DLINE_IN_R_L C 2 7 4
4.7K_0402_5%
4.7K_0402_5% DLINE_IN_R_R C 2 7 5
4.7K_0402_5%

1U_0603_10V4Z

DLINE_IN_RC_L

INT_MIC
R290
R289
R291
R292

DLINE_IN_L
DLINE_IN_R

1U_0603_10V4Z

DLINE_IN_RC_R

C247

R248
AC97_SDIN0_CODEC

PAD T46
29

MIC1

29
R297

MIC2
C273
2.67K_0402_1%

R236

R284
2.2K_0402_5%

R226
PIN44 R 2 2 4
R218
R241

MIC1_C
1U_0603_10V4Z
MIC2_C
1U_0603_10V4Z
SENSE_A
SENSE_B
@ 0_0402_5%

C272

29

@ 10K_0402_5%
LINE_IN_SENSE

Q52
G
R295

L_HP

29

R_HP

29

LINE_IN_SENSE

35

2N7002_SOT23 S
100K_0402_5%

C285
0.1U_0603_50V

10P_0402_25V8K
AC97_BITCLK_CODEC

@ 10_0402_5%

PAD T45

VDDA_CODEC

29

LINE_OUTR
T33 PAD

PAD T47

LINE_OUTL

R296
D

20

@ 10P_0402_25V8K
C249
R252
AC97_SDIN0
33_0402_5%
@ 4.7K_0402_5% PORT_A_SNS
@ 4.7K_0402_5%
10K_0402_5%
@ 4.7K_0402_5%

20
PORT_A_SNS

29

PR_INSERT#
AUD_REF

20
20

P l a c e c l ose to U14

20

11/17

C545

C259

0.1U_0805_25V7M

AC97_RST#_CODEC

CODEC_REF
AFILT1
AFILT2
AFILT4
MONO_IN_HD

AC97_SYNC_CODEC
AC97_SDOUT_CODEC

29,33

EAPD

T41
PAD
T43 PAD
T42 PAD
T38 PAD

AFILT3
PIN33
PIN40

L11
FBM-L10-160808-301-T_0603
PAD T35

C256

C250

1U_0603_10V4Z

0.1U_0402_16V4Z

T40 PAD
T39 PAD
T34 PAD
T36
T37

PAD
PAD

0.1U_0805_25V7M
PIN42

C206

0.1U_0805_25V7M

C284

0.1U_0805_25V7M

AD1981HDJSTZ-REEL_LQFP48

R219

Issued Date

GND

Compal Secret Data

S e c u r i t y C l a s s ification

@ 0_1206_5%

GNDA

2 0 0 5 /03/10

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

A C 9 7 C ODEC AD1981HD
Size

Document Number

Date:
A

Rev
1.0

L A - 2 8 2 1P
Saturday, January 14, 2006
G

Sheet

28
H

of

52

AMP. FOR INTERNAL SPEAKER

+5VALW

+5VAMP
R220
@ 10U_1206_6.3V6M

0_1206_5%
C252

C208

C246

C240

C248
D18

@ 10U_1206_6.3V6M

@ 150U_D_6.3VM

D19

0.1U_0402_16V4Z
@ PACDN042_SOT23~D

@ PACDN042_SOT23~D

@ 1U_0603_10V4Z
U20

1 0 dB
28

JP19

LC 2 6 2K e e p

R272

C261
LINE_C_OUTR

LINE_OUTR

LINE_C_R_OUTR
10K_0402_5%

0.1U_0402_16V4Z

R257

LINE_C_OUTL

LINE_OUTL

LINE_C_R_OUTL
10K_0402_5%

L_SPK+
L_SPKR_SPK+
R_SPK-

1U_0603_10V4Z
LINE_C_R_OUTR

16.5K_0402_1%
R_SPK+

R270

C260
28

10 mil width

100P_0402_50V8J
E&T_3801-04

1 0 dB
C160

R_SPK-

C161

C162

C163

100P_0402_50V8J

100P_0402_50V8J

0.1U_0402_16V4Z

1 0 dB

R256

R271

LINE_C_R_OUTL

16.5K_0402_1%
L_SPK+

100P_0402_50V8J

1 0 dB

0_0402_5%
L_SPK-

U 3 9 G a i n S ettings
18,21,25,28,33,35,36,40,43,44
34

R203

SLP_S3#

R649

MUTE_LED#

R650

11/14

1K_0402_5%
28,33

EAPD

33

A_SD

10K_0402_5%
0_0402_5%

G A I N1

1 0 dB

1 5 . 6 dB

2 1 . 6 dB

D
MAX9710ETP_QFN20
G
Q40
S
@ 2N7002_SOT23
D
G
Q39
S
2N7002_SOT23

A v ( i nv)
2

6 dB

To Audio / USB Board CONN

VDDA_CODEC
VDDA_CODEC

28 PORT_A_SNS
28 SENSE_A_A

VDDA_CODEC

R285
100K_0402_5%

G A I N0

Q49
2N7002_SOT23 S

R278
G

100K_0402_5%

R258
100K_0402_5%

Q50
2N7002_SOT23 S

+5VALW

R273
DLINE_OUT_L
G

35

Q47 S
2N7002_SOT23

DOCK_HPS#

100K_0402_5%

C188

C278

0.1U_0402_16V4Z

21
21

USB20_N2
USB20_P2

USB20_N2
USB20_P2

21
21

USB20_N3
USB20_P3

USB20_N3
USB20_P3

21 USB_OC#2
21 USB_OC#3
30,35,36 SLP_S5

0_0402_5%
R162
USB20_N2_R
R170
USB20_P2_R
0_0402_5% 0_0402_5%
R174
USB20_N3_R
USB20_P3_R
R180
0_0402_5%

D
MIC_SENSE
G
Q37 S
2N7002_SOT23

28

MIC1

28

MIC2

SENSE_A_B

MIC_SENSE
DLINE_OUT_L

28

35 DLINE_OUT_L
35 DLINE_OUT_R
28 R _ H P
28 INT_MIC
28 L _ H P

SLP_S5

2.2U_0603_6.3V6K
C281
0.1U_0603_25V7K_V1

JP25

+5VALW
VDDA_CODEC

C191
100U_D2_6.3VM
C192
100U_D2_6.3VM

R207
15_0805_5%
R217
15_0805_5%

ACES_87212-2200

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

A M P & Audio Jack

Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

29

of

52

USB CONNECTOR 1
+5VALW

USB_VCCA

USB_VCCB

+5VALW

U36
U7
JP16

SLP_S5

USB_OC#4
U35

USB_OC#4
USB_VCCB

USB_VCCA

J13
USB_OC#4
R49

W = 4 0mils

R53
USB20_N4_R
USB20_P4_R
R57

R51
USB20_N5_R
USB20_P5_R
R52

0_0402_5%
USB20_N5
USB20_P5
0_0402_5%

USB20_N5
USB20_P5

21
21

TYCO_1-1734062-1

11/17

21

SLP_S5

SLP_S5

29,35,36

TPS2041BDR_SO8

USB_OC#5

USB20_N4
USB20_P4

PAD-OPEN 3x3m

+5VALW

0_0402_5%
USB20_N4
USB20_P4
0_0402_5%

C126
220U 6.3V M

USB20_N4
USB20_P4

C122
0.1U_0402_16V4Z

21
21

C123
1000P_0402_50V7K

TPS2041BDR_SO8

C498
1000P_0402_50V7K

4.7U_0805_10V4Z

C499
0.1U_0402_16V4Z

C137

C118
220U 6.3V M

W = 4 0mils
D

USB_OC#5

21

USB20_N5
USB20_P5

( 4 A , 1 6 0 m i l s ,Via NO.=8)
D12
@ PACDN042_SOT23~D

USB_OC#5
0_0402_5%

D10
@ PACDN042_SOT23~D

SLP_S5
G548A2P1U_SO8

BT Connector
JP18
+3VAUX_BT

R85
USB20_P0_R
USB20_N0_R

0_0402_5%
0_0402_5%
R87
100_0402_5%
100_0402_5%

R674
R677

USB20_P0
USB20_N0

USB20_P0
USB20_N0

21
21

BT_LED 32
CH_DATA 27
C H _ C L K 27

11/23
ACES_87212-0800

D16
@ PACDN042_SOT23~D

+3VALW

+3VAUX_BT
Q12

SI2301BDS_SOT23
D

0.1U_0402_16V4Z

C140

R69

1U_0603_10V4Z

100K_0402_5%

C144

BT_OFF

C142
4.7U_0805_10V4Z

0.01U_0402_16V7K
C138

R70
21

C143

@ 0.1U_0402_16V4Z
47K_0402_5%

9/14

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

U S B I/O & BT Connector

Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
1

30

of

52

+3VS
RP29
DCD#1
RI#1
CTS#1
DSR#1
+5VS
4.7K_1206_8P4R_5%
IRRX
R427
1K_0402_5%

D31
CH751H-40_SC76

+5VS_PRN
RXD1
U29

21,33 NPCI_RST#
20,27 PLT_RST_B#
+3VS

0_0402_5%
@ 0_0402_5%
10K_0402_5%

10K_1206_8P4R_5%
R428
R437

SIO_RST#
SIO_PD#
PM_CLKRUN#
CLK_PCI_SIO
SIRQ
SIO_PME#

21,23,32,33 PM_CLKRUN#
15 CLK_PCI_SIO
21,23,32,33 SIRQ

SIO_IRQ
10K_0402_5%
SIO_DPIO45
10K_0402_5%

+3VS

R417

SIO_GPIO40
PID0
PID1
SIO_GPIO43
SIO_GPIO44
SIO_DPIO45
CARD_ID#
SER_SHD
SIO_GPIO10
SIO_GPIO11
SIO_GPIO12
SIO_IRQ

R8
CARD_ID#

H i g h : C ompal MXM
L o w : S t andard MXM
R421
EXPCRD_RST#

35

SER_SHD

35

0_0402_5%

4.7K_1206_8P4R_5%
RP27
LPD7
LPD6
LPD5
LPD4

LPTINIT# 35
LPTSLCTIN# 35
LPD0 35
LPD1 35
LPD2 35
LPD3 35
LPD4 35
LPD5 35
LPD6 35
LPD7 35
LPTSLCT 35
LPTPE 35
LPTBUSY 35
LPTACK# 35
LPTERR# 35
LPTAFD# 35
LPTSTB# 35

R422
SW_EXPCRD_RST#

LPD3
LPD2
LPD1
LPD0

RP26
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
4.7K_1206_8P4R_5%
RP25
LPTSTB#
LPTAFD#
LPTERR#
4.7K_1206_8P4R_5%
R414

SW_EXPCRD_RST#

LPTSLCTIN#

9/8

10K_0402_5%

4.7K_1206_8P4R_5%
LPTINIT#
LPTSLCTIN#
LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7
LPTSLCT
LPTPE
LPTBUSY
LPTACK#
LPTERR#
LPTAFD#
LPTSTB#

CLOCK

+3VS

TXD1 35
DSR#1 35
RTS#1 35
CTS#1 35
D T R # 1 35
RI#1 35
D C D # 1 35

FIR

CLK_14M_SIO

CLK_14M_SIO

RP28
1K_0402_5%

IRRX

10K_0402_5%
15

10K_0402_5%

SERIAL I/F

20,27,32,33 LPC_FRAME#
20 L P C _ D R Q # 0

R431
R432
R433

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

PARALLEL I/F

SIO_GPIO12
SIO_GPIO10
SIO_GPIO44
SIO_GPIO43

LPC_FRAME#
LPC_DRQ#0

GPIO

RP30

35

R403

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC I/F

20,27,32,33
20,27,32,33
20,27,32,33
20,27,32,33

4.7K_0402_5%
R418

+3VS

+3VS

POWER

R435

LPTINIT#

PID0
4.7K_0402_5%
10K_0402_5%

C391

C397

C383

C401

LPC47N217_STQFP64

B a s e I / O A d d r e ss
0 = 02Eh
* 1 = 04Eh

R436
PID1

10K_0402_5%

0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z

R429
SIO_GPIO11
10K_0402_5%
R438
SIO_GPIO40
CLK_PCI_SIO

10K_0402_5%

CLK_14M_SIO

R434
@1 0 _ 0 4 0 2 _ 5 %

R420
@1 0 _ 0 4 0 2 _ 5 %

C410
@ 18P_0402_50V8K

C399
@ 10P_0402_25V8K

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

S U P E R I /O LPC47N217
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

31

of

52

+5VS

+3VS

BIOS ROM

47K

12/8

R221
10K

2.2K_0402_5%

WL_LED#

+3VALW

8/26

U14

W i r e l e s s LED

+3VALW
SPI_WP#

8/26
U13

SPI_CS#

SPI_WP#
SPI@ 3.3K_0402_5%
R155
SPI_HOLD#
SPI@ 3.3K_0402_5%

SPI_CLK
SPI_SI
21

SPI_CS#

21

SPI_CLK

21

34

R108

SPI_HOLD#
SPI_CS#
SPI@

30

SST25LF080A_SO8-200mil

SPI_SO
SPI@
@ MX25L8005MI-15G_SO8-150mil

SPI_SO

47_0402_5%

BT_LED

WL_LED

G
Q35
2N7002_SOT23

9/12

100K_0402_5%

8/23

WL_LED
G
Q36
2N7002_SOT23

21

R 1 2 9 1 should be placed less

t h a n 100 mils from U61 & U65.

R199
100K_0402_5%
R95

BT_LED

BT_LED

R109
SPI_SI

M i n i - P C I E Card LED

WL/BT_LED

SPI_CLK

S P I _SI

WL_LED

B L U E LED

8/26

SPI_HOLD#

SPI_WP#

0.1U_0402_16V4Z

D28

LTST-S110TBKT-5A

+3VALW

C172
SPI@

27

Q34
DTA114YKA_SC59

S
R212
@0 _ 0 4 0 2 _ 5 %

T h e c h i p m u st be placed on PCB easily

r e w o r k place for debug.

47K

21

HDD_STP

+3VS

9/6

2N7002_SOT23
Q41
D

+3VL
HDD_STP

47K

G
S

33

AMBER_BATLED#

R211

10K

AMBER_BATLED#
Q44
DTA114YKA_SC59

+3VL

10K

HDD_STP#
100K_0402_5%

+3VS

Q42

47K
C

47K
C

DTA114YKA_SC59
33

10K

GREEN_BATLED#

GREEN_BATLED#

20

10K

IDE_LED#

IDE_LED#

Q45
Q46
DTA114YKA_SC59
DTA114YKA_SC59
R233

R234
R243

R242

150_0402_5% 150_0402_5%
150_0402_5% 150_0402_5%

TPM1.2 on board
+3VS

B a t t e r y LED

+3VALW

C393

C394

21,33

LPC_PD#

L
33

P l ace R1447 close to Y8.1

R397

CLK_TPM

G R E EN

1/4

TPM1.2@ 0.1U_0402_16V4Z

TPM_GPIO
TPM_GPIO2

PAD
PAD

+3VS

T23
T24

+3VS

B a s e I / O A d d r e ss
R378
0 = 02Eh
* 1 = 04Eh
TPM1.2@ 4.7K_0402_5%

Finger printer
+3VL

C124

SLB 9 6 3 5 T T 1 . 2
R390
TPM1.2@ 0 _ 0 4 0 2 _ 5 %

R377
@ 4.7K_0402_5%

0.1U_0402_16V4Z

9/8
21
21

TPM_XTALO

USB20_N1
USB20_P1

9/8

JP15

47K

0_0402_5%
USB20_N1
USB20_P1

USB20_N1_R
USB20_P1_R

R46
R47

27,33,35

0_0402_5%

STB_LED#

STB_LED#

DTA114YKA_SC59

9/13

D9
@ PACDN042_SOT23~D

34

ACES_87212-0800
TPM1.2@ 18P_0402_50V8J
C365

STB_LED

TPM1.2@ SLB 9635 TT 1.2_TSSOP28

TPM_XTALI

R222

TPM1.2@ 32.768KHZ_12.5P_1TJS125BJ2A251

150_0402_5%
R394

TPM1.2@ 1 0 M _ 0 4 0 2 _ 5 %
Y5

P l a ce R1365/R1366 close to JP38.2/JP38.3

a n d m i n i m ize the stub length.
R570
USB20_N1_R

C341

@0 _ 0 4 0 2 _ 5 %
USB20_N1_R_MC

TPM_XTALO
USB20_P1_R

TPM1.2@ 18P_0402_50V8J

R569

2 0 0 5 /03/10

Issued Date

USB20_P1_R_MC
@0 _ 0 4 0 2 _ 5 %
9/8

USB20_N1_R_MC

27

USB20_P1_R_MC

27

Compal Secret Data

S e c u r i t y C l a s s ification

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

P O W E R LED
G R E EN
A

17-21SYGC/S530-E1/TR8_GRN
D29

Compal Electronics, Inc.

Title

T C G / B I O S ROM/PS2/LED/SW
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

10K

Q38
TPM_XTALI

@ 0_0402_5%

R375
TPM1.2@ 0 _ 0 4 0 2 _ 5 %

D27

A M B ER

U26

LPC_AD0
20,27,31,33 LPC_AD0
LPC_AD1
20,27,31,33 LPC_AD1
LPC_AD2
20,27,31,33 LPC_AD2
LPC_AD3
20,27,31,33 LPC_AD3
+3VS
LPC_FRAME#
20,27,31,33 LPC_FRAME#
PLT_RST#
7,19,20,21,23,25,27,33 PLT_RST#
R402
TPM1.2@ 10K_0402_5%21,23,31,33 SIRQ
SIRQ
LPC_PD#
CLK_PCI_TCG
R401
15 CLK_PCI_TCG
TPM1.2@ 0 _ 0 4 0 2 _ 5 %
C392
R415
+3VS
@ 10_0402_5%
@ 10P_0402_50V8K
PM_CLKRUN#
21,23,31,33 PM_CLKRUN#

R379
@ 4.7K_0402_5%

G R E EN

C350

TPM1.2@ 0.1U_0402_16V4Z
TPM1.2@ 0.1U_0402_16V4Z

H D D LED

1 9 - 22UYSYGC/S530-A2/TR8_ G/Y

A M B ER

TPM1.2@ 0.1U_0402_16V4Z
C349

D30

1 9 - 22UYSYGC/S530-A2/TR8_ G/Y

Saturday, January 14, 2006

Sheet
1

32

of

52

+3VL

C196

C215

0.1U_0402_16V4Z

C243

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C255
0.1U_0402_16V4Z

+3VS

C257
4.7U_0805_10V4Z

C244

C226

C209

C236

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0805_10V4Z

+3VL

B I O S d e b u g port
P l a c e u n d e r KB area

RP21
+3VL

R205
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13

KSI7
KSI6
KSI5
KSI4
10K_1206_8P4R_5%

34

K S I [ 0..7]

R192

10K_0402_5%

rface

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

TP_CLK
10K_0402_5%
R197
TP_DATA

RP23
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
10K_1206_8P4R_5%

+3VS

TP_CLK
TP_DATA
KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

34 TP_CLK
34 TP_DATA
35 KBD_CLK
35 KBD_DATA
35 PS2_CLK
35 PS2_DATA

N o t e : R 94 must be removed when

R 1 3 54 stuff and R87 remove.

PM_CLKRUN#
SIRQ
CLK_PCI_EC
RUNSCI_EC#

21,23,31,32 PM_CLKRUN#
21,23,31,32 SIRQ
15 CLK_PCI_EC
21 RUNSCI_EC#

R216
LPCPD#
10K_0402_5%
R262

21,31 NPCI_RST#
7,19,20,21,23,25,27,32 PLT_RST#
21,32 LPC_PD#
P i n 3 4 2 5 0 - - L P CPD#

NPCI_RST# R 6 5 1
PLT_RST# R 6 5 2
R215
ADP_EN
R223

0_0402_5%
@0 _ 0 4 0 2 _ 5 %
@0 _ 0 4 0 2 _ 5 %
@0 _ 0 4 0 2 _ 5 %

R265

@ 0_0402_5%
@ 0_0402_5%

18,25,40,41,42,47

GATEA20

20

+3VL

NUM_LED# 27,34
SLP_S3# 18,21,25,28,29,35,36,40,43,44
0_0402_5%
KSO16 34
P i n 1 2 5 0 - - T E S T P i n ( N C !! )
0_0402_5%
EAPD
28,29

RP24
AB1A_CLK
AB1A_DATA
AB1B_CLK
AB1B_DATA
4.7K_1206_8P4R_5%
R250
NUM_LED#
100K_0402_5%
R246

KSO17

34

PM_POK 7,21
2 5 0 - - 3 2 K H z_OUT
2 5 0 - - R e s e t Out

1 0 _ 0 4 0 2 _ 5 % 10P_0402_50V8K
@
@

R274
PM_POK
10K_0402_5%

AMBER_BATLED# 32
STB_LED# 27,32,35
CAPS_LED# 27,34

EC_GPIO12

+3VL

+3VL
EC_GPIO19 R 2 5 1

ADP_ID

0_0402_5%
0_0402_5%
R260

1U_0603_10V4Z

0.1U_0402_16V4Z

S_CLK

47

CB_CLK

@ 33_0402_5%
R261

24

ADP_EN

ADP_EN

0_0402_5%
R399

A GND FILTER

32.768KHZ_12.5P_1TJS125DJ2A073

CLK_TPM

@ 0_0402_5%
MODE
PGM
FWP#

0.1U_0402_16V4Z

47

@ ACES_85201-0602

32

F o r K B C debugging used.

R268
@ 10K_0402_5%
R267
@ 1K_0402_5%
R276
@ 1K_0402_5%

C254

VCC1_PWRGD
NUM_LED#
STB_LED#
CAPS_LED#

47

ADP_PS0

0_0402_5%
C253

JP22

47

ADP_PS1

EC_GPIO10 R 2 1 4

C268
C263

C245

CLK_14M_KBC

P i n 9 1 2 5 0 - - n D M S_LED

EC_GPIO12 R 2 6 4

10P_0402_50V8J

46
19,23
46

+RTCVCC
KBC1021_TQFP100

C267

ADP_PRES
CH751H-40_SC76
R255
+3VL
10K_0402_5%
D26

FWP#

Y3

10P_0402_50V8J

R259
210K_0402_1%
EC_GPIO12
R263
100K_0402_5%
EC_GPIO13
R194
100K_0402_5%

AB1A_DATA 46
AB1A_CLK 46

EC_GPIO10
AMBER_BATLED#
STB_LED#
CAPS_LED#

C237
@ 10P_0402_50V8J

+3VL
THM_MAIN#

41

THM_MBAY#
PCI_SERR#
THM_MAIN#

R647
100K_0402_5%
120K_0402_5%

@ ACES_85201-0602

AB1B_DATA
AB1B_DATA 46
AB1B_CLK
AB1B_CLK 46
R204
0_0402_5%
A_SD 29
PGM
P i n 5 6 2 5 0 - - PGM
P i n 8 3 2 5 0 - - n E A ( p u l l up !! )
EA#
R238
CLK_14M_KBC
0_0402_5%
CLK_14M_KBC 15
S_CLK
PM_POK
PWR_GD_EC
Pin58
VCC1_PWRGD
V C C 1 _ P W R G D 37
EC_GPIO19
Pin49
P i n 5 0 2 5 0 - - 2 4 M H z_Out
TEST
P i n 5 2 2 5 0 - - X OSEL
R249
300_0402_5%

R232
@ 10_0402_5%

GPIO9
GPIO8

D24
BATCON

AB1A_DATA
AB1A_CLK

@2M_0402_5%
R266

20

KSO16
KSO17

A c c e s s B u s I n t e r face

CLK_PCI_EC

KB_RST#

34

CH751H-40_SC76

LPCPD#

VCC1_PWRGD

D25

41

ON/OFFBTN_KBC#
LOW_BAT# 21
KSO14 34
KSO15 34
PM_RSMRST# 21

BATCON
EC_GPIO12
EC_GPIO13
THM_MBAY#
PCI_SERR#
THM_MAIN#
A20M
NUM_LED#
SLP_S3#
R185
MODE
P i n 5 7 2 5 0 - - MODE
R202

CRY1
CRY2
B

JP21

10K_0402_5%

INV_PWM 17
CH751H-40_SC76
FAN_PWM 4
C H G C T R L 40,41
P i n 8 2 2 5 0 - - nFWP

PM_RSMRST#
GPIO8 R 2 8 0
GPIO9 R 2 8 1

LPC
Bus

10K_0402_5%

11/14

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_FRAME#

20,27,31,32 LPC_AD3
20,27,31,32 LPC_AD2
20,27,31,32 LPC_AD1
20,27,31,32 LPC_AD0
20,27,31,32 LPC_FRAME#

RUNSCI_EC#

P o w e r M g m t / S IRQ

BATSELB_A#

FWP#
ON/OFFBTN_KBC#
LOW_BAT#
KSO14
KSO15

M i s c e l l a n e ous

KBC_PWR_ON 42
GREEN_BATLED# 32

BATSELB_A#
KBRST#
INV_PWM
FAN_PWM
CHGCTRL
Keyboard/Mouse Inte

P i n 3 2 5 0 : K S O 1 2 / O U T 8 /KBRST
+5VS

KBC_PWR_ON
GREEN_BATLED#

erface

RP22

+3VL

U18

K S O [0..13]

K S O [0..13]

General Purpose I/O Int

34

10K_1206_8P4R_5%

S M S C _ L PC47N250_TQFP-100P

KSI3
KSI2
KSI1
KSI0

R268,R280,R281
s t u f f when KBC LPC47N250 used

1 . F o r normal operation:
+3VL

Un-install R29,R65

J9
PGM
NO SHORT PADS
PWR_GD_EC

R670
R669

0_0402_5% PWR_GD
@ 0 _ 0 4 0 2 _ 5 % PGD_IN

11/21

P W R _ G D 18,36,37,45,47
PGD_IN 37,45

FWP#
TEST
EA#

2 5 0@
R 1 27
R 1 28
R 9 77
R 62

1 0 2 1@
R 1 29
R 1 31
R 78

R275
@ 1K_0402_5%
R254
@ 1K_0402_5%
R235
1K_0402_5%

2 . F o r K BC internal ROM flash:

2 0 0 5 /03/10

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

L P C 4 7 N 1021
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

Install R29,R65

Compal Secret Data

S e c u r i t y C l a s s ification
Issued Date

R282
1K_0402_5%

Saturday, January 14, 2006

Sheet
1

33

of

52

INT_KBD CONN.

SWITCH BOARD.
+3VS

+3VL

+5VS

JP1

29

STB_LED
KSI0
NUM_LED#
CAPS_LED#
KSI1
WL/BT_LED
LID_SW#_2nd
KSI2

ON/OFF#
MUTE_LED#
KSO2
KSI6
KSI7
KSI5

MUTE_LED#

STB_LED

33

K S O [0..17]

33

K S I [ 0..7]

JP12

WL/BT_LED

LID_SW#

11/3

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7

NUM_LED# 27,33
CAPS_LED# 27,33
32

ACES_88028-3000
LID_SW#
0_0402_5%

K S I [ 0..7]

32

KSI4

LID_SW#_2nd
R1

K S O [0..17]

17,21

MDC 1.5 Conn.

KSO0
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO14
KSO11
KSO12
KSO1
KSO17
KSO13
KSO15
KSO16
KSI2
KSI3
KSI6
KSI4
KSI1
KSI5
KSI0
KSI7
ACES_85203-26021

+3VS

JP26

20

AC97_SDOUT_MDC

AC97_SDOUT_MDC

20

AC97_SYNC_MDC
20 AC97_SDIN1
20 AC97_RST#_MDC

U p d a t e t o 1 8 x 8 a n g e lfire keyboard matrix

R239
33_0402_5%

AC97_SYNC_MDC
AC97_SDIN1_MDC
AC97_RST#_MDC

CP1
AC97_BITCLK_MDC

AC97_BITCLK_MDC

R209
C221
@ 1 0 _ 0 4 0 2 _ 5 % @ 10P_0402_25V8K

+3VS

KSO12
KSO1
KSO17
KSO13
100P_1206_8P4C_50V8

MDC1.5@ TYCO_1-179396-2~D

C220

C223

100P_1206_8P4C_50V8

CP2

CP5

KSO5
KSO6
KSO7
KSO8

Connector for MDC Rev1.5

MDC1.5@ 1000P_0402_50V7K

CP4

KSO0
KSO2
KSO3
KSO4

20

C204
@ 4.7U_0805_10V4Z

KSO15
KSO16
KSI2
KSI3
100P_1206_8P4C_50V8

MDC1.5@ 0.1U_0402_16V4Z

100P_1206_8P4C_50V8

CP3

CP6

KSO9
KSO10
KSO14
KSO11

KSI6
KSI4
KSI1
KSI5
100P_1206_8P4C_50V8

100P_1206_8P4C_50V8
CP7
KSI0
KSI7

100P_1206_8P4C_50V8

Power button
+3VL

+3VL

+3VL
R163

R167
100K_0402_5%

35

ON/OFF#

TrackPoint CONN.

100K_0402_5%
ON/OFFBTN_KBC#

U15F
SN74LVC14APWLE_TSSOP14
R172

ON/OFF#
C177
1U_0603_10V4Z

1U_0603_10V4Z

T/P BOARD.

33

+5VS

JP11
+3VALW

Q29
2N7002_SOT23

G
100K_0402_5%
C183

ON/OFFBTN_KBC#

JP14

+5VS

R179

SP_CLK
SP_DATA

S
100K_0402_5%

+5VS

D23
ON/OFFBTN#

ON/OFFBTN#

E&T_6700-Q08N-00R

21

C116

33 TP_DATA
33 TP_CLK

0.1U_0402_16V4Z

C490
SP_DATA

0.1U_0402_16V4Z

SP_CLK

11/3

RB751V_SOD323

+5VS

TP_DATA
TP_CLK

ACES_87212-0800

Compal Secret Data

S e c u r i t y C l a s s ification
Issued Date

2 0 0 5 /03/10

D e c i p h e red Date

2 0 0 6 /03/10

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

M D C / K BD/ON_OFF/LID
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

Saturday, January 14, 2006

Sheet

34

of

52

+5VALW

DOCK CONN. 184PIN

R357

11/22

220K_0402_5%

11/18

JP2
SLP_S5#_5R

L14
KC FBM-L18-453215-900LMA90T_1812
VIN
1

DOCKVIN
C314

29,30,36

Q77

SLP_S5

G
Q62
2N7002_SOT23

C305

1000P_0402_50V7K

DOCK_MOD_RING
DOCK_MOD_TIP

R671

PREP#
G

ACES_85205-0200

@ 22K_0402_5%

S
@ 2N7002_SOT23

11/23

1000P_0402_50V7K
C546
@ 1U_0603_10V6K

JP27B

JP27A
DOCKVIN

34

ON/OFF#

26
26

MDO2+
MDO2-

26
26

MDO0+
MDO0-

16 D_VSYNC
16 D_HSYNC
16 D_DDCDATA
16 D _ D D C C L K
18 DVI_DETECT

ON/OFF#

DETECT

MDO2+
MDO2-

MDO3+
MDO3-

MDO3+ 26
MDO3- 26

MDO0+
MDO0-

MDO1+
MDO1-

MDO1+ 26
MDO1- 26

LAN_ACT#_DOCK
LANLINK_STATUS#_DOCK

PWR_LED
R346
DVI_DDC_CLK
DVI_DDC_DAT

D_DDCDATA
D_DDCCLK
DVI_DETECT

DVI_TX2+
DVI_TX1-

16,18 M_COMP
16,18 M_CRMA
16,18 M_LUMA

47

18

DVI_TX2+

18

DVI_CLK+

DVI_TX0+

18
USB20_N6

USB20_N6 R 3 0 1
USB20_P6 R 3 0 0

DVI_TX1+

18
21

USB20_P6

DVI_CLK-

18

21

USB20_N7

DVI_CLK+

18

21

USB20_P7

DCD#1
RI#1
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1

31

DCD#1
31 RI#1
31 D T R # 1
31 CTS#1
31 RTS#1
31 DSR#1
31 TXD1
31 RXD1

31
31
31

DOCK_ADP_SIGNAL
DOCK_ID

18

DVI_TX0+

18

DLINE_IN_L
DLINE_IN_R

PCIE_TXP4
PCIE_TXN4

PCIE_C_RXP4

USB20_P6_R

PCIE_C_RXN4

R3
PCIE_RXP4
0_0402_5%
R4
PCIE_RXN4
0_0402_5%

0_0402_5%
0_0402_5%
USB20_N7 R 3 0 4

29
29

21
21

PCIE_RXP4

21

PCIE_RXN4

21

USB20_N7_R
0_0402_5%

USB20_P7 R 2 9 8

CLK_PCIE_DOCK

CLK_PCIE_DOCK

USB20_P7_R
0_0402_5%

31

28
28

DLINE_OUT_L
DLINE_OUT_R

PCIE_TXN4

CLK_PCIE_DOCK#
SER_SHD
EXPCRD_RST#
DETECT

31 SER_SHD
EXPCRD_RST#

PREP#

DOCK_ADP_SIGNAL
DOCK_ID 21
+3VS

15

CLK_PCIE_DOCK#

PREP#
VA_ON#

15

21,26

R302

C291

1K_0402_5%

0.1U_0402_16V4Z

+5VS

DOCK_ID

5/24

DLINE_IN_L
DLINE_IN_R

PCIE_TXP4

USB20_N6_R

R9

LPTSTB#
LPTAFD#
LPTERR#

LPTSTB#
LPTAFD#
LPTERR#

DVI_TX0-

KBD_DATA 33
KBD_CLK 33
CPPE# 15,19
PS2_DATA 33
PS2_CLK 33
DOCK_HPS# 29

DLINE_OUT_L
DLINE_OUT_R

ACOCP_EN#
DVI_TX0-

KBD_DATA
KBD_CLK
CPPE#
PS2_DATA
PS2_CLK
DOCK_HPS#

18
18

21

DVI_TX1+

LINE_IN_SENSE

DVI_TX2-

DVI_TX1-

DVI_CLK28

11/22

DVI_DDC_CLK
DVI_DDC_DAT

DVI_TX2-

D_RED
D_GREEN
D_BLUE

SLP_S5#_5R
10K_0402_5%

LPTACK#
LPTBUSY
LPTPE
LPTSLCT
LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1
LPD0
LPTSLCTIN#
LPTINIT#

31 LPTACK#
31 LPTBUSY
31 LPTPE
31 LPTSLCT
31 LPD7
31 LPD6
31 LPD5
31 LPD4
31 LPD3
31 LPD2
31 LPD1
31 LPD0
31 LPTSLCTIN#
31 LPTINIT#

C1
@ 10K_0402_5%
@ 22U_0805_6.3V4Z
DOCK_MOD_TIP
9/15

DOCK_MOD_RING
ADP_SIGNAL
R299

JAE_SP03-14588-PCL03

JAE_SP03-14588-PCL03

DOCK_ADP_SIGNAL

N o t e : Place C1 close to JP27.P2 pin

1K_0402_1%

Place them close to U50/U51/U52

D_RED

R7

RED
@ 0_0402_5%

D_GREENR 5

GREEN
@ 0_0402_5%

D_BLUE R6

BLUE
@ 0_0402_5%

+3VALW

V_3P3_LAN

LAN_ACT#_DOCK
D

R372
+3VS

+3VS

+3VS

R352

10K_0402_5%

Q58
2N7002_SOT23

G
S

C8

C5

C6

U3

18
21

D_BLUE
16 B L U E

ISO_PREP#

0.1U_0402_16V4Z

D_BLUE
BLUE

18

ISO_PREP#

U1

U2

0.1U_0402_16V4Z
D_GREEN
16 GREEN

10K_0402_5%

LAN_ACT#

PWR_LED

LANLINK_STATUS#_DOCK

LAN_ACT#

18

ISO_PREP#

D_RED
16 RED

D_RED
RED

D
27,32,33

ISO_PREP#

STB_LED#

D
Q61
2N7002_SOT23

Q59
2N7002_SOT23

S
LANLINK_STATUS#

FSA66P5X_SC70-5

FSA66P5X_SC70-5

18,21,25,28,29,33,36,40,43,44

FSA66P5X_SC70-5

2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

25,26

Compal Electronics, Inc.

Title

Docking CONN.
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

LANLINK_STATUS#

SLP_S3#

Compal Secret Data

S e c u r i t y C l a s s ification

25,26

0.1U_0402_16V4Z

D_GREEN
GREEN

Saturday, January 14, 2006

Sheet
E

35

of

52

+5VALW to +5VS Transfer

+1.8VS

+5VS

D
C277

Q53
SI2306DS-T1 1N_SOT23

U22

+1.8V to +1.8VS Transfer

+1.8V

+5VALW

C295

C296

C280

+5VALW

C271
SI4800DY_SO8
10U_0805_10V4Z

1U_0603_10V4Z

1U_0603_10V4Z

10U_0805_10V4Z

RUNON

R62
RUNON
0.1U_0402_16V4Z

100K_0402_5%

29,30,35

SLP_S5

SLP_S5

+3VALW to +3VS Transfer

B+
J3

+3VALW

21,44

+3VS

SLP_S5#

SLP_S5#

Q9
2N7002_SOT23

G
S

U37
PAD-SHORT 2x2m

10U_0805_10V4Z

R582
C514
330K_0402_5%

C510

C509

SI4800DY_SO8
10U_0805_10V4Z
+VCCP

RUNON

+VCCP

0.1U_0402_16V4Z
J15
2

Q75
2N7002_SOT23

+3VS
+3VALW

C155

@ 0.1U_0603_50V4Z

+3VALW

470_0402_5%

+3VS

C141

@ 0.1U_0603_50V4Z

+5VS

+3VS

C139

@ 0.1U_0603_50V4Z

+5VS

+1.5VS

C524

@ 0.1U_0603_50V4Z

+3VS

C419

0.1U_0402_16V4Z

C290

0.1U_0402_16V4Z

C501

+3VALW

0.01UF_0402_25V7K

@ 0.1U_0603_50V4Z

+3VS

D
G

0.1U_0603_50V4Z

C526

R583

PAD-SHORT 2x2m
SLP_S3

C29

+3VS

+3VL

R244
100K_0402_5%

SLP_S3

+2.5VALW to +2.5VS Transfer

D
+2.5VALW

+2.5VS

18,21,25,28,29,33,35,40,43,44

SLP_S3#

SLP_S3#

Q43
2N7002_SOT23

U32

C456
C487
SI4800DY_SO8
10U_0805_10V4Z

C458
10U_0805_10V4Z

RUNON
0.1U_0402_16V4Z

Discharge circuit

PWR_GD

+0.9V

+1.8V

+3VS

+2.5VS

+1.8VS

18,33,37,45,47

+1.5VS

+5VS
R94

R571

R574

R138

R32

470_0402_5%

470_0402_5%

470_0402_5%

470_0402_5%

R93

R577

470_0402_5%

D
SLP_S5
R573
@ 0_0402_5%
SLP_S3
R572
0_0402_5%

D
Q73
2N7002_SOT23

G
S

SLP_S5

D
Q74
2N7002_SOT23

G
S

SLP_S3

D
Q19
2N7002_SOT23

G
S

470_0402_5%

SLP_S3

D
Q7
2N7002_SOT23

G
S

SLP_S3

Q18
2N7002_SOT23

470_0402_5%

SLP_S3

D
Q16
2N7002_SOT23

SLP_S3
G

Q72
2N7002_SOT23

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

DC/DC Circuits
Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
E

36

of

52

+1.8VS

+3VS

+3VS

+3VL

+3VL
+3VL
+3VL

R139

R158

1K_0402_5%

R157

330_0402_5%

R188

330_0402_5%

U15A

U15B

+3VL

D20

R171

10K_0402_5%

R184
47K_0402_5%

C
Q25
MMBT3904_SOT23

B
C
B

RB751V_SOD323
SN74LVC14APWLE_TSSOP14

SN74LVC14APWLE_TSSOP14

VCC1_PWRGD

100K_0402_5%
U15D
+3VS

E
Q26
MMBT3904_SOT23

33

C181

Q33
2N7002_SOT23

0.1U_0402_16V7K

C186

SN74LVC14APWLE_TSSOP14

0.1U_0402_16V7K

+5VS

+3VL

R156
10K_0402_5%
C176

R177

J8

0.1U_0402_16V4Z

PWR_GD

180K_0402_5%

PWR_GD

18,33,36,45,47

PAD-SHORT 2x2m
U15C

UNUSED PARTS

Q23
2N7002_SOT23

G
S
SN74LVC14APWLE_TSSOP14
R181

C190

560K_0402_5%

+1.5VS

R196
1K_0402_5%

0.1U_0402_16V7K

+2.5VS

+2.5VS

R178

+3VL

R210

330_0402_5%

330_0402_5%

U15E

C
43

VCCP_POK

C502

H6
H8
HOLEA HOLEA

H25
HOLEA

H26
HOLEA

H16
HOLEA

H13
H18
HOLEA HOLEA

H19
HOLEA

H27
HOLEA

H24
HOLEA

H20
HOLEA

H17
HOLEA

C500

FM1

FM3

FM2

FM4

FM5

FM6

CF1

CF2

CF3

CF4

CF5

CF6

0.1U_0402_16V4Z
D33

R578

RB751V_SOD323

U33

PWR_GD

U34
R580
100K_0402_5%

0_0402_5%
R579

SN74LVC1G17DBVR_SOT23-5
PGD_IN_1

H5
HOLEA

+3VS

N e e d be tune to
3 m s e c time delay

0.1U_0402_16V4Z

PGD_IN_1

H4
HOLEA

SN74LVC14APWLE_TSSOP14

+3VS

11/21

H2
HOLEA

S
Q31
MMBT3904_SOT23

Q32
MMBT3904_SOT23

B
E

@ 0_0402_5%

H1
HOLEA

Q24
2N7002_SOT23

G
C
B

H3
HOLEA

45

C497

PGD_IN

PGD_IN

CF7

CF9

CF11

CF12

CF8

CF10

33,45

SN74LVC1G17DBVR_SOT23-5

0.1U_0603_16V7K

R581
15,45

CLK_ENABLE#

CLK_ENABLE#
@ 0_0402_5%
PAD1

M1
HOLEA

M2
HOLEA

H11
H12
H23
H21
HOLEA HOLEA HOLEA HOLEA

H10
HOLEA

H14 H9
HOLEAHOLEA

H15
HOLEA

PAD-R118x63

1/4

CPU

Compal Secret Data

S e c u r i t y C l a s s ification
Issued Date

2 0 0 5 /03/10

D e c i p h e red Date

2 0 0 6 /03/10

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

POK CKT
Size

Document Number

Rev
1.0

L A - 2 8 2 1P
Date:

Saturday, January 14, 2006

Sheet

37

of

52

VIN

AC
A dapter
in

A D P _EN#

A PL5508
LDO
( 2.5V)

+ 3VALWP
L M358
T hermal
P rotector

S W I TCH

M A I NPWON

E N BL2 E N BL1

B+

A PL5151
LDO
(3V)

VL

VL

+ 3VALWP

+ 5 VS

T PS51020
D C/DC
( 3V/5V)

+ 2 .5VALWP 0.4A
VL

S HDN#

P W R_GD

B+

+ 3 VLP 0.1A

V CC

S H DN#

+ 5VALWP
VIN

I S L 6260&ISL6208
D C/DC
( C PU_CORE)

B Q24703
C harger

M AX8743
D C/DC
( 1 .05V/1.5V)

B+
B

S L P _S3#

+ 1 .5VSP 4.2A
C PU_CORE
( 44A)
B

+ 1 . 05V_VCCP 6.4A

+ 5 V ALWP

E N BL1/ENBL2

B ATSELB_A
B attery
S elector
C ircuit

B A TSELB_A#

VCC
B attery A
8 Cell

B attery B
8 Cell

B+
S W I TCH

S W I TCH

S W I TCH

B attery
C onnector
A

B attery
C onnector
B

S L P _ S 3 # /SLP_S5#

T PS51116
D C/DC
( + 1 .8VP/+0.9VSP)

+ 1.8VP 7A

+ 0.9VP 2A
S 3/S5
A

BATT
B A T T_A

T itle

POWER BLOCK DIAGRAM

B A T T_B
S ize
D a t e:
5

D o c u m e n t N u m ber
S a t u r d a y , J a n u a r y 1 4, 2006

Rev
S h eet

38
1

of

52

VIN
PJP13
PL1
C 8 B B P H 853025_2P

A D P _ SIGNAL

1
1

PR1
1 5 K_0402_5%

PC4
1 0 0 0 P_0402_50V7K

PC2
1 0 0 0 P _0402_50V7K

PC3
1 0 0 P _0402_50V8J

1
2

1
2
F O X _ J PD113E-LB103-7F

PC1
1 0 0 P _0402_50V8J

A D P IN

Security Cl assification
I s s u ed Date

C o m p a l S e cret Data
2005/03/10

Decipher ed Date

2006/03/10

T H IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R ADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

T itle

Compal Electronics, Inc.

DCIN

Size
D o c u m ent Number
Custom

R ev

LA-2821

D a te:

S a t u r d a y , January 14, 2006

D

Sh eet

39

of

52

VIN

P2

BATT
PQ3
AO4407_SO8

P4

B+

PR338
100_0402_1%
ADP_PRES

PD33
1N4148_SOD80
ADP_EN#

PC198
1U_0603_6.3V6M

47

PD6
RLZ16B_LL34

D
BQ24703_QFN28

PC19
SE_CHG+
0.1U_0402_16V7K

150P_0402_50V8J
PC21

SE_CHG-

PC22
0.1U_0402_10V6K

ADP_PRES

C V = 1 6 . 8 V (8 CELLS LI-ION)
C C=3A

PR43
150_0402_1%

PU4
SN74LVC1G17DBVR_SOT23-5

LM393DG_SO8

PD8
EC31QS04

BATT

18,25,33,41,42,47

+3VL

PR47
604K_0603_0.1%

PR50
10K_0603_0.1%

PR52
4.7K_0402_5%

+3VL
PR56

BATT
PR51
604K_0402_1%

PU5A

LX_CHG
PL3
16UH_SIL104R-160PF_3.6A_30%
PR38
3K_0402_1%

PC18
4.7U_0805_6.3V6K

PR41
80.6K_0402_1%

PC20
PR45
10K_0402_1%

PR58
1M_0402_5%
PC24
@ 0.1U_0402_16V7K
PU5B

41

BQ24703VREF
PR63
@ 47K_0402_1%

AC_CHG
PC26
0.022U_0402_16V7K

ALARM

100K_0402_5%

LM393DG_SO8
VL
PR67
33K_0402_1%
PU6

41
PR61
100_0402_5%

PQ12

PQ13

PR59
75K_0402_1%

PR64
15K_0402_1%

PC205
470P_0402_50V7K

PR44

100K_0603_1%

PR49

+3VL

PR33
0.015_2512_1%

PR32
100K_0402_5%
BQ24703VREF
PR36
100K_0402_1%

PR35
100K_0402_1%

+3VL

+3VL

VL

12.4K_0603_0.1%

B ATT

191K_0402_1%

1U_0603_6.3V6M

CHGCTRL

PC15

33,41

PR29
1K_0402_1%
ALARM

PC17
10U_1206_25VAK

PR31

PR240
2.15K_0402_1%

10K_0603_1%

PQ8
SI4835BDY-T1-E3_SO8

PC16
4.7U_1206_25V6K

CHGLIM

330K_0402_5%

PR55
130K_0402_1%

ACDRV#

PR39
3K_0402_1%

AC_CHG
47

PR42

DH_CHG

1U_0603_6.3V6M

PR376
@ 0_0402_5%
P2

PU2

PC25
100P_0402_50V8J

PR339
1K_0402_1%

SLP_S3#

PR62

PR26
0_0402_5%

PC23
4.7U_0805_10V6K

PD32
@ 1N4148_SOD80

ACDET

CHG_B+

47
PC11
10U_1206_25VAK

ACN

PQ91
@ RHU002N06_SOT323

9,33,35,36,43,44

PL2
FBM-L11-322513-151LMAT_1210

ACDRV#

+3VL

PR15
0_0402_5%

PC14
1U_0805_25V4Z

PR372
0.015_2512_1%

PR20
150K_0402_5%

P2

PC12
4.7U_1206_25V6K

PR14
200K_0402_5%
PR17

PC138

0.1U_0603_16V7K

47K

47K

PQ5
AO4407_SO8

0_0402_5%

PR16

PQ6
DTA144EUA_SC70

PC10
47P_0402_50V8J

47K_0402_5%

PQ4
AO4407_SO8

PR57
47K_0603_0.5%

AC_CHG
1.24VREF

G
S
RHU002N06_SOT323

RHU002N06_SOT323
S

S e c u r i t y C l a s s ification
Issued Date

Compal Secret Data

2 0 0 5 /03/10

D e c i p h e red Date

2 0 0 6 /03/10

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LMV431ACM5X_SOT23-5

Compal Electronics, Inc.

Charger
Size
Document Number
Custom L A - 2 8 21

Rev

Saturday, January 14, 2006

A

40

52

PU7

+3VL

PU8

D
74LVC1G02_04_SOT353

RB715F_SOT323

PC29

PR72
22K_0402_5%

PD11
RLZ6.2C_LL34

S
PU9

D
D

PR73
22K_0402_5%

BATT

SN74LVC1G14DCKR_SC70-5

BATSELB_A#
S

PQ19
RHU002N06_SOT323

ADP_PRES

18,25,33,40,42,47
2

PQ21
PMBT2222A_SOT23-3

PR74
470K_0402_5%
+3VL

+3VL

PR76
10K_0402_5%

PD10
1N4148_SOD80

PR71
1.5M_0402_5%

+3VL

PQ18
RHU002N06_SOT323

1000P_0402_50V7K

PC30

+3VL

RHU002N06_SOT323

BATT_IN
0_0402_5%

PQ16
RHU002N06_SOT323

PQ17
D

PR69

100_0402_5%
G

74LVC1G02_04_SOT353

BATSELB_A
1000P_0402_50V7K

PQ15
RHU002N06_SOT323

PR68

0.1U_0603_50V4Z

PC28

PD9

B A TT_B

ALARM

PR70
47K_0402_5%

40

B A TT_A

PC27

@ 0.1U_0402_10V6K

+3VL

CFET_A

PQ22
RHU002N06_SOT323

PD13

PR78

BATSELB_A

PQ23
G

PU11
SN74AHC1G08DCKR_SC70

PC197
220P_0402_50V7K

SN74LVC1G14DCKR_SC70-5

B540C_SMC
PQ24
AO4407_SO8

RHU002N06_SOT323
S

10K_0402_5%
D

PQ26
BATT_IN
G

PR77
4.7K_0402_5%

1N4148_SOD80

BATSELB_A#

BATSELB_A#

PR75
470K_0402_5%

PD12

PU10
33

PQ20
RHU002N06_SOT323
BATT_IN
G

PQ25
AO4407_SO8
PR79
470K_0402_5%

B A TT_A

BATT

RHU002N06_SOT323

+3VL
+3VL

PQ29
PMBT2222A_SOT23-3

PQ30

RHU002N06_SOT323

AC_CHG

PR80
470K_0402_5%

BATSELB_A#
PU13
SN74AHC1G08DCKR_SC70

PR85
470K_0402_5%

40

PR87
10K_0402_5%

PR84
10K_0402_1%

PQ28
AO4407_SO8

PR81
470K_0402_5%

PR82
220K_0402_5%

PC31

1N4148_SOD80

PQ27
AO4407_SO8

SN74LVC1G17DBVR_SOT23-5
PU12

PD14
PR83
470K_0402_5%

CHGCTRL

0.22U_0402_10V4Z

33,40

PD16

B A TT_B
PD15
PR86
4.7K_0402_5%
B540C_SMC

G
1N4148_SOD80

ADP_PRES

PR88

PQ31

RHU002N06_SOT323

+3VL

10K_0402_5%

PQ32
RHU002N06_SOT323

CFET_B
PQ33
PQ34

RHU002N06_SOT323
BATT_IN
G

D
PD17

BATT_IN

CFET_A

RB715F_SOT323

RHU002N06_SOT323

G
BATCON

CFET_B
PR237
100K_0402_5%

PU14

33

SN74LVC1G17DBVR_SOT23-5

S e c u r i t y C l a s s ification
Issued Date

Compal Secret Data

2 0 0 5 /03/10

D e c i p h e red Date

2 0 0 6 /03/10

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Battery selector
Size
Document Number
Custom L A - 2 8 21

Rev

Saturday, January 14, 2006

A

41

52

AO4912_SO8
PR100
0_0402_5%

+ 5 V ALWP
PL5
10UH_SIL104R-100PF_4.4A_30%

BST_5V

LX_5V
PC36
0.1U_0603_50V4Z

PU15
+
DH_5V_1

+3VALW_POK

LX_5V

47

DL_5V

PR187
154K_0603_1%

TPS51020DBTR_TSSOP30
PC41 0.1U_0402_16V7K

M A I NPWON

K B C _ P W R_ON

PQ40
S
RHU002N06_SOT323

PQ41
RHU002N06_SOT323

+3VLP

VL

PR369
100K_0402_5%

PC53
@ 0.33U_0603_10V7K

PC51
1U_0603_10V6K

APL5151_SOT23-5

PC52
1U_0603_10V6K

PQ101
SI2301BDS-T1-E3_SOT23-3

PQ42
SI2301BDS-T1-E3_SOT23-3

PR109
10K_0402_5%

+ 3 V ALWP

PL6
10UH_SIL104R-100PF_4.4A_30%
LX_3.3V

A D P _ PRES 1 8 , 2 5 , 3 3 , 40,41,47
+

+3VALWP

PR113
10K_0402_1%

PU16

PR365
100K_0402_5%

VL

PQ38
DH_3.3V_2

PR112
330_0402_5%
PC50
3300P_0603_50V7K

33

D
ADP_PRES
G

PR108
@ 0_0402_5%

PC48
4700P_0402_25V7K

PR106
1M_0402_5%

PC46
820P_0603_50V7K

PR104
0_0402_5%

AO4912_SO8

PR111
29.4K_0402_1%

PQ39
RHU002N06_SOT323 S

DL_3.3V
BST_3.3V
PC43
0.1U_0603_50V4Z

PR110
3.9K_0402_1%

PR107
100K_0402_5%

VL

DH_3.3V_1

PR335
0_0402_5%
PR103
@0 _ 0 4 0 2 _ 5 %
PC47
820P_0603_50V7K

+5VALWP
PC42
0.47U_0603_10V7K

PR105
@1M_0402_5%

46

PR102
100K_0402_5%
B++

PC45
2200P_0402_50V7K

PC44
4.7U_1206_25V6K

+5VALWP

PC40
4.7U_0805_10V6K

VL

PC39
220U_D3L_6.3M_R40

PC35
2.2U_1206_25V7K

PR98
12.7K_0402_1%

PR97
17.4K_0402_1%

PC199
220U_D3L_6.3M_R40

PR101
0_0402_5%

PR96
2.7K_0402_1%

PC37
4700P_0603_50V7K

PR99
10K_0402_1%

VL

B+

PC33
10U_1206_25VAK

PC34
2200P_0402_50V7K

PQ37
DH_5V_2

PL4
FBM-L11-322513-151LMAT_1210
PR91
330_0402_5%

PR90
49.9K_0402_1%

PC32
4700P_0603_50V7K

B++

PR115
100K_0402_5%

D
+3VALW_POK
G
PQ98
RHU002N06_SOT323

S
A

PC120
@ 1500P_0402_50V7K

Compal Secret Data

S e c u r i t y C l a s s ification
Issued Date

2 0 0 5 /03/10

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

3 . 3 V A LW/5VALW
Size
Document Number
Custom L A - 2 8 2 1
Date:

Rev

Saturday, January 14, 2006

Sheet
1

42

of

52

PL23
FBM-L11-322513-151LMAT_1210

MAX8743_B+
PC189
2200P_0402_50V7K

B+

PR328
0_0402_5%
1

PC186
4.7U_1206_16V4Z
PR332
20_0603_5%

PR329
5.1K_0402_1%

+ 1 . 5VSP
PC195

PR327
0_0402_5%

PC144
0.1U_0603_50V4Z

PL21
3.3UH_PCMC063T-3R3MN_6A_20%

PQ86

PR333
0_0402_5%

PR258
5.1K_0402_1%

PU28

PR331
0_0402_5%

VCC_MAX8743

1U_0805_16V7K

DH_1.5V_2

DH_1.05V_1
DH_1.5V_1
LX_1.05V

LX_1.5V

DL_1.05V

DL_1.5V

SLP_S3#

PR319
0_0402_5%

PR259
100K_0402_5%

PR262
20K_0402_1%
2VREF

PR260
100K_0402_5%

VCC_MAX8743
@ 0_0402_5%
PR265

PR343
47K_0402_5%

PR268
0_0402_5%

+5VALW

G
S
PQ95
RHU002N06_SOT323

D
3

1.5VSP/ +1.05V_VCCP/+2.5VALWP

PR342
0_0402_5%

PR266
100K_0402_1%

+5VALW

G
S
PQ93
RHU002N06_SOT323

D
G

PQ92 S
RHU002N06_SOT323

G
PC201
@ 0.001U_0402_50V7M

1 8 , 2 1 , 2 5 , 2 8 , 2 9 , 33,35,36,40,44 S L P _ S3#

PR341
47K_0402_5%

D
PR263
0_0402_5%

PR267
100K_0402_1%

PC72
1U_0603_10V6K

PC73
4.7U_0805_6.3V6K

+3VALWP

SLP_S3#

V C C P _POK 37

PQ94
RHU002N06_SOT323

PJP1

PC200
@ 0.001U_0402_50V7M

MAX8743EEI+T_QSOP28~N

( 4 0 0 m A , 4 0 m i l s ,Via NO.= 1)
PU20
+2.5VALWP
APL5508-25DC-TRL_SOT89-3

PR261
10K_0402_1%

PR371
@ 0_0402_5%

PR370
@ 0_0402_5%

PR257
100K_0402_1%

PC147
0.22U_0603_10V7K

PC145
4.7U_0805_6.3V6K

PC191
330U_D2E_2.5VM

DH_1.05V_2

PQ78
AO4702_SO8

PR330
0_0402_5%

BST_1.5V_1

AO4912_SO8

BST_1.5V_2
BST_1.05V_1
PC194
0.1U_0603_50V4Z

PC192
0.1U_0603_50V4Z

PL22
3.3UH_PCMB104E-3R3MS_11A_20%

+ 1 . 0 5 V _VCCP

BST_1.05V_2

PQ79
AO4404_SO8

PC185
4.7U_1206_25V6K

PC188
2200P_0402_50V7K

1U_0805_50V4Z
PC190
PD31
CHP202UPT_SOT323-3

PC203
220U_B2_2.5VM

+5VALW
PC57
4.7U_1206_25V6K

PR340
0_0402_5%

S L P _ S3# 1 8 , 2 1 , 2 5 , 2 8 , 2 9 , 33,35,36,40,44

PJP2
+1.5VS

+1.5VSP

+5VALWP

+5VALW

( 4 A , 1 6 0 m i l s ,Via NO.=8)

PAD-OPEN 3x3m
PJP3
PAD-OPEN 4x4m

( 4 . 5 A , 1 8 0 m i l s ,Via NO.= 9)
PAD-OPEN 4x4m
PJP4

+1.8V

+1.8VP

( 7 A , 2 8 0 m i l s ,Via NO.= 14)

+3VALWP

+3VALW

( 3 A , 1 2 0 m i l s ,Via NO.= 6)

PAD-OPEN 4x4m

PJP5
PAD-OPEN 4x4m

PJP6
+VCCP

+1.05V_VCCP

( 6 A , 2 4 0 m i l s ,Via NO.= 12)

+3VL

+3VLP

( 1 0 0 m A , 2 0 m i l s ,Via NO.= 1)

PAD-OPEN 2x2m

PJP12
PAD-OPEN 4x4m

PJP11
+2.5VALWP

+2.5VALW

( 4 0 0 m A , 4 0 m i l s ,Via NO.= 1)

PAD-OPEN 2x2m
PJP7
+0.9VP

+0.9V

S e c u r i t y C l a s s ification

( 2 A , 8 0 m i l s ,Via NO.= 4)

Issued Date

Compal Secret Data

2 0 0 5 /03/10

D e c i p h e red Date

2 0 0 6 /03/10

PAD-OPEN 3x3m
T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

2 . 5 V A L W /1.5VS/1.05VCCP
Size
Document Number
Custom L A - 2 8 21

Rev

Saturday, January 14, 2006

A

43

52

D D R _B+

PL15
F B M - L 1 1 - 3 2 2 5 1 3 - 151LMAT_1210

P C121
0 . 1 U _ 0 6 0 3 _ 5 0V4Z
B S T _ 1 . 8 V_2

+ 1 . 8VP

PL16
1 . 8 U _ S I L 1 0 4 R - 1 R 8 P F _ 9 . 5 A_ 3 0 %
L X _ 1 .8 V

+
PQ64
A O 4 7 0 2 _ SO8

1
1

P R236
0 _ 0 4 0 2 _5%

+1.8V

P R389
0 _ 0 4 0 2 _5%

P C133
2 2 P _ 0 4 0 2 _ 50V8J
2
1

+5VALWP

P R232
3 _ 0 4 0 2 _5%

P R234
0 _ 0 4 0 2 _5%
P R314
@ 0 _ 0 4 0 2_5%

T P S 5 1 1 1 6 _ H T S S O P20

P R233
2 0 K _ 0 6 0 3_1%

1
2

1
2

P C122
4 . 7 U _ 0 8 0 5 _ 1 0V6K

1
2

P C130
0 . 0 3 3 U _ 0 4 0 2 _ 16V7K

P C123
0 . 0 0 1 U _ 0 4 0 2 _ 50V7M

4
3
2
1

G
S
S
S

P C129
2 2 U _ 1 2 0 6 _ 6 .3V6M

P R388
0 _ 0 4 0 2 _5%
2

D
D
D
D

DL_1.8V

1
2

+5VALWP

4
3
2
1
D H_1.8V_2

P R324
0 _ 0 4 0 2 _5%

7,13,14 V_DDR_MCH_REF

P C124
1 0 U _ 1 2 0 6 _ 2 5 VAK

P C204
2 2 0 U _ D 2 _ 4 VM

D H_1.8V_1

5
6
7
8

+0.9VP

P R230
0 _ 0 4 0 2 _5%

P C128
1 0 U _ 0 8 0 5 _ 1 0V4Z

P C127
1 0 U _ 0 8 0 5 _ 1 0V4Z

B S T _ 1 . 8 V_1

PQ63
A O 4 4 0 4 _ SO8

5
6
7
8
D
D
D
D
P R231
0 _ 0 4 0 2 _5%

G
S
S
S

P U27

P C125
2 2 0 0 P _ 0 4 0 2 _50V7K
2
1

B+

P R242
0 _ 1 2 0 6 _5%

+1.5VS

1 4 . 3 K _ 0 6 0 3 _ 0.1%
P R238

SLP_S5# 21,36
B

SLP_S4# 21
SLP_S3# 18,21,25,28,29,33,35,36,40,43

P R323

SLP_S5# 21,36

P C137
@ 0 . 0 0 1 U _ 0 4 0 2 _ 50V7M

1 0 K _ 0 6 0 3 _ 0.1%
P R239
2

1
2

1
2

P C136
@ 0 . 0 0 1 U _ 0 4 0 2 _ 50V7M

@ 0 _ 0 4 0 2 _5%

S ecurity Classification
Issued Date

Compal Secret Data

2005/03/10

D e ciphered Date

2006/03/10

T i tle

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

A N D T R A D E S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S i ze
B
Date:

Compal Electronics, Inc.

Document Number

1.8V/0.9VS

Rev

L A-2821
S a t u r d a y , J a n u a r y 1 4 , 2006

S h e et
1

44

o f

52

+CPU_B+

_CPU1_1
BST

03_10V6K
1U_06

_0402_25V7K

P C 1 55
P L 19

0 . 3 6 U H _ M P C1040LR36_24A_20%

0.01U
P C 156

32PBF_SO8
P Q 82
IRF78

10_060

3_5%

+3VS

32PBF_SO8

L X _CPU1

I S L 6 2 0 8 CRZ-T_QFN8

IRF78

P R 2 70
0 _ 0 4 0 2_5%

+ 5VS

P R 2 69
1 0 _ 0 6 0 3_5%

P C 153
1 0 U _ 1 206_25VAK

P Q 80
S I 7 840DP-T1-E3_SO8

P C 152
1 0 U _ 1 206_25VAK

P C 150

P C 1 51
2 2 0 0 P _ 0402_50V7K

P L 24
F B M A - L 1 8 - 453215-900LMA90T_1812

P C 196
6 8 U _ 25V_M

P R 271
1 0 _ 0 4 02_1%

P C 157
0 . 2 2 U _ 0603_16V7K

1 0 K _ 0 402_1%

P R 274
5 . 1 1 K _0402_1%
P R 3 17

03_10V6K

V SUM

1 . 9 1 K _0603_1%

1U_06

V G A TE_INTEL

P R 3 26
0 _ 0 4 0 2_5%

VO

7,21

P C 1 84

+CPU_B+
+ 5 VS

P R 2 79

N T C
P H 2
4 7 0 K B _ 0 4 0 2_5%_ERTJ0EV474J

4 . 2 2 K _0603_1%

I SEN1

P U 32

P C 162
1 0 U _ 1 206_25VAK

P R 2 78
1 4 7 K _ 0402_1%

P Q 83

0.01U_0

H_PROCHOT#

BST

P C 1 63
1 U _ 0 6 03_10V6K

P C 161
1 0 U _ 1 206_25VAK

P R 280
0 _ 0 4 0 2_5%

P C 160

I S L 6 2 6 0CRZ-T_QFN40
P R 277
0 _ 0 4 0 2_5%

_CPU2_1

0 . 0 1 U _0402_16V7K

402_50V4Z

N T C

0 . 2 2 U _0603_16V7K
P L 20

0 . 0 1 5 U _0402_16V7K

P U 31
P R 281

I
I
I
I

D
D
D
D

1
2
3
4

0 _ 0 4 0 2_5%
P R 2 84
0 _ 0 4 0 2_5%
P R 2 86

15,37

P R 2 91
4 9 9 _ 0 4 02_1%

P R 292

H_PSI#

0 _ 0 4 0 2_5%

P R 2 94

P R 290
1 0 K _ 0 4 02_1%

P C 166
0 . 2 2 U _ 0603_16V7K

P R 2 93
5 . 1 1 K _ 0402_1%

P R 318
0 _ 0 4 0 2_5%
0 _ 0 4 0 2_5%

P R 2 96

PWR_GD

+ 5VS

0 _ 0 4 0 2_5%

D L _ CPU2

V C C SENSE

1 0 0 _ 0 4 02_1%

P C 167

1 0 0 0 P _ 0402_50V7K
1 0 0 0 P _0402_50V7K

P R 2 97

V S S S E NSE

P R 298
P C 1 73
1 8 0 _ 0 6 03_1%1 8 0 0 P _0402_50V7K

P C 182

1 K _ 0 4 02_1%

P R 301
10KB_0603

6 . 1 9 K _ 0603_1%

PH3
_5%_ERTJ1VR103J

VO

0402_16V7K

P C 1 80

1 0 0 0 P _ 0402_50V7K
P R 307

0.1U_

2 2 0 P _ 0402_25V8K

0603_16V7K

P R 304
P C 1 76
5 1 K _ 0 6 03_1%
0 . 0 2 2 U _0402_16V7K

4.53K

P R 303
_0402_1%

1 . 2 K _ 0402_1%

P C 1 79

P C 177
1 0 0 0 P _ 0402_50V7K

P R 2 99

0.22U_

P R 287

PGD_IN

P R 316
1 0 0 _ 0 4 02_1%

+ V C C_CORE

0 _ 0 4 0 2_5%

P R 289
0 _ 0 4 0 2_5%

0 _ 0 4 0 2_5%

0 . 3 6 U H _ M P C1040LR36_24A_20%

L X _CPU2

I SEN2

CLK_ENABLE#

18,33,36,37,47

P W M 2

P R 285
0 _ 0 4 0 2_5%

C P U_VID6

5
33,37

D H _ CPU2

P R 283

32PBF_SO8

V
V
V
V

D P R SLPVR

PGD_IN_1

_
_
_
_

H _ D PRSTP#
7,21

37

U
U
U
U

IRF78

4,20

P
P
P
P

IRF78

C
C
C
C

32PBF_SO8

5
5
5
5

P C 1 83

3 3 0 P _ 0402_50V7K

C o m p a l S e c r e t Data
2005/03/10

Issued Date

Deciphered Date

Compal Electronics, Inc.

2006/03/10

C P U _ CORE

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E P R O P R I E T A R Y
PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T B E
TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T H O R I Z E D B Y C O M P A L E L E C T R ONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S C L O S E D T O A N Y T H I R D P A R T Y WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LA-2821
S a t u rday, January 14, 2006

4 5
1

5 2

VMB_A

1
2

BATT_A

PL13

PCN2
PR185
4 7 K_0402_1%

P U 2 1A

+ 5 V ALW

F B M A - L 18-453215-900LMA90T_1812

P C 1 06
0 . 1 U _ 0 402_10V6K

+ 5 V ALW

P H 1 u n d e r CPU botten side :

C P U t h e r m a l protection at 90 +-3 degree C
R e c o v e r y at 43 +-3 degree C

E C _ SMD_A
E C _ SMC_A

G
4
8

33

PU21B

33

PR191
1 5 0 K_0402_1%

1
PR192
PR193
2 . 5 5 K_0603_1% 1 5 0 K_0402_1%

PC107
0 . 2 2 U _0603_10V7K

33

A B 1 A_ C L K

L M 3 5 8ADR_SO8

PQ56
R H U 0 0 2N06_SOT323

A B 1 A _ DATA

E C _ S MC_A1

+ 5 V ALW

E C _ S MD_A1
2

T H M _ MAIN#

L M 3 5 8 ADR_SO8

M A I NPWON 42

PR190
1 5 K_0603_1%

PR186
1 K _ 0402_5%

PR188
PR189
100_0402_5% 1 0 0 _0402_5%

PD27
@ S M 0 5_SOT23

PD26
@ S M 2 4_SOT23

CPU

T Y C O _C-1746706_6P

PC105
0 . 0 1 U _0402_50V4Z

PH1
1 0 K _ T H 1 1 -3H103FT_0603_1%

PC104
1 0 0 0 P_0402_50V7K

PR334
@ 3 3 0 K_0402_5%

PC108
1 0 0 0 P _0402_50V7K

VMB_B
PL14
F B M A - L 1 8-453215-900LMA90T_1812

PR197
S U Y I N _ 2 0163S-06G1-K

PR195
2 1 0 K_0402_1%

PC109
1 0 0 0 P_0402_50V7K

+3VL

PR194
1 K _ 0402_5%

E C _ SMD_B
E C _ SMC_B
AB/I_B
TS_B

B A T T_B

PCN3

PC110
0 . 0 1 U _0402_50V4Z

PD19
@ S M 2 4_SOT23

1 K _ 0402_5%

PR200
100_0402_5%

PD20

PR201

@ S M 0 5_SOT23
T H M _ M BAY#

33

1 0 0 _0402_5%

E C _ S MD_B1

A B 1 B _ DATA

E C _ S MC_B1

A B 1 B_ C L K

33
33

Security Cl assification
I s s u ed Date

C o m p a l S e cret Data
2005/03/10

Decipher ed Date

2006/03/10

T H IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R ADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

T itle

Compal Electronics, Inc.

BATTERY CONN

Size
D o c u m ent Number
Custom

R ev

LA-2821

D a te:

S a t u r d a y , January 14, 2006

D

Sh eet

46

of

52

+5VS
PQ105
N D S 0 610_SOT23

+5VS

MXM_CD1#

PQ107
R H U 0 0 2 N 0 6_SOT323

A D P _ PS0

P U 3 4A

G
L M 3 9 3DG_SO8

1
PR364
1 0 K_0402_5%

P U 3 4B

A D P _ PS1

PQ62
M M B T 3904_SOT23

+3VS

PR361
2 1 K_0402_1%

1 2

33

+5VS

PR358
3 . 4 8 K_0402_1%

2
1

2
1

PR224
1 0 0 K_0402_5%

1 1
1
PR363
1 0 K_0402_5%

33

L M 3 9 3DG_SO8

PR362
1 M _ 0402_5%
PR357
2 1 K _ 0402_1%

1
2

33

PR384
2 2 0 K_0402_5%

40

C H G LIM

1
2

PR368
2 2 0 K _0402_5%

1 N 4 148_SOD80

PQ97
R H U 0 02N06_SOT323

40

Security Cl assification

C o m p a l S e cret Data
2005/03/10

I s s u ed Date

Decipher ed Date

2006/03/10

T H IS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R ADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R TMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

P C 1 15
1 U _ 0 805_16V7K

1
2

P R 3 83
2 2 1 K_0603_1%

1 2
22

47K

47K
P R 3 85
1 5 0 K _0402_5%

1
2

PR359
1 0 K_0402_5%

1
1
G
4

A D P _ EN

40

PD34

A D P _ EN#

+ 3 V ALW
G
PQ106
@ R H U 0 02N06_SOT323

2
PR387
2 2 0 K_0402_5%

P
G
4
1
2

0 . 0 2 7 U _0603_16V7K

P C 1 17

1
1
2
1

PC207
1 U _ 0603_10V6K

T itle

Compal Electronics, Inc.

ADP_OCP

L M 3 93DG_SO8

@ 6 8 K _0402_5%

1
PR382

1 2

1
1 2

@ 2 9 . 4 K_0402_1%

P R 3 86

G
PQ104 S
@ R H U 0 02N06_SOT323

+5VS
PR360
1 M _ 0402_5%

7 1 . 5 K_0402_1%

P R 3 51
4 7 K _ 0402_5%

PR352
2 2 0 K_0402_5%

PU33B

18,21

2
1
2

PR218

2
2

1
2

G
S
PQ103
@ R H U 0 02N06_SOT323

PC202
0 . 1 U _0805_50V7M

4 7 0 K_0402_5%

PR225
@1 0 0 K _ 0 4 0 2 _ 5 %

PR353
4 7 K _ 0402_5%

A D P _ PRES

+3VS

33

VIN

L M 3 93DG_SO8

PR356

2
1
1 2

PR349
1 0 K _ 0402_1%
D

ACN

A D P _ ID

1 N 4 148_SOD80

+3VS

G
4

2
1
2

P R 3 48
1 0 0 K_0402_1%

PR381
4 0 . 2 K_ 0 4 0 2 _ 1 %

1 K _ 0402_5%

4 7 K_0402_5%

1
2
1
1

P R 3 67
0_0402_5%

P R 3 79
@ 4 4 2 K_0402_1%

PQ100
@ R H U 0 02N06_SOT323

A C O C P_EN#

1 8 , 2 5 ,33,40,41,42

PU33A

PR350
1 M _ 0402_5%

VIN

35

R H U 0 0 2N06_SOT323

PR355

PR354
1 0 K_0402_5%

PR347
2 2 6 K_0402_1%

PR391
2 8 7 K_0402_1%

C H 3 5 5PT_SOD323-2
+3VS

0_0402_5%

+ 3 V ALW

PR346
1 M _ 0402_5%

PR345
1 0 K_0603_1%

PD36
PD35

PR390

PR344
1 0 0 K_0402_1%

PR227
4 7 0 K_0402_5%

PC206
3 9 0 0 P _0402_50V7K

PD38

VIN

A D P _ S I GNAL

4,21
PR380

C H 3 5 5PT_SOD323-2

VIN

42

1 8 , 3 3 ,36,37,45

PWR_GD

P R 2 49
3 . 9 K _0402_5%

C
1 8 , 2 5 ,33,40,41,42
PQ102
B
M M B T 3904_SOT23
E

PQ96
N D S 0 610_SOT23
A D P _ SIGNAL

8 0 . 6 K_0402_1%

OCP#

PR373

LX_5V

1 N 4 148_SOD80

PR223
PD30
@ C H 7 5 1 H-40PT_SOD323-2

1 2 4 K_0402_1%

PR221
10_0402_5%

PD37

PQ61

A D P _ PRES

PQ108
D T A 1 4 4 EUA_SC70

PR217
6 0 4 K_0603_1%

3 . 9 K _ 0402_5%

0_0402_5%
B+

P
4

1
2

PR216
2 K _ 0402_5%

1
P R 2 20

0 . 1 U _ 0 402_16V7K

PR252

L M V 4 3 1 ACM5X_SOT23-5

PR226

L M 3 93DG_SO8
VIN

0_0402_5%

PC119

P R 2 22

PU26

PQ59
M M B T 3906_SOT23

L M 3 93DG_SO8

PR206

4 2 2 _0603_1%

7 . 8 7 K_0402_1%

PC116
0 . 2 2 U _0603_16V7K

PU25A

PD22

PR378
1 0 K _ 0402_5%

1 0 0 K_0402_5%

0_0402_5%
L M 3 5 8ADR_SO8

PU25B

8
P

PR212

G
4

PR209

0_0402_5%

G
4

PR210
0_0402_5%

1
1

PR214
1 0 0 K _ 0603_0.5%

P C 1 18
1 U _ 0 805_50V4Z

PR213
1 0 K_0402_1%

PU24B

6 . 8 1 K_0402_1%

PR211

L M 3 5 8ADR_SO8

PR207
1 3 3 K_0402_1%
PR377
1 0 K_0402_5%

P4

C H 7 5 1 H-40PT_SOD323-2

PR208

PR251
3 3 0 K_0402_5%

PU24A

C H 7 5 1 H-40PT_SOD323-2
D

+5VS

+3VS

PD21

Size
D o c u m ent Number
C u s tom

R ev

LA-2821

D a te:

S a t u r d a y , January 14, 2006

Sh eet
1

47

of

52

E A L 8 0 f r o m P r e D B - 1 S t e p to DB-1 Step LA-2821 REV:0.0 -> 0.1 Modify <94.03.26.~94.04.08. >

24. Remove the R1153 2.2Kohm pull-high resistor for lever age AF1.0 CFG9 setup. <Page 11> 94.04.01.
- R e move R1153(@2.2K_0402). (Modify CKT&BOM)
25. Add net name for USB signals layout rule create. <Page 30> 94.04.04.
- A d d net names USB20_N1_R, USB20_P1_R, USB20_N4_R, USB20_P4_R, USB20_HUB_N1_R,
U S B 2 0 _ H U B _ P 1 _ R o n J P 1 6 . 6 / 7 / 2 / 3 J P 2 2 . 4 / 3 . ( M o d i f y C K T & L a y o ut)
4 t h N e tin
26. Remove the R555,R612 8.2Kohm pull-high resistors because the signals be double pulled up.
<Page 18> 94.04.04.

1. Change +0.9V discharge circuit control signal fr om SLP_S3 to SLP_S5. <Page 36> 94.03.26.
- C h a n g e Q 2 7 . 2 ( 2 N 7 0 0 2 ) c o n n e c t i o n f r o m S L P _ S 3 t o S L P _ S 5 . ( M o d i f y C K T & L a yout)
2. Just reserve a test pad for TPM_GPIO directly. <Page 32> 94.03.28.
- D e l R 1 2 4 8 a n d c o n n e c t T P 6 2 t o J P 3 3 . 8 d i r e c t l y . ( M o d i f y C K T & Layout)
3. Change TPM1.2 +3VL Power Rail to +3VALW by Custo mer request. <Page 32> 94.03.28.
- C h a n g e + 3 V L t h a t c o n n e c t s t o R 1 2 4 2 . 1 t o + 3 V A L W . ( M o d i f y C K T & L ayout)
4. Correct U25.39/38's net name from CLK_PCIE_NC/NC# to PCIE_NC/NC# . <Page 15> 94.03.28.
- R e move R555,R612(@8.2K_0402). (Modify CKT&BOM)
- Change U25.39/38 connection from CLK_PCIE_NC/CLK_PCIE_NC# to PCIE_NC/PCIE_NC#. (Modify CKT&Layout)
27. Reserve Audio mute control signals on KBC to lev erage AF1.0 designing. <Page 33> 94.04.04.
5. Change the RC parts for POK Time del ay request. <Page 37> 94.03.29.
- R e s e r v e R 1 4 0 , R 1 4 1 ( @ 0 _ 0 4 0 2 ) o n U 4 7 . 5 7 / 5 6 f o r E A P D / A _ S D . ( M o d i f y C K T & L a y o u t)
- Change R117 from 100K_0402_5% to 150K_0402_1%. (Modify CKT&BOM)
28. Correct net name for USB signals layout rule create. <Page 29,35> 94.04.04.
- C h a n g e C 8 7 f r o m 0 . 1 U _ 0 4 0 2 t o 0 . 4 7 U _ 0 6 0 3 _ X 7 R . ( M o d i f y C K T , B O M & L a y o u t)
- C orrect net names to USB20_N2_R, USB20_P2_R, USB20_N3_R, USB20_P3_R, USB20_N6_R,
U S B 2 0 _ P 6 _ R , U S B 2 0 _ N 7 _ R , U S B 2 0 _ P 7 _ R , o n J P 2 7 . 1 / 2 / 4 / 5 J P 3 0 . 2 / 4 / 6 / 8 . ( M o d i f y C K T & L a yout)
6. Update the PCI7611MLS/PCI7612 related schematic by Vendor recommend. <Page 23,24> 94.03.29.
- C h a n g e R 9 3 , R 9 7 f r o m 7 6 1 2 @ 0 _ 0 4 0 2 t o 0 _ 0 4 0 2 ; R 1 0 3 f r o m 7 6 1 1 @ 0 _ 0 4 0 2 t o @ 0 _ 0 4 0 2 . ( M o d i f y C K T & B OM)
29. Add (NC@0_0402) to connect CP_USB# and NC_CPPE# f or New Card function usage. <Page 24>
94.04.04.
- A d d R 1 3 0 8 ( 0 _ 0 4 0 2 ) b e t w e e n U 4 2 . K 3 a n d U 4 2 . K 5 ; c h a n g e R 1 0 6 f r o m 0 _ 0 4 0 2 t o @ 0 _ 0 4 0 2 . ( M o d i f y C K T , B O M &Layout)
-Change R1299 from 43K_0402 to @43K_0402. (Modify CKT&BOM)
- A d d R1316(NC@0_0402) to connect CP_USB# and NC_CPPE#. (Modify CKT,BOM&Layout)
7. Reserve a 68UF Cap. by LAN Chip Vendor request. <Page 25> 94.03.29.
- Change R1272,R1273 from @10K_0402 to @100K_0402. (Modify CKT&BOM)
5 t h N e tin
- R e serve C976(@68U_B2_4VM) close to U6.M14. (Modify CKT,BOM&Layout)
30. Del JP39.157's ADP_PRES connection to leverage AF1.0 an d standard MXM pin definition. <Page 18>
8. Reserve two resistors(@0_0402) to isolate VGATE and VG ATE_INTEL. <Page 37> 94.03.29.
94.04.04.
- R e s e r v e R 1 3 0 6 ( @ 0 _ 0 4 0 2 ) b e t w e e n P U 3 1 . 4 0 a n d U 4 5 . 2 . ( M o d i f y C K T , B O M & L a y o ut)
- D e l J P 3 9 . 1 5 7 ' s A D P _ P R E S c o n n e c t i o n . ( M o d i f y C K T & L a y o u t)
- R e s e r v e R 1 3 0 7 ( @ 0 _ 0 4 0 2 ) b e t w e e n U 4 8 . 4 a n d P R 3 2 6 . 2 . ( M o d i f y C K T , B O M & L a y o ut)
31. Reserve the circuit to control the mute to block the speaker pop on power up by customer recommend.
9. Change Calistoga LVDS function power source to GND for di sabling by customer recommend. <Page 10> 94.03.29.
<Page 29> 94.04.04.
- C h a n g e U 1 5 . B 3 0 / C 3 0 / A 3 0 c o n n e c t i o n f r o m + 2 . 5 V S t o G N D . ( M o d i f y C K T & L a yout)
- R e serve D59(@RB751V), R613(@1M_0402), R431(@10K_0402), C93(@2.2U_0805), R439(@10K_0402),
- C h a n g e U 1 5 . A 2 8 / B 2 8 / C 2 8 c o n n e c t i o n f r o m + 1 . 5 V S t o G N D . ( M o d i f y C K T & L a yout)
R 4 3 8 ( @ 1 0 _ 0 4 0 2 ) a n d t h e r e l a t e d c i r c u i t o n U 3 9 . 1 9 . ( M o d i f y C K T , B O M & Layout)
10. Remove DPRSLPVR Pull-down resistor by customer recommend. <Page 21> 94.03.29.
- C hange R1015 from 100K_0402_5% to @100K_0402_5%. (Modify CKT&BOM)
11. Stuff SPI related function Pull-High resistors by customer/Intel recommend. <Page 21,32> 94.03.29.
- C h ange R1284~R1286 from @10K_0402_5% to 10K_0402_5%. (Modify CKT&BOM)
12. Reserve 0 ohm resistor for PM_EXTTS#1 and DPRSLPVR connection by Customer/Intel recommend. <Page 7,21>
94.03.29.
- R eserve R1309(@0_0402_5%) between PM_EXTTS#1 and DPRSLPVR connection. (Modify CKT&Layout)
13. Add +1.8V discharge circ uit. <Page 36> 94.03.30.
- A d d R 1 3 1 0 ( 4 7 0 _ 0 4 0 2 _ 5 % ) a n d Q 9 0 ( 2 N 7 0 0 2 _ S O T 2 3 ) f o r + 1 . 8 V d i s c h a r g e s c h e m a t i c r e l a t e d . ( M o d i f y C K T , B O M & L a y out)
14. Change ICH7 HD function power source to +3VS for wake on ring function from Azalia modem disabling by
customer recommend. <Pag e 22> 94.03.30.
- C h a n g e U 2 6 . R 7 c o n n e c t i o n f r o m + 3 V A L W t o + 3 V S . ( M o d i f y C K T & L a y out)
15. Change TPM1.2 +3VL Power Rail to +3VALW by Custo mer request. <Page 32> 94.03.30.
- C h a n g e + 3 V L t h a t c o n n e c t s t o C 1 9 3 . 1 t o + 3 V A L W . ( M o d i f y C K T & L ayout)
16. Update ICH7M HD Audio, Codec Chip and MDC related Schematic. <Page 20,34,36> 94.03.30.
- A d d R 1 3 1 3 , R 1 3 1 4 , R 1 3 1 5 ( 3 3 _ 0 4 0 2 ) f o r I C H 7 / M D C / C o d e c r e l a t e d u p d a t e . ( M o d i f y C K T , B O M & L a y out)
- C r e a t e n e t n ame AC97_RST#_MDC, AC97_RST#_CODEC, AC97_SYNC_MDC, AC97_SYNC_CODEC,
A C 9 7 _ S D O U T _ M D C , A C 9 7 _ SDOUT_CODEC, AC97_BITCLK_MDC, AC97_BITCLK_CODEC, AC97_SDIN0_CODEC,
A C 9 7 _ S D I N 1 _ M D C f o r I C H 7 / M D C / C o d e c r e l a t e d u p d a t e . ( M o d i f y C K T & L a y o u t)
17. Reserve 0ohm option resistors for +0.9V discharge circuit co ntrol signal SLP_S3 and SLP_S5 selecting . <Page 36>
94.03.30.
- R e s e r v e R 1 3 1 1 ( @ 0 _ 0 4 0 2 ) t o c o n n e c t S L P _ S 5 t o Q 2 7 . 2 . ( M o d i f y C K T & L a y out)
G e r b e r O u t 4 / 14
- A d d R 1 3 1 2 ( 0 _ 0 4 0 2 ) t o c o n n e c t S L P _ S 3 t o Q 2 7 . 2 . ( M o d i f y C K T , B O M & L a yout)
18. Populate the 68UF Cap. and reserve 10UF Cap. by LAN Chip Vendor/Customer request. <Page 25> 94.03.30.
- C h a nge C976 from @68U_B2_4VM to 68U_B2_4VM, remove C243(@10U_1206_6.3V). (Modify CKT&BOM)
19. Swapping DDR2 SO-DIMM Data Group pin definition for Layout routing smoothly. <Page 13,14> 94.03.31.
- S w a p p i n g J P 3 4 a n d J P 1 0 D a t a G r o u p p i n d e f i n i t i o n . ( M o d i f y CKT&Layout)
3 t h N e tin
20. Correct Calistoga chip power pin connection base on CRB Rev:1.301 recommend. <Page 11> 94.04.01.
- D i s c o n n e c t U 1 5 . A V 1 a n d U 1 5 . A J 1 t o + 1 . 8 V a n d m o d i f y t h e r e l a t e d s c h e m a t i c . ( M o d i f y C KT&Layout)
- C h a n g e U15.AT41/AM41 net name from MCH_AT41/MCH_AM41 to VCCSM_LF4/VCCSM_LF5. (Modify CKT&Layout)
21. Change C899~C930 from 10U_1206_X5R to 10U_00805_X5R to meet Intel N apa ESL request. <Page 6> 94.04.01.
- C hange C899~C930 from 10U_1206_X5R to 10U_00805_X5R. (Modify CKT,BOM&Layout)
22. Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R to meet Int el request, avoid thermal risk. <Page 6>
94.04.01.
S e c u r i t y C l a s s ification
Compal Secret Data
Compal Electronics, Inc.
- Change C940~C945 from 0.1U_0402_Y5V to 0.1U_0402_X5R. (Modify CKT&BOM)
2 0 0 5 /03/10
2 0 0 6 /03/10
Title
Issued Date
D e c i p h e red Date
23. Update ICS954306 PCB Footprint for L ayout routing. <Page 15> 94.04.01.
H / W 2 E E Dept. PIR SHEET(1)
T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
Rev
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
- Change U25 PCB Footprint from ICS954306_TSSOP64 to ICS954306BGLFT_TSSOP64.
1.0
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
L A - 2 8 2 1P
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
( M odify CKT,BOM&Layout)
Date:
Saturday, January 14, 2006
Sheet
48
of
52
1

E A L 8 0 f r o m D B - 1 S t e p t o DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

6. Change SRC clock assignments as customer request . <Page 15> 94.05.13.

- Change U25.20 connection from "MCH_3GPLL" to "PCIE_LOM". (Modify CKT&Layout)
- Change U25.21 connection from "MCH_3GPLL#" to "PCIE_LOM#". (Modify CKT&Layout)
-Change U25.22 connection from "PCIE_LOM" to "PCIE_NC". (Modify CKT&Layout)
-Change U25.23 connection from "PCIE_LOM#" to "PCIE_NC#". (Modify CKT&Layout)
- C hange U25.26 connection from "PCIE_MCARD" to "PCIE_DOCK". (Modify CKT&Layout)
- C hange U25.27 connection from "PCIE_MCARD#" to "PCIE_DOCK#". (Modify CKT&Layout)
- C hange U25.37 connection from "PCIE_DOCK" to "MCH_3GPLL". (Modify CKT&Layout)
- C hange U25.36 connection from "PCIE_DOCK#" to "MCH_3GPLL#". (Modify CKT&Layout)
- Change U25.39 connection from "PCIE_NC" to "PCIE_MCARD". (Modify CKT&Layout)
- Change U25.38 connection from "PCIE_NC#" to "PCIE_MCARD#". (Modify CKT&Layout)
7. Change CLKREQ assignments as customer request . <Page 07,15,24,27> 94.05.13.
- C hange R1344.2 connection from "CLKREQB#" to "CLKREQC#". (Modify CKT&Layout)
- Change R1279.1/R1280.1/C961.1 connection from "CLKREQD#" to "CLKREQA#". (Modify CKT&Layout)
- C h a n g e R1336 connection from "CLKREQB#" to "CLKREQD#"; from "CLKREQB#_MC" to "CLKREQD#_MC".
( Modify CKT&Layout)
- A d d R 1 1 2 0 ( N O X D P @ 1 0 K _ 0 4 0 2 ) f r o m n e t " C L K R E Q C # " t o + 3 V S p u l l - h i g h . ( M o d i f y C K T , B O M & L a y o u t)
- C h a n ge R1142 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)
- A d d R 1 1 4 7 ( N O X D P @ 1 0 K _ 0 4 0 2 ) f r o m n e t " C L K R E Q D # " t o + 3 V S p u l l - h i g h . ( M o d i f y C K T , B O M & L a y o u t)
- C h a n ge R1254 from NOXDP@10K_0402 to NOXDP@0_0402 . (Modify CKT&BOM)
- C h a n g e R 1 1 0 6 ( 1 0 K _ 0 4 0 2 ) c o n n e c t i o n f r o m + 3 V S p u l l - h i g h t o b e t w e e n C L K R E Q B # a n d CPPE# .
( Modify CKT&Layout)
8. Reserve test Mini-Card that supports USB interface as customer request . <Page 27,32> 94.05.13.
- A d d R 1 3 6 5 ( @ 0 _ 0 4 0 2 ) b e t w e e n J P 3 8 . 2 a n d J P 4 4 . 3 6 . ( M o d i f y C K T & L ayout)
- A d d R 1 3 6 6 ( @ 0 _ 0 4 0 2 ) b e t w e e n J P 3 8 . 3 a n d t o J P 4 4 . 3 8 . ( M o d i f y C K T & Layout)
9. Del R1344 & R1336 and short directly because of dou ble reserved . <Page 07,27> 94.05.16.
- D e l R 1 3 4 4 ( @ 0 _ 0 4 0 2 _ 5 % ) a n d s h o r t d i r e c t l y . ( M o d i f y C K T & L a yout)
- D e l R 1 3 3 6 ( 0 _ 0 4 0 2 _ 5 % ) a n d s h o r t d i r e c t l y . ( M o d i f y C K T , B O M & L a yout)
10. Update LAN Controller schematic related caused by ch ipset changed from BCM5751M to BCM5753M .
<Page 25,26> 94.05.16.

1. Change HDD I/F from PATA to S ATA. <Page 20> 94.05.10.

- C h a n g e U 2 6 . A F 1 8 f r o m N C t o I D E _ L E D # . ( M o d i f y C K T & L a y o u t)
- C hange U26.AF3 from GND to SATA_RXN0_C. (Modify CKT&Layout)
- Change U26.AE3 from GND to SATA_RXP0_C. (Modify CKT&Layout)
- Change U26.AG2 from NC to SATA_TXN0_C. (Modify CKT&Layout)
- Change U26.AH2 from NC to SATA_TXP0_C. (Modify CKT&Layout)
- A d d R 1 2 5 6 ( 2 4 . 9 _ 0 4 0 2 _ 1 % ) b e t w e e n U 2 6 . A H 1 0 / A G 1 0 a n d G N D . ( M o d i f y C K T , B O M & L a y o u t)
- D e l R1326,R1327(NOSATA@0_0402). (Modify CKT,BOM&Layout)
- A d d J P 4 5 , C 9 5 5 ~ C 9 5 8 ( 3 9 0 0 P _ 0 4 0 2 ) a n d r e l a t e d s c h e m a t i c f o r S A T A c o n n e c t o r . ( M o d i f y C K T , B O M & L a yout)
2. Remove R1294(1K_0402) Pull-High to +3VS to avoid do uble Pull-High risk. <Page 20> 94.05.10.
- R e m ove R1294(@1K_0402). (Modify CKT&BOM)
3. Add the accelerometer device LIS3LV02DQ and modify the rela ted schematic . <Page 02,21,27,33> 94.05.11.
- A d d U 64(LIS3LV02DQ_QFN28),R1355(0_0805_5%),R1356(0_0603_5%),R1357~R1361(0_0402_5%),
R 1 3 62(10K_0402_5%),C994(0.01U_0402_16V7K),C995(0.1U_0402_16V4Z) and C996(4.7U_0805_10V4Z)
a t t h e c e n t e r o f t h e s y s t e m . ( M o d i f y C K T , B O M & Layout)
-Add R1364(0_0402_5%) between "ACCEL_INT#" and U26.E20(SB_GPIO9); Reserve R1363(@0_0402_5%) between
" A D P_PWRID" and U26.E20(SB_GPIO9) . (Modify CKT,BOM&Layout)
- R e serve R1354(@0_0402_5%) between "ACCEL_INT#" and U47.34(KBC_GPIO23) . (Modify CKT,BOM&Layout)
4. Change USB port assignments as customer request . <Page 02,21,24,30,32> 94.05.11.
- C h a nge R1317(NC@0_0402_5%) connection Net from "USB20_P0_HUB" to "USB20_P1_HUB" and from "USB20_P0" to
" USB20_P1" . (Modify CKT&Layout)
- C h a n g e R1318(NC@0_0402_5%) connection Net from "USB20_N0_HUB" to "USB20_N1_HUB" and from "USB20_N0" to
" USB20_N1" . (Modify CKT&Layout)
- C h ange R562(0_0402_5%) connection Net from "USB20_HUB_P1_R" to "USB20_P0_R" and from "USB20_HUB_P1" to
" USB20_P0" . (Modify CKT&Layout)
- C h a n ge R586(0_0402_5%) connection Net from "USB20_HUB_N1_R" to "USB20_N0_R" and from "USB20_HUB_N1" to
" USB20_N0" . (Modify CKT&Layout)
- C hange R983(NONC@0_0402_5%) connection Net from "USB20_P0" to "USB20_P1" . (Modify CKT&Layout)
- C h ange R982(NONC@0_0402_5%) connection Net from "USB20_N0" to "USB20_N1" . (Modify CKT&Layout)
- U p d a t e t h e r e l a t e d s c h e m a t i c . ( M o d i f y C K T & L a yout)
- C h ange R1335(0_0402_5%) connection Net from "USB20_HUB_P2_R" to "USB20_HUB_P1_R" and from
- C h a n g e R 2 7 5 , R 2 8 9 f r o m 4 7 K _ 0 4 0 2 t o 1 K _ 0 4 0 2 . ( M o d i f y C K T , B O M & L a y out)
" U S B 20_HUB_P2" to "USB20_HUB_P1" . (Modify CKT&Layout)
- C h a n g e R 2 7 6 f r o m 4 . 7 K _ 0 4 0 2 t o 1 K _ 0 4 0 2 . ( M o d i f y C K T , B O M & L a yout)
- C h a nge R1334(0_0402_5%) connection Net from "USB20_HUB_N2_R" to "USB20_HUB_N1_R" and from
-Add R1370,R1371(0_0402) and reserve R1372,R1373(@2.2K_0402),Q92,Q93(@2N7002) for SMBus
" U S B 2 0_HUB_N2" to "USB20_HUB_N1" . (Modify CKT&Layout)
c o n n e c t i o n . ( M o d i f y C K T , B O M & L a y o u t)
- C h a nge R1276(NC@0_0402_5%) connection Net from "USB20_P5_R" to "USB20_HUB_P2_R" and from
- A d d R 1 3 6 7 ( 1 K _ 0 4 0 2 ) f r o m U 6 . H 1 2 t o + 3 V S . ( M o d i f y C K T , B O M & L a y out)
"U SB20_P5" to "USB20_HUB_P2" . (Modify CKT&Layout)
11. Remove U37,D32,R504, and C577. Remove CLKREQA# connect ion from NIC to CK clock by customer
- C h a n ge R1274(NC@0_0402_5%) connection Net from "USB20_N5_R" to "USB20_HUB_N2_R" and from
recommend . <Page 2 5> 94.05.16.
" U S B20_N5" to "USB20_HUB_N2" . (Modify CKT&Layout)
-Remove U37,D32,R504, and C577 . (Modify CKT,BOM&Layout)
-Change R607(0_0402_5%),D51.3 connection Net from "USB20_P1_R" to "USB20_P5_R" and fro m
12. Update Accelerometer related schematic by Vendor S TMicro recommend . <Page 27> 94.05.16.
"USB20_P1" to "USB20_P5" . (Modify CKT&Layout)
- R e m o v e C 9 9 4 ( @ 0 . 0 1 U _ 0 4 0 2 ) , C h a n g e C 9 9 6 f r o m 4 . 7 U _ 0 8 0 5 t o 1 0 U _ 0 8 0 5 . ( M o d i f y C K T , B O M & L a y o u t)
-Change R606(0_0402_5%),D51.2 connection Net from "USB20_N1_R" to "USB20_N5_R" and from
13. Modify ICH7 Power_OK connection to be able to be enable same as NB . <Page 21> 94.05.16.
"U SB20_N1" to "USB20_N5" . (Modify CKT&Layout)
- A d d R 1 3 6 8 ( 0 _ 0 4 0 2 ) a n d r e s e r v e R 1 3 6 9 ( @ 0 _ 0 4 0 2 ) f o r U 2 6 . A D 2 2 c o n n e c t i o n . ( M o d i f y C K T , B O M & L a y out)
- C hange U53(NC@USB2502) pin15 connection from Net "USB_OC#0" to "USB_OC#1" . (Modify CKT&Layout)
14. Swap RP11,RP13 pin connection for DDR2 shift trace routing issue improving . <Page 14> 94.05.16.
-Change U41(TPS2041B) pin5 connection from Net "USB_OC#1" to "USB_OC#5" . (Modify CKT&Layout)
- C hange RP11.2 connection from DDR_B_MA11 to DDR_CKE3_DIMMB . (Modify CKT&Layout)
5. Change PCIE port assignments as customer request . <Page 02,21,24,25,27,35> 94.05.12.
- C hange RP11.1 connection from DDR_CKE3_DIMMB to DDR_B_MA7 . (Modify CKT&Layout)
- C h a n g e U 2 6 . K 2 6 / K 2 5 / J 2 8 / J 2 7 t o N C . ( M o d i f y C K T & L a y out)
- Change RP13.2 connection from DDR_B_MA6 to DDR_B_MA11 . (Modify CKT&Layout)
- C h a n g e C 7 1 2 c o n n e c t i o n f r o m P C I E _ C _ T X N 3 t o P C I E _ C _ T X N 4 ; f r o m P C I E _ T X N 3 t o P C I E _ T X N 4 . ( M o d i f y C K T & L a y o ut)
- Change RP13.1 connection from DDR_B_MA7 to DDR_B_MA6 . (Modify CKT&Layout)
- C h a n g e C 7 1 3 c o n n e c t i o n f r o m P C I E _ C _ T X P 3 t o P C I E _ C _ T X P 4 ; f r o m P C I E _ T X P 3 t o P C I E _ T X P 4 . ( M o d i f y C K T & L a yout)
1 s t N e t in
- C h a n g e C 9 5 2 c o n n e c t i o n f r o m P C I E _ C _ T X N 4 t o P C I E _ C _ T X N 5 ; f r o m P C I E _ T X N 4 t o P C I E _ T X N 5 . ( M o d i f y C K T & L a y o ut)
15. Update the SATA supported r elated . <Page 20> 94.05.17.
- C h a n g e C 9 5 3 c o n n e c t i o n f r o m P C I E _ C _ T X P 4 t o P C I E _ C _ T X P 5 ; f r o m P C I E _ T X P 4 t o P C I E _ T X P 5 . ( M o d i f y C K T & L a yout)
- D e l e t e J P 2 3 , R 4 5 8 , R 1 3 2 4 , R 1 3 2 5 , R 3 0 0 . ( M o d i f y C K T , B O M & L a y o u t)
- C h a n g e C 9 5 9 c o n n e c t i o n f r o m P C I E _ C _ R X N 3 t o P C I E _ C _ R X N 4 ; f r o m P C I E _ R X N 3 t o P C I E _ R X N 4 . ( M o d i f y C K T & L a y o ut)
- A d d C 9 9 7 ( 1 0 U _ 0 8 0 5 ) , C 9 9 8 ~ C 1 0 0 0 ( 0 . 1 U _ 0 4 0 2 ) c l o s e t o J P 4 5 + 3 V S p i n s . ( M o d i f y C K T , B O M & L a y o ut)
- C h a n g e C 9 6 0 c o n n e c t i o n f r o m P C I E _ C _ R X P 3 t o P C I E _ C _ R X P 4 ; f r o m P C I E _ R X P 3 t o P C I E _ R X P 4 . ( M o d i f y C K T & L a yout)
16. Dual design SPI ROM for SOP8-150mil/200mil p ackage . <Page 32> 94.05.17.
- C h a n g e J P 9 . A 2 4 c o n n e c t i o n f r o m P C I E _ T X N 3 t o P C I E _ T X N 4 . ( M o d i f y C K T & L a y out)
- Add U65(SPI@SST25LF080A-200mil) . (Modify CKT,BOM&Layout)
- C h a n g e J P 9 . A 2 5 c o n n e c t i o n f r o m P C I E _ T X P 3 t o P C I E _ T X P 4 . ( M o d i f y C K T & L a yout)
17. TPM1.2 on board designing reserve re lated . <Page 32> 94.05.17.
- C h a n g e R 1 3 4 7 c o n n e c t i o n f r o m P C I E _ C _ R X N 4 t o P C I E _ C _ R X N 5 ; f r o m P C I E _ R X N 4 t o P C I E _ R X N 5 . ( M o d i f y C K T & L a y o ut)
- A d d U66(TPM1.2@SLB9635TT),C1001~C1004(0.1U_0402),C1005,C1006(18P_0402),Y8(32.768KHz),
- C h a n g e R 1 3 4 6 c o n n e c t i o n f r o m P C I E _ C _ R X P 4 t o P C I E _ C _ R X P 5 ; f r o m P C I E _ R X P 4 t o P C I E _ R X P 5 . ( M o d i f y C K T & L a yout)
R 1 3 7 5 ~ R 1 3 8 1 a n d r e l a t e d s c h e m a t i c u p d a t e . ( M o d i f y C K T , B O M & L a y out)
- C h a n g e J P 3 0 . 1 5 1 c o n n e c t i o n f r o m P C I E _ T X N 4 t o P C I E _ T X N 5 . ( M o d i f y C K T & L a y out)
2 n d N e t in
- C h a n g e J P 3 0 . 1 4 9 c o n n e c t i o n f r o m P C I E _ T X P 4 t o P C I E _ T X P 5 . ( M o d i f y C K T & L a yout)
Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

H / W 2 E E Dept. PIR SHEET(2)

Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
5

49

of

52

E A L 8 0 f r o m D B - 1 S t e p t o DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.27. >

31. Update Clock Gen. schematic related by cust omer recommend . <Page 15> 94.05.23.
- R e serve R1393(@0_0402_5%) from U25.46(CLKIREF) to +CK_VDD_DP . (Modify CKT&Layout)
-Reserve C1011(@0.1U_0402) from U25.46(CLKIREF) to GND . (Modify CKT&Layout)
- R e s e r v e R 1 3 9 4 ( @ 1 0 K _ 0 4 0 2 ) f r o m U 2 5 . 2 ( P C I _ E C ) t o + 3 V S . ( M o d i f y C K T & L a y o ut)
- R e m ove R1353,R1333(@0_0402_5%) . (Modify CKT&BOM)
32. Update AC97 Codec to keep AD1981HD only schematic rel ated by customer recommend and DFx issue
improved . <Page 15, 28> 94.05.23.
- D e l C 391,R403,R406,R388,R158,R159,C410,C408,C401,C398,R415,R364,C397,R1085(CLK_14M_CODEC)
, R 4 1 8 a n d s h o r t U 1 4 . 4 2 t o G N D A . ( M o d i f y C K T , B O M & L a y out)
- A d d T 8 8 ~ T 1 0 1 t e s t p o i n t o n t h e b o t t o m s i d e . ( M o d i f y C KT&Layout)
33. Update ICH7 SPI I/F related schematic by custo mer recommend . <Page 21> 94.05.24.
- C h a n g e R 1 2 8 4 . 1 , R 1 2 8 5 . 1 a n d R 1 2 8 6 . 1 c o n n e c t i o n f r o m + 3 V S t o + 3 V A L W . ( M o d i f y C K T & Layout)
34. Update TI PCI7611MLS/PCI7612 related schematic by custom er recommend . <Page 23> 94.05.24.
- C h a n g e R 5 9 4 . 2 a n d R 6 0 2 . 2 c o n n e c t i o n f r o m + V C C _ S D t o + V C C _ S M _ X D . ( M o d i f y C K T & L a y o u t)
35. Update ICH7 SATA I/F related schematic by cust omer recommend . <Page 20> 94.05.24.
- D e l J P 4 5 p i n 8 , 9 , 1 0 + 3 V S c o n n e c t i o n . ( M o d i f y C K T & Layout)
-Del C997~C1000 . (Modify CKT,BOM&Layout)
36. Update ICH7 PATA I/F related schematic for SATA HDD support . <Page 20> 94.05.24.
- Add R556(100K_0402) . (Modify CKT&BOM)
37. Change some Capacitors for Lead Free desig ning . <Page 6,18,22,30> 94.05.25.
- R e m ove C939(@220U_C6_6.3V) and add C983(330U_D2E_2.5V) . (Modify CKT&BOM)
- R e m o ve C633(@47U_25V_M) and add C1013~C1017(10U_1206_25V6M) . (Modify CKT,BOM&Layout)
- R e m ove C671(@100U_6.3V_M) and add C1012(150U_D_6.3VM) . (Modify CKT,BOM&Layout)
- R e m o ve C670(@220U_C6_6.3V) and add C979(330U_DD2E_2.5V) . (Modify CKT&BOM)
- R e m ove C1,C527(@100U_6.3V) and add CC568,C567(150U_D_6.3V) . (Modify CKT&BOM)
38. Update the Accelerometer related and install the related BOM for Accelerometer enable . <Page 19,21,27,33>
- Change the net name from ACCEL_INT# to ACCEL_INT, ACCEL#_SB to ACCEL_SB, ACCEL_INT#_KBC
to ACCEL_INT_KBC . (Modify CKT&Layout)
- N o t e R 9 4 m u s t b e r e m o v e d w h e n R 1 3 5 4 s t u f f a n d R 8 7 r e m o v e . ( M o d i f y C K T &BOM)
- R e s e r v e D 6 1 , C 1 0 1 8 , R 1 3 9 5 , Q 9 5 b e t w e e n A C C E L _ I N T a n d Q 7 8 . 1 . ( M o d i f y C K T & L a y o ut)
- R e move R1358,R1360 . (Modify CKT&BOM)
9 r d N e t i n / B O M T r a n s f er
39. Update Docking related schematic for Customer Smart Adaptor new function request . <Page 21,35>
- C h a n g e J P 3 0 . 1 1 8 a n d R 1 3 8 7 . 1 n e t n a m e t o D O C K _ I D . ( M o d i f y C K T & L a yout)
- A d d JP30.117(DOCK_ADP_SIGNAL) to ADP_SIGNAL by R1401(1K_0402_1%) . (Modify CKT,BOM&Layout)
40. Update AD1981HD related schematic for Ve ndor ADI review result . <Page 28>
- C h a n g e U 1 8 . 2 c o n n e c t i o n f r o m G N D t o A G N D , m o v e R 2 5 8 b e t w e e n C 5 5 1 . 1 a n d U 1 8 . 2 . ( M o d i f y C K T & Layout)
- C h a n g e C 4 0 9 , C 4 2 7 , C 4 3 1 f r o m 0 . 1 U _ 0 4 0 2 t o 0 . 1 U _ 0 8 0 5 . ( M o d i f y C K T , B O M & L a y out)
- A d d R 1 4 0 0 ( 0 _ 1 2 0 6 ) b e t w e e n G N D a n d A G N D c l o s e t o C o d e c a r e a . ( M o d i f y C K T , B O M & L a y out)
- D i s c o n n e c t U 1 4 . 1 4 a n d U 1 4 . 1 5 , d i s c o n n e c t U 1 4 . 4 0 a n d U 1 4 . 3 3 t o A G N D a n d a d d T 1 0 2 , T 1 0 3 , T 1 0 4 o n p i n 14,40,33 .
( Modify CKT&Layout)
- Add R1399(0_0805) replace L36(CHB2012U121(0805)) . (Modify CKT&BOM)
-Add C1019(10P_0402) to GND . (Modify CKT,BOM&Layout)
41. Update Accelerometer related schematic f or Customer review result . <Page 27>
- Remove R1355(@0_0805), add D62(ACCEL@CH751H) between U64.3/19 and +3VS . (Modify CKT,BOM&Layout)
- D e l R 1 3 5 8 a n d R 1 3 6 0 p u l l - d o w n r e s i s t o r s . ( M o d i f y C K T , B O M & Layout)
- A d d R 1 3 9 8 ( 0 _ 0 4 0 2 ) t o G N D , d e l U 6 4 . 2 9 t o G N D c o n n e c t i o n . ( M o d i f y C K T , B O M & L ayout)
42. Change the Audio Amp chip from TI TPA6017A2_TSSP20 to MAXI M MAX9710_QFN20 and update related
schematic for Customer Spec modified request . <Page 29>

18. Update TPM1.2 on board designing schematic. <Page 32,36> 94.05.18.

- C h a n g e p i n 5 ( V S B ) t o + 3 V A L W a n d m o v e C 1 0 0 4 t o c o n n e c t t o p i n 5 . ( M o d i f y C K T&Layout)
- D e l e t e S M B u s c o n n e c t i o n w i t h R 1 3 8 0 , R 1 3 8 1 o n U 6 6 . 2 & U 6 6 . 6 ; C o n n e c t U 6 6 . 6 t o J P 3 3 . 8 , U66.2 to T87 .
( M odify CKT,BOM&Layout)
- D e l e t e + 3 V p o w e r f r o m J P 3 3 . 4 . ( M o d i f y C K T & Layout)
- D e l e t e + 3 V p o w e r r e s e r v e d s c h e m a t i c a n d p a r t s i n c l u d e Q 9 1 , C 9 7 7 , C 9 7 8 . ( M o d i f y C K T , B O M &Layout)
19. Add DC/DC schematic about +2.5VALW to +2.5VS for power sequence fail issue fixed. <Page 36> 94.05.18.
- Add U67(SI4800DY_SO8),C1007,C1008,C1009 . (Modify CKT,BOM&Layout)
20. Delete MDC 1.0 Connector reserved related to save layout space . <Page 34> 94.05.18.
-Del JP25(MDC1.0 Conn),C13(0.1U_0402) . (Modify CKT,BOM&Layout)
21. Change the power source designing from +3VALW to +3VS f or DB-2 LS-2712 issue fixed . <Page 34> 94.05.18.
- C h a n g e J P 1 8 . 1 a n d J P 1 8 . 3 c o n n e c t i o n f r o m + 3 V A L W t o + 3 V S . ( M o d i f y C K T & Layout)
3 r d N e t in
22. Change the ICH7 RTC Cap. Value for SVTP measure f ail issue fixed . <Page 20> 94.05.19.
- C h a n g e C 5 1 6 , C 5 2 8 f r o m 1 8 P _ 0 4 0 2 t o 1 0 P _ 0 4 0 2 . ( M o d i f y C K T & B OM)
23. Update LAN chip schematic related by cust omer recommend . <Page 25> 94.05.19.
- C h a n g e R 2 7 5 , R 2 8 9 f r o m 1 K _ 0 4 0 2 t o @ 1 K _ 0 4 0 2 . ( M o d i f y C K T & B O M)
- D e l D 3 2 , R 5 0 4 , C 5 7 7 , U 3 7 . ( M o d i f y C K T , B O M & L a y o u t)
-Add R1380(0_0402) and reserve R1381(@0_0402) . (Modify CKT,BOM&Layout)
- D e l C 4 0 , C 4 5 , C 5 3 , C 6 2 , C 6 4 f o r + 3 V S p o w e r r a i l c a n c e l . ( M o d i f y C K T , B O M &Layout)
24. Update KBC related designing by custo mer recommend . <Page 33> 94.05.20.
-Add ADP_EN to S_CLK(GPIO22) by R1385(0_0402) . (Modify CKT,BOM&Layout)
- A d d A D P _ I D t o E C _ G P I O 1 9 b y R 1 3 8 2 ( 0 _ 0 4 0 2 ) . ( M o d i f y C K T , B O M & L a y o u t)
- A d d A D P _ P S 1 t o E C _ G P I O 1 2 b y R 1 3 8 3 ( 0 _ 0 4 0 2 ) . ( M o d i f y C K T , B O M & L a y o u t)
- A d d A D P _ P S 0 t o E C _ G P I O 1 0 b y R 1 3 8 4 ( 0 _ 0 4 0 2 ) . ( M o d i f y C K T , B O M & L a y o u t)
- R emove R87(@0_0402) . (Modify CKT&BOM)
25. Update ICH7 related designing by customer recommend . <Page 21,35> 94.05.20.
- Change R1363 from 0_0402 to ACCEL@0_0402 . (Modify CKT&BOM)
- C h a n g e R 1 3 6 3 . 2 c o n n e c t i o n f r o m A D P _ P W R I D t o A D P _ I D . ( M o d i f y C K T & L a y o ut)
- Reserve R1386(@0_0402) from PREP2# to U26.AD20(ICH7_GPIO38) . (Modify CKT&Layout)
- R e s e r v e R 1 3 8 7 ( @ 1 0 K _ 0 4 0 2 ) f r o m P R E P 2 # t o + 3 V S . ( M o d i f y C K T & L a y o u t)
26. Update LAN chip schematic related by cust omer recommend . <Page 25> 94.05.20.
- C h a n g e R 7 3 . 1 a n d R 3 6 . 1 c o n n e c t i o n f r o m + 3 V S t o V _ 3 P 3 _ L A N . ( M o d i f y C K T & Layout)
27. Update CardReader chip schematic related by c ustomer recommend . <Page 23> 94.05.20.
- D e l U 4 6 a n d r e l a t e d n e t . ( M o d i f y C K T , B O M & L ayout)
- D e l R 5 9 1 , R 5 9 3 . ( M o d i f y C K T , B O M & L a y o u t)
- C h a n g e R 5 9 4 c o n n e c t i o n t o b e t w e e n + V C C _ S D a n d S D W P # _ S M C E # . ( M o d i f y C K T & L a y o u t)
- C h a n g e R 6 0 2 c o n n e c t i o n t o b e t w e e n + V C C _ S D a n d S M _ R B # . ( M o d i f y C K T & L a y out)
- C hange JP41.36 connection to MSBS_SDCMD_SMWE# . (Modify CKT&Layout)
- C h a n g e J P 4 1 . 2 7 c o n n e c t i o n t o S D C L K _ S M R E # . ( M o d i f y C K T & L a y o u t)
-Change JP41.28 connection to SDWP#_SMCE# . (Modify CKT&Layout)
- C h a n g e J P 4 1 . 2 6 c o n n e c t i o n t o S M _ R B # . ( M o d i f y C K T & L a y out)
- A d d R 1388(0_0402) between MC_PWRON# and MC_PWRON . (Modify CKT,BOM&Layout)
- R e move Q77,D45,D46,R595,D48 . (Modify CKT&BOM)
28. Update Clock Gen. schematic related by cust omer recommend . <Page 15> 94.05.20.
- D e l R 1 3 2 8 , R 1 3 2 9 , R 1 3 3 0 , R 1 3 3 1 , R 1 3 3 2 a n d r e l a t e d n e t . ( M o d i f y C K T , B O M & L ayout)
- C h a n g e U 2 5 . 1 5 c o n n e c t i o n t o F S B . ( M o d i f y C K T & L a yout)
- C h a n g e U 2 5 . 1 6 , 2 4 , 4 1 c o n n e c t i o n t o + C K _ V D D _ D P . ( M o d i f y C K T & L a y out)
- C h a nge U39 from TPA6017A2_TSSOP20 to MAX9710ETP_QFN20 . (Modify CKT,BOM&Layout)
-Change C734,C735,C736 connection to +CK_VDD_DP . (Modify CKT&Layout)
- Del D59,R613,R431,C93,R439,R438,C663,C664,R971~R974,C661 . (Modify CKT,BOM&Layout)
- Add R1389(NODP@0_0805),R1390(DP@0_0805),C1010(10U_0805) and related net . (Modify CKT,BOM&Layout)
- C h a n g e C 5 0 3 , C 5 0 2 f r o m 0 . 0 4 7 U t o 0 . 1 U . ( M o d i f y C K T , B O M & L a y out)
- C h a n g e R 1 3 5 2 , R 1 3 3 3 f r o m @ 0 _ 0 4 0 2 t o 0 _ 0 4 0 2 . ( M o d i f y C K T , B O M & L a y o ut)
- A d d R 1 4 0 3 ( 1 0 K _ 0 4 0 2 ) f r o m U 3 9 . 5 t o C 5 0 3 . 2 , R 1 4 0 4 ( 1 0 K _ 0 4 0 2 ) f r o m U 3 9 . 5 t o U 3 9 . 7 . ( M o d i f y C K T , B O M&Layout)
29. Update MXM schematic related by customer r ecommend . <Page 18> 94.05.23.
- A d d R 1 4 0 5 ( 1 0 K _ 0 4 0 2 ) f r o m U 3 9 . 1 t o C 5 0 2 . 2 , R 1 4 0 6 ( 1 0 K _ 0 4 0 2 ) f r o m U 3 9 . 1 t o U 3 9 . 1 9 . ( M o d i f y C K T , B O M&Layout)
-Reserve R1391(@0_0402) from JP39.125 to CLKREQA# . (Modify CKT&Layout)
-Add R1407(0ohm) from U39.4 to AGND;Add C1020(10U_1206) from +5VALW and GND . (Modify CKT,BOM&Layout)
- A d d R 1 3 9 2 ( 0 _ 0 4 0 2 ) f r o m J P 3 9 . 1 5 7 t o A D P _ P R E S . ( M o d i f y C K T , B O M & L a y o ut)
- A d d C 1 0 2 1 ( 1 U _ 0 6 0 3 ) f r o m U 3 9 . 2 t o A G N D . ( M o d i f y C K T , B O M & L a y o u t)
30. Update LAN chip schematic related by cust omer recommend . <Page 25> 94.05.23.
- C h a n g e C 6 6 2 f r o m @ 1 0 0 U _ 6 . 3 V t o @ 1 5 0 U _ D _ 6 . 3 V . ( M o d i f y C K T & L a y o u t)
- R e s e r v e R 2 8 4 ( @ 4 . 7 K _ 0 4 0 2 _ 5 % ) f r o m U 6 . L 3 t o V _ 3 P 3 _ L A N . ( M o d i f y C K T & L a y o u t)
- A d d T 5 9 o n U 6 . L 3 . ( M o d i f y C K T & L a y out)
- A d d T 6 0 o n U 6 . M 5 . ( M o d i f y C K T & L a y o ut)
S e c u r i t y C l a s s ification
Compal Secret Data
Compal Electronics, Inc.
- R e s e r v e Q 9 4 ( @ 2 N 7 0 0 2 _ S O T 2 3 ) a n d c h a n g e R 1 3 8 0 c o n n e c t i o n a s u p d a t e s c h e m a t i c . ( M o d i fy
2 0 0 5 /03/10
2 0 0 6 /03/10
Title
Issued Date
D e c i p h e red Date
C K T&Layout)
H
/ W 2 E E Dept. PIR SHEET(3)
T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
Rev
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
- D e l R 1 3 8 1 a n d s h o r t Q 2 9 . 3 t o G N D d i r e c t l y . ( M o d i f y C K T & Layout)
1.0
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
L A - 2 8 2 1P
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:
1

Saturday, January 14, 2006

Sheet
5

50

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52

E A L 8 0 f r o m D B - 1 S t e p t o DB-2 Step LA-2821 REV:0.1 -> 0.2 Modify <94.05.10.~94.05.30. >

43. Reserve a 0ohm resistor for time delay pass through schem atic by Customer request. <Page 37> 94.05.27.
- R eserve R1402(@0_0402) between PWR_GD and PGD_IN . (Modify CKT&Layout)
44. Change the resistor value to tune the delay schemat ic by Customer request. <Page 37> 94.05.27.
- C h a n g e R 3 8 f r o m 1 0 0 K _ 0 4 0 2 t o 4 7 K _ 0 4 0 2 . ( M o d i f y C K T & B OM)
45. Change BOM option for Intel chipset ver:A1 by C ustomer recommend . <Page 7,21> 94.05.27.
-Change R1309 from @0_0402 to 0_0402, remove R1015(@100K_0402) . (Modify CKT&BOM)
46. Add a 0ohm resistor for debug by Custome r recommend . <Page 4,20> 94.05.27.
- A d d R 1 4 0 8 ( 0 _ 0 4 0 2 ) b e t w e e n U 2 6 . H 2 2 a n d H _ S T P C L K # . ( M o d i f y C K T , B O M & L a y o ut)
47. Add a 0.1UF CAP to improve Cut Moat issue for RGB signals . <Page 36> 94.05.27.
- A d d C 1 0 2 2 ( 0 . 1 U _ 0 6 0 3 ) b e t w e e n + 3 V S a n d + V C C P . ( M o d i f y C K T , B O M & L a y out)
48. Add 10Kohm pull-high to +VCC_SM_XD for TI FAE recommend . <Page 23> 94.05.27.
- A d d R1396 and R1397(10K_0402) Pull-High to +VCC_SM_XD for MSBS_SDCMD_SMWE# and SDCLK_SMRE# .
( M odify CKT,BOM&Layout)
49. Update TPM related schematic for Vendor r eview result . <Page 32> 94.05.27.
-Add R1409(TPM1.2@0_0402) from U66.7 to GND, remove R1379(@4.7K_0402) . (Modify CKT,BOM&Layout)
- C h a n g e C 1 9 3 . 1 c o n n e c t i o n f r o m + 3 V t o + 3 V A L W f o r T P M 1 . 2 . ( M o d i f y C K T & Layout)

E A L 8 0 f r o m S I - 1 S t e p t o SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

1. Add discharge circuit for BT_LED and WL_LED to solve t he LED always light on issue. <Page 32> 94.08.23.
- A d d R 1 4 4 0 a n d R 1 4 4 1 ( 1 0 0 K _ 0 4 0 2 ) f o r B T _ L E D a n d W L _ L E D d i s c h a r g e . ( M o d i f y C K T , B O M & L a y o u t)
2. Remove DPRSLPVR NB side PullHigh resistor for I ntel document update. <Page 7> 94.08.24.
- R e m ove R1209(@10K_0402) for DPRSLPVR . (Modify CKT&BOM)
3. Keep TPM1.2 on Board and Delete TPM1.1 Module Conn ector designing. <Page 32> 94.08.24.
- D e l J P 3 3 , R 1 2 3 6 , R 1 2 4 2 , R 1 2 5 3 , C 1 9 1 , C 1 9 2 , C 1 9 3 a n d r e l a t e d s c h e m a t i c . ( M o d i f y C K T , B O M & L a y o ut)
4. Update TPM1.2 chip PCB layout footprint. <Page 32> 94.08.24.
- Change U66 PCB Footprint from SLD9630TT_TSSOP28 to SLB-9635-TT-1P2_TSSOP28. (Modify CKT&Layout)
5. Correct ODD CSEL option se tting. <Page 20> 94.08.24.
- R emove R460(@4.7K_0402) and add R557(470_0402). (Modify CKT&BOM)
6. Correct SPI I/F Power Source for Capell_Valley_CRB_Schematics_ Rev1_502.pdf update . <Page 32> 94.08.26.
- C h a n g e U 6 1 . 8 , U 6 5 . 8 , R 1 2 8 7 . 1 a n d R 1 2 8 8 . 1 P o w e r R a i l f r o m + 3 V S t o + 3 V A L W . ( M o d i f y CKT&Layout)
7. Modify Mini-Card debug interface design for customer update . <Page 27> 94.08.30.
- M o v e + 3 V A L W f r o m p i n 3 9 t o p i n 4 5 a n d m o v e C A P S _ L E D # f r o m p i n 4 1 t o p i n 5 1 . ( M o d i f y CKT&Layout)
8. Update ADI1981HD CIS symbol and PCB F ootprint . <Page 28> 94.08.30.
- U pdate U14 CIS symbol and change PCB Footprint from AD1981B_LQFP48 to AD1981HDJSTZ-REEL_LQFP48.
( Modify CKT&Layout)
9. Change PCI-E Ports for ICH7 modify . <Page 21,24,35> 94.08.31.
- C h a n g e E x p r e s s C a r d ( N C ) c o n n e c t i o n t o p o r t 3 , C h a n g e D o c k i n g c o n n e c t i o n t o p o r t 4 . ( M o d i f y C KT&Layout)
10. Update Accelerometer related design for custome r request . <Page 19,21,33,36> 94.09.02.
- D e l D 6 1 , C 1 0 1 8 , R 1 3 9 5 & Q 9 5 . ( M o d i f y C K T & L a y out)
- A d d Q 7 5 , R 1 8 7 ; c h a n g e D 1 2 t o D u a l L E D . ( M o d i f y C K T , B O M & L a y out)
- A d d n e t H D D _ S T P # f r o m G P I O 1 9 o f I C H 7 t o Q 7 5 . ( M o d i f y C K T & L a y out)
- I n s t a l l R 1 3 7 4 a n d c h a n g e R 1 0 6 0 t o n o - s t u f f . ( M o d i f y C KT&BOM)
- D e l R 1 3 6 3 a n d R 1 3 6 4 ; A d d S B G P I O t e s t p a d T 8 0 , T 8 9 , T 9 9 , T 1 0 6 . ( M o d i f y C K T , B O M & L ayout)
11. Modify Mini-Card debug interface design for customer update . <Page 27> 94.09.02.
- R e move R1435 and R1436(@0_0402). (Modify CKT&BOM)
12. Modify TI PCI7612 designing for vendo r request . <Page 23> 94.09.06.
- C h a n g e R 5 7 3 f r o m 1 0 K _ 0 4 0 2 t o 0 _ 0 4 0 2 . ( M o d i f y C K T & B O M)
- C h a n g e R 5 9 4 , R 1 3 9 6 a n d R 1 3 9 7 f r o m 1 0 K _ 0 4 0 2 t o 1 0 0 K _ 0 4 0 2 . ( M o d i f y C K T & B O M)
- C h a n g e R 6 0 2 f r o m 1 0 K _ 0 4 0 2 t o 2 2 K _ 0 4 0 2 . ( M o d i f y C K T & B O M)
13. Update Accelerometer related design for custome r request . <Page 19,21,33,36> 94.09.02.
- A d d n e t H D D _ S T P f r o m G P I O 1 9 o f I C H 7 t o Q 8 4 . 2 . ( M o d i f y C K T & L a yout)
- Add Q84(2N7002) and R1442(100K_0402) for HDD_STP. (Modify CKT,BOM&Layout)
- R eserve R1443(@0_0402) for HDD_STP#. (Modify CKT&Layout)
14. Update ICH7 GPIO related design for customer request . <Page 21> 94.09.06.
- D e l R 1 3 2 1 a n d R 1 3 2 3 r e l a t e d r e s e r v e d s c h e m a t i c . ( M o d i f y C K T & L a yout)
15. Modify LAN controller related for cu stomer request . <Page 25> 94.09.07.
- A d d a n d c h a n g e R 2 7 7 f r o m @ 0 _ 0 4 0 2 t o 1 0 K _ 0 4 0 2 . ( M o d i f y C K T & B OM)
- R e move R1380(@0_0402) and add Q94(2N7002). (Modify CKT&BOM)
S e c u r i t y C l a s s ification
- C h a n g e R 5 0 6 p u l l - u p t o + 3 V A L W f r o m V _ 3 P 3 _ L A N . ( M o d i f y C K T & L a y out)
Issued Date
- A d d Q 1 0 0 ( S I 2 3 0 1 B D S ) , r e s e r v e R 8 3 ( @ 0 _ 0 4 0 2 ) a n d r e l a t e d s c h e m a t i c . ( M o d i f y C K T , B O M & L a y o ut)

16. Modify PCMCIA Connector design for M/E team request . <Page 24> 94.09.08.
- Change JP9 PCBFootprint from SLINK_AFH-1000-17A0-3_104P to TYCO_C-PT05-023-D1_150P_LT.
( M odify CKT,BOM&Layout)
17. Delete New Card, USB HUB related design for customer S pec update . <Page 15,21,24,30,31> 94.09.08.
- Delete R1272,R1273,R1274,R1275,R1276,R1277,R1278,R1279,R1280,R1282,R1316,C959,C960,C961,C962,
C 963,C964,C965,C966,C967,C968,C969,C970,C971,C972,C973,U60,R535,C541,L34,C521,C529,C535,C517,
C 558,C540,C559,R981,U53,Y6,R984,C22,C27,L37,R1353,R537,R539,R523,R1317,R1318,R1099,R1102,
R1100,R1103,C712,C713; Add T107. (Modify CKT,BOM&Layout)
- D e l e t e R 9 8 2 , R 9 8 3 r e s e r v e . ( M o d i f y C K T & L a y o ut)
18. Modify MiniCard related design for customer request. <Page 27> 94.09.08.
- A dd Q101,Q102,R1445; Reserve R1444(@0_0805). (Modify CKT,BOM&Layout)
19. Delete FWH I/F BIOS related design for customer r equest. <Page 15,19,20,21,32> 94.09.08.
- D e l &U21(SST49LF008A-33-4C-NH),U21,U20,R273,R278,RP42,R1125,C42,C333. (Modify CKT,BOM&Layout)
- D e l R 2 7 9 , C 4 3 r e s e r v e . ( M o d i f y C K T & L a y o u t)
- A d d T 1 0 8 , T 1 0 9 , T 1 1 0 . ( M o d i f y C K T & L a y o u t)
- D e l e t e B I O S _ S E L 1 a n d r e p l a c e w i t h s h o r t t o G N D d i r e c t l y . ( M o d i f y CKT&Layout)
20. Wire VGA Thermal inform signal with System side for function workable. <Page 21> 94.09.09.
- Add R252(0_0402). (Modify CKT&BOM)
21. Modify MiniCard related design fo r customer. <Page 27> 94.09.10.
- A d d J 4 4 ( J U M P _ 4 3 X 3 9 ) a n d r e s e r v e J 4 5 ( @ J U M P _ 4 3 X 3 9 ) f o r P o w e r S o u r c e o p t i o n . ( M o d i f y C K T & L a y o ut)
- C h a n g e R 1 4 4 4 . 1 c o n n e c t i o n f r o m + 3 V A L W t o + 3 V S . ( M o d i f y C K T & L a y out)
- R emove Q101,Q102,R1445 and add R1444. (Modify CKT&BOM)
22. Modify TI PCI7612 designing for vendo r request . <Page 23> 94.09.10.
- C h a n g e R 5 7 3 . 1 p o w e r c o n n e c t i o n t o + S C _ P W R f r o m + 5 V S . ( M o d i f y C K T & L a yout)
- C h a n g e p o w e r r a i l t o R 6 1 5 & R 6 1 6 t o + 3 V S f r o m + 5 V S a n d r e m o v e b o t h R 6 1 5 & R 6 1 6 . ( M o d i f y C K T , BOM&Layout)
23. Modify LAN Transformer designing for cu stomer request . <Page 26> 94.09.10.
- C h a n g e R 2 7 0 , R 2 7 1 c o n n e c t i o n b y a d d C 3 3 3 b e t w e e n g r o u n d a n d R 2 7 0 / R 2 7 1 . ( M o d i f y C K T , B O M & L ayout)
24. Create an option to use the 32KHz clock from KBC for TP M1.2 for customer request . <Page 32,33> 94.09.10.
- R e s e r v e R 1 4 4 6 ( @ 0 _ 0 4 0 2 ) t o c o n n e c t U 4 7 . 5 8 a n d U 6 6 . 1 3 . ( M o d i f y C K T & L a y o ut)
25. Delete MiniPCI Debug I/F reserve for Layout space free . <Page 19,27,32> 94.09.12.
-Del R1117,R235,R441,R447,R451,R452 and JP20. (Modify CKT,BOM&Layout)
- D e l R 4 4 8 , C 5 3 7 , R 4 3 7 a n d Q 4 9 r e s e r v e . ( M o d i f y C K T & L a y o u t)
- C h a n g e R 1 4 2 0 . 1 c o n n e c t i o n f r o m + 3 V A L W t o + 3 V L . ( M o d i f y C K T & L a y out)
- C h a n g e C 2 9 2 , C 5 3 8 , C 5 4 2 p o w e r s o u r c e f r o m + 3 V S t o + 3 V S _ M I N I . ( M o d i f y C K T & L a yout)
- A d d H 2 9 , H 3 0 ( H _ C 2 3 6 D 1 5 7 ) ( M i n i C a r d S t a n d O f f ) . ( M o d i f y C K T , B O M & L a y o u t)
26. Change Jopen PAD for CIC DFx req uest . <Page 15> 94.09.12.
- C h a n g e J 2 9 P C B f o o t p r i n t t o J U M P _ 4 3 X 3 9 . ( M o d i f y C K T & L a y out)
27. Change LAN chip desgin to switch LAN power with LP_ EN# for customer request . <Page 25> 94.09.13.
- I nstall R15(4.7K_0402_5%) and no-stuff U36(@SN74LVC1G17DBVR_SOT23-5). (Modify CKT&BOM)
28. Modify TPM1.2 related design about the ADP_EN for c ustomer request . <Page 32,33> 94.09.13.
- R e s e r v e R 1 4 4 7 ( @ 0 _ 0 4 0 2 ) c l o s e t o Y 8 . 1 . ( M o d i f y C K T & L a y o ut)
- Reserve R1448(@0_0402) for ADP_EN. (Modify CKT&Layout)
29. Modify BT related design for cust omer request . <Page 30> 94.09.14.
- C h a n g e R 4 5 4 t o 4 7 K f r o m 1 K . ( M o d i f y C K T & B OM)
- R e s e r v e a 0 . 1 u F c a p ( n o - s t u f f ) f r o m R 4 5 4 . 2 t o g r o u n d . ( M o d i f y C K T&Layout)
30. Modify LAN chip related design for c ustomer request . <Page 25> 94.09.14.
- A d d R 4 5 8 ( 0 _ 0 4 0 2 ) b e t w e e n Q 1 0 0 . 2 a n d Q 9 4 . 1 . ( M o d i f y C K T , B O M & L a yout)
31. Modify BITCLK related design for EMI req uest . <Page 20,28,34> 94.09.14.
- R e s e r v e R 1 0 3 2 , C 7 2 2 c l o s e t o U 1 4 . 6 . ( M o d i f y C K T & L a y o ut)
- M o v e R 1 0 2 8 , C 7 2 1 c l o s e t o J P 3 2 . 1 2 ; R 1 3 1 4 , R 3 7 1 c l o s e t o U 2 6 . U 1 . ( M o d i f y C K T & L ayout)
32. Modify LID_SW# related design for M/E request . <Page 34> 94.09.14.
- A d d R 1 4 4 9 c l o s e t o J P 1 8 . 1 6 . ( M o d i f y C K T , B O M & L a y o ut)
33. Modify Clock Gen. related design for V endor request . <Page 15> 94.09.14.
-Change R1092 from 475_0402_1% to 4.7K_0402_1%. (Modify CKT&BOM)
34. Modify NB chip CFG11 related design for Intel CRB Rev1_502 update . <Page 11> 94.09.14.
- R e m ove R1154(@2.2K_0402_5%). (Modify CKT&BOM)
35. Modify Smart AC Adaptor related design f or customer request . <Page 11> 94.09.14.
- C h a n g e R 1 2 3 7 f r o m 1 0 K _ 0 4 0 2 t o 1 0 0 K _ 0 4 0 2 . ( M o d i f y C K T & B O M)
Compal Secret Data
2 0 0 5 /03/10

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

H / W 2 E E Dept. PIR SHEET(4)

Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
5

51

of

52

E A L 8 0 f r o m S I - 1 S t e p t o SI-2 Step LA-2821 REV:0.3 -> 0.4 Modify <94.08.23.~94.09.21. >

36. Add DDR2 Module Thermal inform function to NB for customer request. <Page 7,13,14> 94.09.15.
- A d d R1450(0_0402) between DDR_THERM# and PM_EXTTS#0 . (Modify CKT,BOM&Layout)
37. Reserve a cap at JP30.P2 pin for +5VS of Docking for customer request. <Page 35> 94.09.15.
-Reserve C1033(@22U_0805_6.3V4Z) close to JP30.P2. (Modify CKT&Layout)
38. Delete Bulk Cap. Daul Layout design reserve for DFx request. <Page 18> 94.09.15.
-Change C633 from @47U_25V(Non-LF) to 100U_25V(250',10sec,LF); Del C1013~C1017 . (Modify CKT,BOM&Layout)
- D e l C 8 2 3 ( 1 0 0 U 6 . 3 V M B ( 6 . 3 X 6 . 0 ) C V - A X ) , C 9 3 9 , C 8 3 0 , C 8 0 6 ( 2 2 0 U _ C 6 _ 6 . 3 V _ M _ R 1 5 ) . ( M o d i f y C K T & L a y o ut)
- D el C979(220U_D2_2VK_R9); Change C670 to SF22001M300. (Modify CKT,BOM&Layout)
- Del C1012(150U_D_6.3VM); Change C671 to SF22001M300. (Modify CKT,BOM&Layout)
- Del C567,C568(150U_D_6.3VM); Change C1,C527 to SF22001M300. (Modify CKT,BOM&Layout)
39. Remove all Clock Gen. pairs Pull-Down Resistors for LP design recommend. <Page 15> 94.09.15.
- R e move R1071,R1073,R1076,R1082,R1119,R1122,R1094,R1096,R1258,R1260,R1112,R1116,R1250,R1252,
R 1 1 24,R1127,R1134,R1137,R1238,R1239. (Modify CKT&BOM)
40. Modify XMIT_OFF related design for S/ W request. <Page 27> 94.09.16.
- Add R1424(0_0402) between XMIT_OFF and XMIT_OFF#. (Modify CKT,BOM&Layout)
41. Modify TI PCMCIA Controller related design for Vendor request. <Page 23,24> 94.09.16.
- A d d R 5 9 1 ( 0 _ 0 4 0 2 ) c l o s e t o U 4 2 . E 2 . ( M o d i f y C K T , B O M & L a y o ut)
- A d d R 6 1 7 ~ R 6 2 0 , R 6 2 3 , R 6 2 4 ( 0 _ 0 4 0 2 ) c l o s e t o J P 4 1 . ( M o d i f y C K T , B O M & L a y o u t)
- R e s e r v e C 3 6 9 , C 3 7 2 , C 3 7 3 , R 5 9 3 , R 5 9 9 , R 6 1 3 , R 6 1 4 c l o s e t o J P 9 . ( M o d i f y C K T & L a y o u t)
- R e move R565. (Modify CKT&BOM)
42. Modify Audio Codec related design to avoid a small amount of noise on pin 2 could cause the codec to power
up in a test mode. <Page 28> 94.09.21.

-Change R422 from @0_0402 to 10K_0402. (Modify CKT&BOM)

43. Modify ICH7 related design for ICH7M & 3945abg Host Interf ace auto-detect sequence Issue (Sighting# 80332).
<Page 21> 94.09.21.
- C h a n g e d e c o u p l i n g c a p s ( C 7 1 0 & C 7 1 1 ) f r o m 0 . 1 u F _ 0 4 0 2 t o 0 . 1 5 u F _ 0 6 0 3 ) . ( M o d i f y C K T , B O M & L ayout)
44. Modify Clock Gen. all series termination resistors for the differential signals related design for ICS recommend.
<Page 15> 94.09.21.
- C hange R1070,R1072,R1075,R1081,R1118,R1121,R1257,R1259,R1093,R1095,R1144,R1145,R1123,R1126,R1111,
R 1 1 1 5 , R 1 2 4 9 , R 1 2 5 1 f r o m 3 3 _ 0 4 0 2 t o 2 4 _ 0 4 0 2 . ( M o d i f y C K T & B O M)

Compal Secret Data

S e c u r i t y C l a s s ification
2 0 0 5 /03/10

Issued Date

2 0 0 6 /03/10

D e c i p h e red Date

T H I S S H E E T O F E N G I N E E R I NG DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
A N D T R A D E S E C R E T I N F O R M A T I O N. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T E X C E P T A S A U T HORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
M A Y B E U S E D B Y O R D I S CLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

Title

H / W 2 E E Dept. PIR SHEET(5)

Size

Rev
1.0

L A - 2 8 2 1P
Date:

Document Number
Saturday, January 14, 2006

Sheet
5

52

of

52