LAB 1: LOGIC ANALYZER FAMILIARIZATION

ECE 218-01, Thursday Lab

Melanie Dooley
TA: Yan Han
Date of Experiment: 10 September 2015
Report Due Date: 17 September 2015

Lab 1, Dooley, Page 1

I.

INTRODUCTION
The purpose of this lab was to help students become familiar with the lab setting. This familiarization
involved an introduction to working with the breadboard, logic analyzer, and general lab procedures. To achieve
this, two simple circuits were erected, and simple data was gathered from them using lab equipment.

II.

THEORY

In Lab 1, the two circuits built and tested were simple 4-bit counters. One circuit counted in binary, and the
other counted in Gray code. Preliminary questions delved briefly into the different use cases for binary and Gray
code, but overall, Lab 1 did not heavily interact with theoretical material. Lab 1 was simply an exercise in
becoming comfortable working in the lab.
Due to the introductory nature of Lab 1, preliminary work was extensive. In order to successfully complete
the lab, students needed a complete understanding of how to use the logic analyzer as well as how to physically
build a circuit. To fulfill these preliminary requirements, students needed to search datasheets for parameters of
the chips in use, and students needed to find information on the logic analyzer model provided in the lab. A solid
understanding of binary, Gray code, and different logic types (CMOS, TTL, etc.) was also necessary; any student
lacking this knowledge could have referenced the course textbook or the internet.
III.

EXPERIMENTAL PROCEDURE
Materials Needed:
Breadboard
Digilent Analog Discovery device (logic analyzer)
WaveForms (software)
1 x 74LS163 (4-bit counter)
1 x 74LS00 (quad 2-input NAND gate)
Wire
Procedure:
1. Set up the circuit depicted in Figure 1.
2. Using the logic analyzer and software, supply +5 V and ground to the breadboard.
3. Using the logic analyzer and software, supply a 1 Hz, 50% duty cycle clock to the circuit.
4. In the software, engage all supplies (ground, +5 V, and clock).
5. Using the logic analyzer and software, collect digital-in signals from four terminals connected to Q0
through Q3 on the circuit.
6. Using the logic analyzer and software, collect digital-in signals from four terminals connected to Q4
through Q7.
7. Photograph the collected data sets.
8. Analyze data.
A photograph of the wired circuit is in Figure 2. The same photograph is labeled in Figure 3.
Results from data collection are listed in Figure 4 and Table 1.

Lab 1, Dooley, Page 2

Figure 1: Lab 1 Schematic

Figure 2: Breadboard Setup

Lab 1, Dooley, Page 3

Figure 3: Labeled Breadboard Setup

Lab 1, Dooley, Page 4

Figure 4: Data Collected (Datasheet)

Table 1: Data Collection Results
Step
Output
Binary
Bus
Q0
Q1
Q2
Q3
Gray
Code
Bus
Q4
Q5
Q6
Q7

IV.

10

11

12

13

14

15

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0
0
0
0
0000

0
0
0
1
0001

0
0
1
0
0011

0
0
1
1
0010

0
1
0
0
0110

0
1
0
1
0111

0
1
1
0
0101

0
1
1
1
0100

1
0
0
0
1100

1
0
0
1
1101

1
0
1
0
1111

1
0
1
1
1110

1
1
0
0
1010

1
1
0
1
1011

1
1
1
0
1001

1
1
1
1
1000

0
0
0
0

0
0
0
1

0
0
1
1

0
0
1
0

0
1
1
0

0
1
1
1

0
1
0
1

0
1
0
0

1
1
0
0

1
1
0
1

1
1
1
1

1
1
1
0

1
0
1
0

1
0
1
1

1
0
0
1

1
0
0
0

INTERPRETATION

The results from Figure 4 and Table 1 indicate the counter progressed through 16 unique digits for both binary
and Gray code. For both the binary and Gray code, the bits flipped at the expected points, and each string was
unique from the others in the set. For binary, each bit increase moved to the least significant place, as expected.
For Gray code, each bitstring only differed by one bit from the adjacent bitstrings, as expected. Furthermore,
from Figure 4, the bitstrings repeated the same pattern after passing the 15th string, thus indicating periodicity in
the progression of the bitstrings for each code representation.
Error for this lab would have been largely due to human mistakes. This being the first lab of an introductory
course, it was common for students to make small but impactful mistakes. For instance, errors in wiring were
common, as was improperly configuring/engaging sources. Human error was minimized in this lab by rechecking all circuits and sources before attempting to gather data.
It was also possible to have error introduced by faulty chips. Minimizing this error source involved simple
tests on the chips to ensure functionality if unexpected data presented itself.
Overall, error was not a great concern in this lab due to its simplicity.
V.

CONCLUSIONS

From the evidence examined briefly in Section IV, the counter operated correctly for both binary four-bit
counting and Gray code four-bit counting.
Lab 1, Dooley, Page 5

In order to complete this lab successfully, students were required to have an understanding of the logic
analyzer, software, and general circuit construction.
The objectives of the lab were thus achieved.

Lab 1, Dooley, Page 6