UNIT I

1.1 EMBEDDED SYSTEM OVERVIEW

System: A system is an arrangement in which all its unit assemble work together according to a
set of rules. It can also be defined as a way of working, organizing or doing one or many tasks
according to a fixed plan.
For example, a watch is a time displaying system. Its components follow a set of rules to show
time. If one of its parts fails, the watch will stop working. So we can say, in a system, all its
subcomponents depend on each other.
Embedded System: As its name suggests, Embedded means something that is attached to another
thing. An embedded system can be thought of as a computer hardware system having software
embedded in it. An embedded system can be an independent system or it can be a part of a large
system. An embedded system is a microcontroller or microprocessor based system which is
designed to perform a specific task.
For example, a fire alarm is an embedded system it will sense only smoke. An embedded system
has three components
It has hardware.
It has application software.
It has Real Time Operating system
RTOSRTOS that supervises the application software and provide mechanism to let the processor
run a process as per scheduling by following a plan to control the latencies. RTOS defines the
way the system works. It sets the rules during the execution of application program. A small
scale embedded system may not have RTOS.
So we can define an embedded system as a Microcontroller based, software driven, reliable,
realtime control system.
Characteristics of an Embedded System
Single functioned: An embedded system usually performs a specialized operation and does
the samerepeatedly. For example: A pager always functions as a pager.
Tightly constrained All computing systems have constraints on design metrics, but those on an
embedded system can be especially tight. Design metrics is a measure of an implementation's
features suchas its cost, size, power, and performance. It must be of a size to fit on a single chip,

must perform fast enough to process data in real time and consume minimum power to extend
battery life.
Reactive and Real time Many embedded systems must continually react to changes in the
system's environment and must compute certain results in real time without any delay. Consider
an example of a car cruise controller it continually monitors and reacts to speed and brake
sensors. It must compute acceleration or de-accelerations repeatedly within a limited time a
delayed computation can result in failure to control of the car.
Microprocessors based It must be microprocessor or microcontroller based.
Memory It must have a memory, as its software usually embeds in ROM. It does not need any
secondary memories in the computer.
Connected It must have connected peripherals to connect input and output devices.
HWSW systems Software is used for more features and flexibility. Hardware is used for
performance and security.

ASIP and
ASIC

Analog IO
Memory

Processor
Cores

Digital IO

Basic Structure of an Embedded System

The following illustration shows the basic structure of an embedded system

Sensor It measures the physical quantity and converts it to an electrical signal which can be
read by an observer or by any electronic instrument like an A2D converter. A sensor stores the
measured quantity to the memory.
AD Converter An analog to digital converter converts the analog signal sent by the sensor into
a digital signal.
Processor & ASICs Processors process the data to measure the output and store it to the
memory.
DA Converter A digital to analog converter converts the digital data fed by the processor to
analog data
Actuator An actuator compares the output given by the DA Converter to the actual Expected
expected output stored in it and stores the approved output.

1.2 APPLICATIONS
Household appliances: Microwave ovens, Television, DVD Players & Recorders
Audio players
Integrated systems in aircrafts and missiles
Cellular telephones
Electric and Electronic Motor controllers
Engine controllers in automobiles
Calculators
Medical equipments
Videogames
Digital musical instruments, etc.

1.3 FEATURES
Features of Embedded Systems?

Embedded systems example the versatility of the embedded computer system lends itself to
utility in all kinds of enterprises, from the simplification of deliverable products to a reduction in
costs in their development and manufacture.
Embedded Systems are the crucial components of the modern compacted devices with
multifunction capabilities. Embedded systems are specific computer programs that combine the
functions of specially designed softwares and hardwares and are completely encapsulated by
the devices that they control.

 An embedded system has specific requirements and performs pre-defined tasks, unlike a
general-purpose personal computer. An embedded system is a programmed hardware device. A
programmable hardware chip is the platform and it is programmed with particular applications.
Embedded systems are a combination of hardware and software which facilitates mass
production and a host of applications.
Features of Embedded Operating System?
1-Embedded systems are designed to do some specific task, rather than be a general-purpose
computer for multiple tasks. Some also have real-time performance constraints that must be met,
for reasons such as safety and usability others may have low or no performance requirements,
allowing the system hardware to be simplified to reduce costs.
2-Embedded systems are not always standalone devices. Many embedded systems consist of
small, computerized parts within a larger device that serves a more general purpose. For
example, the Gibson Robot Guitar features an embedded system for tuning the strings, but the
overall purpose of the Robot Guitar is, of course, to play music similarly, an embedded system in
an automobile provides a specific function as a subsystem of the car itself.
3-The program instructions written for embedded systems are referred to as firmware, and are
stored in read-only memory or Flash memory chips. They run with limited computer hardware
resources: little memory, small or non-existent keyboard and/or screen.
* Size & Weight : Microcontrollers are designed to deliver maximum performance for
minimum size and weight. A centralised on-board computer system would greatly outweigh a
collection of microcontrollers.
* Efficiency

: Microcontrollers are designed to perform repeated functions for long periods

of time without failing or requiring service. Other computer systems are prone to software and
hardware failure as well as a whole host of other problems recognisable to the users of any home
computer. Above all other considerations, computer systems must be 100% reliable when trusted
to control such functions as braking in an automobile.

1.4 Embedded Systems Architecture Types

The 8051 microcontrollers work with 8bit data bus. So they can support external data
memory up to 64K and external program memory of 64k at best. Collectively, 8051
microcontrollers can address 128k of external memory.
When data and code lie in different memory blocks, then the architecture is referred as
Harvard architecture. In case data and code lie in the same memory block, then the architecture is
referred as Von Neumann architecture.
Von Neumann Architecture
The Von Neumann architecture was first proposed by a computer scientist John von
Neumann. In this architecture, one data path or bus exists for both instruction and data. As a
result, the CPU does one operation at a time. It either fetches an instruction from memory, or
performs read/write operation on data. So an instruction fetch and a data operation cannot occur
simultaneously, sharing a common bus.

Von-Neumann architecture supports simple hardware. It allows the use of a single, sequential
memory. Today's processing speeds vastly outpace memory access times, and we employ a very
fast but small amount of memory cache local to the processor.
Harvard Architecture
The Harvard architecture offers separate storage and signal buses for instructions and
data. This architecture has data storage entirely contained within the CPU, and there is no access
to the instruction storage as data. Computers have separate memory areas for program
instructions and data using internal data buses, allowing simultaneous access to both instructions
and data. Programs needed to be loaded by an operator the processor could not boot itself. In a
Harvard architecture, there is no need to make the two memories share properties.

VonNeumann Architecture vs Harvard Architecture

The following points distinguish the Von Neumann Architecture from the Harvard Architecture.
Von-Neumann Architecture
Single memory to be shared by both

Harvard Architecture
Separate memories for code and data.

code and data

Processor needs to fetch code in a
separate clock cycle and data in another
clock cycle. So it requires two clock
cycles.
Higher speed, thus less time consuming
Simple in design.

Single clock cycle is sufficient, as

separate buses are used to access code
and data.
Slower in speed, thus more time
consuming
Complex in design.

CISC and RISC

CISC is a Complex Instruction Set Computer. It is a computer that can address a large
number of instructions. In the early 1980s, computer designers recommended that computers
should use fewer instructions with simple constructs so that they can be executed much faster
within the CPU without having to use memory. Such computers are classified as Reduced
Instruction Set Computer or RISC.
CISC vs RISC
The following points differentiate a CISC from a RISC
CISC

RISC

Larger set of instructions. Easy to

Larger set of instructions. Easy to

program
Simpler design of compiler,

program
Complex design of compiler
Few addressing modes, fix instruction

considering larger set of instructions.

Many addressing modes causing

complex instruction formats.

Instruction length is variable.
Higher clock cycles per second.
Emphasis is on hardware
Control unit implements large
instruction set using micro program

unit.
Slower execution, as instructions are to
be read from memory and decoded by
the decoder unit.
Pipelining is not possible.

format
Instruction length varies
Low clock cycle per second
Emphasis is on software.
Each instruction is to be executed by

hardware
Faster execution, as each instruction is
to be
executed by hardware
Pipelining of instructions is possible,
considering single clock cycle.

1.5 RAM (RANDOM ACCESS MODEL):

Random access model A memory-, a data byte, or a word, or a double word, or a quad
word may be accessed from or at all addressable locations with a similar process would be used
to access from all locations and there is would be equal access time for a read or for a write that
is independent of a memory address location. This mode differentiates from another model called
serial access mode Addresses Addresses Memory (both RAM and ROM) divided into a set of
storage locations, each of which can hold 1 byte (8 bits) of data. The storage locations are
numbered, and the number of a storage location (called its address) is used to tell the memory
system which location the processor wants to reference. Important characteristics of a computer
system is the width of the addresses it uses, which limits the amount of memory that the
processor can address. Most current computers use either 32-bit or 64-bit addresses, allowing
them to access either 232 or 264 bytes of memory. Simple model for RAM and ROM Both has
random-access model of memory All memory operations take the same amount of time
independent of the address of the byte or word at the memory. Simple model for RAM and ROM
Both has random-access model of memory All memory operations take the same amount of time
independent of the address of the byte or word at the memory.
Can be both read and, written, Hold the programs, operating system, and data
required by the system. Generally volatile, meaning that it does not retain the data
stored in it when the system 's power is turned off. A Data that needs to be stored
while the system is off must be written to a permanent storage device, such as a
flash memory or hard disk. An example is as follows: A mobile phone has 128 kB or
256 kB of RAM to hold the stack and temporary variables of the programs, operating
system, and data.

1.6 ROM: The RAM can be both read and, written, and is used to hold the
programs, operating system, and data required by a computer system. In
embedded systems, it holds the stack and temporary variables of the programs,
operating system, and data. RAM is generally volatile, does not retain the data
stored in it when the system 's power is turned off. Any data that needs to be
stored while the system is off must be written to a permanent storage device, such
as a flash memory or hard disk. Contents of the read-only memory cannot be
modified by the computer but may be read. A system has ROM unit(s) for
bootstrap program(s), basic input-output system (BIOS) program(s) and for vector

addresses for the interrupts Used to hold bootstrap program that is executed
automatically by the system every time it is turned on or reset. Instructs the system
to load its operating system off ROM image holds the programs, operating system,
and data required by the system.

1.7 MEMORY MAPS

Memory Maps A memory map for a processor defines how addresses get mapped to
hardware. The total size of the address space is constrained by the address width of
the processor. A 32-bit processor, for example, can address 232 locations, or 4
gigabytes (GB), assuming each address refers to one byte. The address width
typically matches the word width, except for 8-bit processors, where the address
width is typically higher (often 16 bits). An ARM CortexTM - M3 architecture, for
example, has the memory map shown in Figure 8.1. Other architectures will have
other layouts, but the pattern is similar. Notice that this architecture separates
addresses used for program memory (labeled A in the figure) from those used for
data memory (B and D). This (typical) pattern allows these memories to be
accessed via separate buses, permitting instructions and data to be fetched
simultaneously. This effectively doubles the memory bandwidth. Such a separation
of program memory from data memory is known as a Harvard architecture. It
contrasts with the classical von Neumann architecture, which stores program and
data in the same memory. Any particular realization in silicon of this architecture is
constrained by this memory map. For example, the Luminary Micro1 LM3S8962
controller, which includes an ARM CortexTM - M3 core, has 256 KB of on-chip flash
memory, nowhere near the total of 0.5 GB that the architecture allows. This
memory is mapped to addresses 0x00000000 through 0x0003FFFF. The remaining
addresses that the architecture allows for program memory, which are 0x00040000
through 0x1FFFFFFF are reserved addresses, meaning that they should not be
used by a compiler targeting this particular device. The LM3S8962 has 64 KB of
SRAM, mapped to addresses 0x20000000 through 0x2000FFFF, a small portion of
area B in the figure. It also includes a number of on-chip peripherals, which are
devices that are accessed by the processor using some of the memory addresses in
the range from 0x40000000 to 0x5FFFFFFF (area C in the figure). These include
timers, ADCs, GPIO, UARTs, and other I/O devices. Each of these devices occupies a
few of the memory addresses by providing memory-mapped registers. The

processor may write to some of these registers to configure and/or control the
peripheral, or to provide data to be produced on an output. Some of the registers
may be read to retrieve input data obtained by the peripheral. A few of the
addresses in the private peripheral bus region are used to access the interrupt
controller.

1.8 I/O HARDWARE

Embedded processors, be they microcontrollers, DSP processors, or general-purpose processors,
typically include a number of input and output (I/O) mechanisms on chip, exposed to designers
as pins of the chip. In this section, we review some of the more common interfaces provided,
illustrating their properties through the following running example.
The I/O ports are used to connect input and output devices. The common input devices for an
embedded system include keypads, switches, buttons, knobs, and all kinds of sensors (light,
temperature, pressure, etc). The output devices include Light Emitting Diodes (LED), Liquid
Crystal Displays (LCD), printers, alarms, actuators , etc. Some devices support both input and
output, such as communication interfaces including Network Interface Cards (NIC), modems,
and mobile phones.

1.9 TIMERS AND INTERRUPTS

Time and event management in embedded systems
An introduction to timers
Using the mbed Timer object
Using multiple timers

 Using the mbed Ticker object

Hardware interrupts
External interrupts on the mbed
Switch debouncing for interrupt control
Extended exercises
Time and event management in embedded systems
Many embedded systems need high precision timing control and the ability to respond urgently
to critical requests
For example:
A video camera needs to capture image data at very specific time intervals, and to a high
degree of accuracy, to enable smooth playback
A automotive system needs to be able to respond rapidly to a crash detection sensor in order to
activate the passenger airbag
Interrupts allow software processes to be halted while another, higher priority section of
software executes
Interrupt routines can be programmed to execute on timed events or by events that occur
externally in hardware
Routines executed by events that occur from an external source (e.g. a mouse click or input
from another program) can be referred to as event driven.
An introduction to timers
Interrupts in embedded systems can be thought of as functions which are called by specific
events rather than directly in code.
The simplest type of interrupt is one which automatically increments a counter at a periodic
interval, this is done behind the scenes while the software is operating.
Most microcontrollers have built in timers or real-time-interrupts which can be used for this
purpose. The main code can then be executed at specified time increments by evaluating the
counter value. For example, we can set some pieces of software to operate every 10ms and
others to operate every 100ms. We call this scheduled programming.
Using the mbed Timer object
We can use the mbed Timer object to perform scheduled programming:

Using multiple timers

With scheduled programs we often need to execute different sections of code at different rates.
Consider an automotive system:
The engine spark, valve and fuel injection system needs to be controlled and executed at a
high speed, perhaps every 1 ms or less given that the engine revolves at anything up to 8,000
revs per minute.
The fuel tank level monitoring system needs to report the fuel level less often, perhaps every
1000 ms is sufficient.
There is no point in executing both the injection management and the fuel level management
systems at the same rate.
For this reason we can use synchronous programs to improve efficiency
1.10 INTERFACING USING SYSTEM BUS
Interfacing of processor, memory and IO devices using memory system bus
System bus interconnections for a simple bus structure has three sets of signals
System bus defines by address bus, data bus, and control bus
A system-bus interfacing-design is according to the timing diagrams of processor signals, speed,
and word length for instructions and data.
Interconnections for a simple bus structure

Interfacing of processor, memory and IO devices using memory system bus

1.11 ADDRESS BUS: Processor issues the address of the instruction byte or word to memory
system through the address bus. Processor execution unit, when required, issues the address of
data (byte or word) to be read or written using the memory system through address bus. The
address bus of 32-bits used to fetch the instruction or data from an address specified by 32-bit
number.
EXAMPLE
Let a processor at the start reset the program counter at address 0. Then the processor
issues address 0 on the bus and the instruction at address 0 is fetched from memory on
reset
Let a processor instruction be such that it needs to load register r1 from the memory
address M. The processor issues address M on the address bus and data at address M is
fetched.
1.12 DATA BUS: Data Bus Instruction fetch Processor issues the address of the instruction, it
gets back the instruction through the data bus. Data Read When it issues the address of the
data, it loads the data through data bus. Data Write When it issues the address of the data, it
stores the data in the memory through the data bus. A data bus of 32-bits fetches, loads, or stores
the instruction or data of 32-bits.
EXAMPLE

 Processor issues address m for an instruction, it fetches the instruction through data bus
from address m. [For a 32-bit instruction, word at data bus from addresses m, m + 1, m +
2, and m + 3.]
Instruction executes for store of register r1 bits to the memory address M, the processor
issues address M on the bus and sends the data at address M through the data bus. [For
32-bit data, word at data bus sent to the memory addresses M, M + 1, M + 2, and M + 3.]
1.13 CONTROL BUS Control Bus Issues signals to control the timing of various actions during
interconnection. Signals synchronize all the subsystems. address latch enable (ALE)[ Address
Strobe (AS) or address valid, (ADV)], memory read (RD) or write (WR) or IO read (IORD)
or write,(IOWR) or data valid(DAV) Other control signals as per the processor design.
Interrupts and DMA Control Signals Interrupts and DMA Control Signals Interrupt
acknowledge (INTA) [on a request for drawing the processor attention to an event] INT
(Interrupt) from external device interrupt to the system Hold acknowledge (HLDA) [on an
external hold request for permitting use of the system buses] HOLD when external device sends
a hold request for direct memory access (DMA).
Program memory access and data buses multiplexed for memory access in Harvard
Architecture
Address and data buses are multiplexed
Control signal PSEN active when accessing program memory using the address and data buses
Control signal Read or Write active when accessing data memory using the address and data
buses
Time division multiplexed (TDM) address and data bits for the memories
TDM Different time slots, there are is a different set sets (channel) of the signals.
Address signals during one time slot t. and data bus signals in another time slot.
Interfacing circuit for the demultiplexing of the buses uses a control signal in such systems.
Control signal Address Latch Enable (ALE) in 8051, Address Strobe (AS) in 68HC11 and
address valid (ADV) in 80196. ALE or AS or ADV demultiplexes the address and data buses to
the devices
Interfacing Using System and IO 2. Interfacing Using System and IO Buses
System Bus and IO Bus
System bus interconnects
processor

 memory systems and subsystems

Another set of signals called I/O bus
Interfacing of processor with system bus at first level and IO bus at second level
Popular IO buses and wireless communication
PCI Bus interfaces to devices designed to meet the PCI standard.
USB interfaces to devices designed to meet the USB IOs
PCI Bus interfaces to devices designed to meet the PCI standard. USB interfaces to devices
designed to meet the USB IOs
Memory system bus and I/O bus interconnections in a bus structure

2.1 MSP430 FUNCTIONAL BLOCK DIAGRAM

On the left is the CPU and its supporting hardware, including the clock generator. The emulation,
JTAG interface and Spy-Bi-Wire are used to communicate with a desktop computer when
downloading a program and for debugging.

 The main blocks are linked by the memory address bus (MAB) and memory data
bus (MDB).
These devices have flash memory, 1KB in the F2003 or 2KB in the F2013, and 128 bytes of
RAM.
Six blocks are shown for peripheral functions (there are many more in larger devices). All
MSP430s include input/output ports, Timer_A, and a watchdog timer, although the details differ.
The universal serial interface (USI) and sigmadelta analog-to-digital converter (SD16_A) are
particular features of this device.
The brownout protection comes into action if the supply voltage drops to a dangerous level.
Most devices include this but not some of the MSP430x1xx family.
There are ground and power supply connections. Ground is labeled VSS and is taken to define
0V. The supply connection is VCC. For many years, the standard for logic was VCC =+5V but
most devices now work from lower voltages and a range of 1.83.6V is specified for the F2013.
The performance of the device depends on VCC. For example, it is unable to program the flash

memory if VCC < 2.2V and the maximum clock frequency of 16MHz is available only if VCC
3.3V. TI uses a quaint notation for the power connections. The S stands for the source of a fieldeffect transistor, while the C stands for the collector of a bipolar junction transistor, a quite
different device. The MSP430, like most modern integrated circuits, is built using
complementary metaloxidesilicon (CMOS) technology and field-effect transistors. I doubt if it
contains any bipolar junction transistors except possibly in some of the analog peripherals.
There is only one pair of address and data buses, as expected with a von Neumann architecture.
Some addresses must therefore point to RAM and some to flash, so it is a good idea to explore
the memory map next.

BOARD FEATURES:
MCU: MSP430FG4619 with 120K Bytes Program Flash, 256 Bytes data Flash, 4K Bytes
RAM
NOKIA 6610 LCD 128x128 pixels 12 bit color LCD with backlight
Joystick with 4 directions and push button function
two buttons
SD/MMC card connector
MMA7620 3 axis accelerometer
IrDA transceiver
UEXT connector which allow other Olimex's modules to be connected like: MOD-MP3, MODNRF24L01, etc.
JTAG connector
32 768 Hz oscillator crystal
8Mhz crystal oscillator
power supply voltage regulators and filtering capacitor
extension headers for all uC pins
Battery holder for 2 x 1.5 V AA batteries
PCB: FR-4, 1.5 mm (0,062"), soldermask, white silkscreen component print
Dimensions: 81.20 x 62.48 mm (3.20 x 2.46")

PROCESSOR FEATURES:
MSP430-4619LCD board use mixed signal microcontroller MSP430FG4619 from Texas
Instruments, with these features:

Low Supply-Voltage Range, 1.8 V to 3.6 V

Ultralow-Power Consumption:
Active Mode: 350 A at 1 MHz, 2.2 V
Standby Mode: 1.1 A
Off Mode (RAM Retention): 0.3 A
Five Power Saving Modes
Wake-Up From Standby Mode in less than 6 s
16-Bit RISC Architecture, Extended Memory, 125-ns Instruction Cycle Time
Three Channel Internal DMA
12-Bit A/D Converter With Internal Reference, Sample-and-Hold and Autoscan Feature
Three Configurable Operational Amplifiers
Dual 12-Bit D/A Converters With Synchronization
16-Bit Timer_A With Three Capture/Compare Registers
16-Bit Timer_B With Seven Capture/Compare-With-Shadow Registers
On-Chip Comparator
Supply Voltage Supervisor/Monitor With Programmable Level Detection
Serial Communication Interface (USART1), Select Asynchronous UART or Synchronous SPI
by Software Universal Serial Communication Interface
Enhanced UART supporting auto
-baudrate detection
IrDA Encoder and Decoder
Synchronous SPI
I2CTM Serial Onboard Programming, No External Programming Voltage Needed
Programmable Code Protection by Security Fuse
Brownout Detector
Basic Timer with Real Time Clock Feature
Integrated LCD Driver up to 160 Segments With Regulated Charge Pump
120KB+256B Flash Memory
4KB RAM

2.2 ARCHITECTURE
Introduction The types of devices such as microprocessor, microcontroller, processor, digital
signal processor (DSP), amongst others, in a certain manner, are related to the same device the
ASIC (Application Specific Integrated Circuit). Each processing device executes instructions,
following a determined program applied to the inputs and shares architectural characteristics
developed from the first microprocessors created in 1971. In the three decades after the
development of the first microprocessor, huge developments and innovations have been made in
this engineering field. Any of the terms used at the beginning of this section are correct to define
a microprocessor, although each one has different characteristics and applications. The definition
of a microcontroller is somewhat difficult due to the constantly changing nature of the silicon
industry. What we today consider a microcontroller with medium capabilities is several orders of
magnitude more powerful, than the computer used on the first space missions. Nevertheless,
some generalizations can be made as to what characterizes a microcontroller. Typically,
microcontrollers are selected for embedded systems projects, i.e., control systems with a limited
number of inputs and outputs where the controller is embedded into the system. The
programmable SoC (system-on-chip) concept started in 1972 with the 4-bit TMS1000
microcomputer developed by Texas Instruments (TI), and in those days it was ideal for
applications such as calculators and ovens. This term was changed to Microcontroller Unit
(MCU), which was more descriptive of a typical application. Nowadays, MCUs are at the heart
of many physical systems, with higher levels of integration and processing power at lower power
consumption.
The following list presents several qualities that define a microcontroller:
Cost: Usually, the microcontrollers are high-volume, low cost devices
Clock frequency: Compared with other devices (microprocessors and DSPs), microcontrollers
use a low clock frequency. Microcontrollers today can run up to 100 MHz/ 100 Million
Instructions Per Second (MIPS)
Power consumption: orders of magnitude lower than their DSP and MPU cousins Bits: 4 bits
(older devices) to 32 bits devices
Memory: Limited available memory, usually less than 1 MByte Input/Output (I/O): Low to
high (8-150) pin-out count.

Main characteristics of a MSP430 microcontroller

Although there are variants in devices in the family, a MSP430 microcontroller can be
characterized by: Low power consumption:
A for RAM data retention
A for real time clock mode operation
0.8 A/MIPS at active operation. 250
Low operation voltage (from 1.8 V to 3.6 V).
1.
2.
3.

1 < s clock start-up.1

< 50 nA port leakage. Zero-power Brown-Out Reset (BOR).
On-chip analogue devices:
10/12/16-bit Analogue-to-Digital Converter (ADC)
12-bit dual Digital-to-Analogue Converter (DAC)
Comparator-gated timers Operational Amplifiers (OP Amps)
Supply Voltage Supervisor (SVS).

2.2.1 16 bit RISC CPU:

Instructions processing on either bits, bytes or words

Compact core design reduces power consumption and cost
Compiler efficient
27 core instructions
7 addressing modes
Extensive vectored-interrupt capability.

2.2.2 Flexibility:

Up to 256 kB In-System Programmable (ISP) Flash

Up to 100 pin options
USART, I2C, Timers
LCD driver
Embedded emulation

The microcontrollers performance is directly related to the 16-bit data bus, the 7 addressing
modes and the reduced instructions set, which allows a shorter, denser programming code for
fast execution. These microcontroller families share a 16-bit CPU (Central Processing Unit) core,
RISC1 type, intelligent peripherals, and flexible clock system that interconnects using a Von
Neumann2 common memory address bus (MAB) and memory data bus (MDB) architecture.
Figure 4-2. MSP430 architecture.

2.3 Address space

All memory, including RAM, Flash/ROM, information memory, special function
registers (SFRs), and peripheral registers are mapped into a single, contiguous address space as
shown in Figure 43. Note: See the device-specific datasheets for specific memory maps. Code
access is always performed on even addresses. Data can be accessed as bytes or words.
The MSP430 is available with either Flash or ROM memory types. The memory type is
identified by the letter immediately following MSP430 in the part numbers. Flash devices:
Identified by the letter F in the part numbers, having the advantage that the code space can be
erased and reprogrammed. ROM devices: Identified by the letter C in the part numbers. They
have the advantage of being very inexpensive because they are shipped pre-programmed, which
is the best solution for high-volume designs.
Figure 4-3. Memory Map.

For all devices, each memory location is formed by 1 data byte. The CPU is capable of
addressing data values either as bytes (8 bits) or words (16 bits). Words are always addressed at
an even address, which contain the least significant byte, followed by the next odd address,
which contains the most significant byte. For 8-bit operations, the data can be accessed from
either odd or even addresses, but for 16-bit operations, the data values can only be accessed from
even addresses.
2.3.1 Interrupt vector table
The interrupt vector table is mapped at the very end of memory space (upper 16 words of
Flash/ROM), in locations 0FFE0h through to 0FFFEh (see the device-specific datasheets). The
priority of the interrupt vector increases with the word address.

2.3.2 Flash/ROM
The start address of Flash/ROM depends on the amount of Flash/ROM present on the device.
The start address varies between 01100h (60k devices) to 0F800h (2k devices) and always runs

to the end of the address space at location 0FFFFh. Flash can be used for both code and data.
Word or byte tables can also be stored and read by the program from Flash/ROM. All code,
tables, and hard-coded constants reside in this memory space.
2.3.3 Information memory (Flash devices only)
The MSP430 flash devices contain an address space for information memory. It is like an
onboard EEPROM, where variables needed for the next power up can be stored during power
down. It can also be used as code memory. Flash memory may be written one byte or word at a
time, but must be erased in segments. The information memory is divided into two 128-byte
segments. The first of these segments is located at addresses 01000h through to 0107Fh
(Segment B), and the second is at address 01080h through to 010FFh (Segment A). This is the
case in 4xx devices. It is 256 bytes (4 segments of 64 bytes each) in 2xx devices.
2.3.4 Boot memory (Flash devices only)
The MSP430 flash devices contain an address space for boot memory, located between addresses
0C00h through to 0FFFh. The bootstrap loader is located in this memory space, which is an
external interface that can be used to program the flash memory in addition to the JTAG. This
memory region is not accessible by other applications, so it cannot be overwritten accidentally.
The bootstrap loader performs some of the same functions as the JTAG interface (excepting the
security fuse programming), using the TI data structure protocol for UART communication at a
fixed data rate of 9600 baud.
2.3.5 RAM RAM always starts at address 0200h. The end address of RAM depends on the
amount of RAM present on the device. RAM is used for both code and data.
2.3.6 Peripheral Modules
Peripheral modules consist of all on-chip peripheral registers that are mapped into the address
space. These modules can be accessed with byte or word instructions, depending if the peripheral
module is 8-bit or 16-bit respectively. The 16-bit peripheral modules are located in the address
space from addresses 0100 through to 01FFh and the 8-bit peripheral modules are mapped into
memory from addresses 0010h through to 00FFh.
2.3.7 Special Function Registers (SFRs)
Some peripheral functions are mapped into memory with special dedicated functions. The
Special Function Registers (SFRs) are located at memory addresses from 0000h to 000Fh, and
are the specific registers for:

 Interrupt enables (locations 0000h and 0001h)

Interrupt flags (locations 0002h and 0003h)
Enable flags (locations 0004h and 0005h)
SFRs must be accessed using byte instructions only. See the device specific data sheets for the
applicable SFR bits.
2.4 Central Processing Unit (MSP430 CPU)
The RISC type architecture of the CPU is based on a short instruction set (27 instructions),
interconnected by a 3-stage instruction pipeline for instruction decoding. The CPU has a 16-bit
ALU, four dedicated registers and twelve working registers, which makes the MSP430 a high
performance microcontroller suitable for low power applications. The addition of twelve
working general purpose registers saves CPU cycles by allowing the storage of frequently used
values and variables instead of using RAM. The orthogonal instruction set allows the use of any
addressing mode for any instruction, which makes programming clear and consistent, with few
exceptions, increasing the compiler efficiency for high-level languages such as C.
Figure 4-4. MSP430 CPU block diagram

2.4.1 Arithmetic Logic Unit (ALU)

The MSP430 CPU includes an arithmetic logic unit (ALU) that handles addition, subtraction,
comparison and logical (AND, OR, XOR) operations. ALU operations can affect the overflow,
zero, negative, and carry flags in the status register.
2.4.2 MSP430 CPU registers
The CPU incorporates sixteen 16-bit registers:
Four registers (R0, R1, R2 and R3) have dedicated functions
There are 12 working registers (R4 to R15) for general use.
R0: Program Counter (PC)
The 16-bit Program Counter (PC/R0) points to the next instruction to be read from memory and
executed by the CPU. The Program counter is implemented by the number of bytes used by the
instruction (2, 4, or 6 bytes, always even). It is important to remember that the PC is aligned at
even addresses, because the instructions are 16 bits, even though the individual memory
addresses contain 8-bit values.
R1: Stack Pointer (SP)
The Stack Pointer (SP/R1) is located in R1. 1st: stack can be used by user to store data for later
use (instructions: store by PUSH, retrieve by POP) 2nd: stack can be used by user or by
compiler for subroutine parameters (PUSH, POP in calling routine addressed via offset
calculation on stack pointer (SP) in called subroutine) 3rd: used by subroutine calls to store the
program counter value for return at subroutine's end (RET) 4th: used by interrupt - system stores
the actual PC value first, then the actual status register content (on top of stack) on return from
interrupt (RETI) the system get the same status as just before the interrupt happened (as long as
none has changed the value on TOS) and the same program counter value from stack.
R2: Status Register (SR)
The Status Register (SR/R2) stores the state and control bits. The system flags are changed
automatically by the CPU depending on the result of an operation in a register. The reserved bits
of the SR are used to support the constants generator. See the device-specific data sheets for
more details.

R2/R3: Constant Generator Registers (CG1/CG2)

Depending of the source-register addressing modes (As) value, six commonly used constants can
be generated without a code word or code memory access to retrieve them. This is a very
powerful feature, which allows the implementation of emulated instructions, for example, instead
of implementing a core instruction for an increment, the constant generator is used.

R4 - R15: GeneralPurpose Registers

These general-purpose registers are used to store data values, address pointers, or index values
and can be accessed with byte or word instructions.
2.5 Central Processing Unit (MSP430X CPU)
2.5.1 Main features of the MSP430X CPU architecture

The MSP430X CPU extends the addressing capabilities of the MSP430 family beyond 64 kB to
1 MB. To achieve this, there are some changes to the addressing modes and two new types of
instructions. One type of new instructions allows access to the entire address space, and the other
is designed for address calculations. The MSP430X CPU address bus is 20 bits, but the data bus
is still 16 bits. The CPU supports 8-bit, 16-bit and 20-bit memory accesses. Despite these
changes, the MSP430X CPU remains compatible with the MSP430 CPU, having a similar
number of registers. A block diagram of the MSP430X CPU is shown in the figure below:
Figure 4-5. MSP430X CPU block diagram.

Although the MSP430X CPU structure is similar to that of the MSP430 CPU, there are some
differences that will now be discussed. With the exception of the status register SR, all
MSP430X registers are 20 bits. The CPU can now process 20-bit or 16-bit data.
2.5.2 MSP430X CPU registers

 R0 (PC) - Program Counter

Has the same function as the MSP430 CPU, although now it has 20 bits.
R1 (SP) - Stack Pointer
Has the same function as the MSP430 CPU, although now it has 20 bits.
R2 (SR) - Status Register
Has the same function as the MSP430 CPU, but still only has 16 bits.
2.6 Addressing modes
The MSP430 supports seven addressing modes for the source operand and four addressing
modes for the destination operand (see Table 4-5). The following sections describe each of the
addressing modes, with a brief description, an example and the number of CPU clock cycles
required for an instruction, depending on the instruction format and the addressing modes used.

2.6.1 Register Mode

Register mode operations work directly on the processor registers, R4 through R15, or on special
function registers, such as the program counter or status register. They are very efficient in terms
of both instruction speed and code space.
Description: Register contents are operands.
Source mode bits: As = 00 (source register defined in the opcode).

Destination mode bit: Ad=0 (destination register defined in the opcode).

Syntax: Rn. Length: One or two words.
Comment: Valid for source and destination.
Example 1: Move (copy) the contents of source (register R4) to destination (register R5).
Register R4 is not affected.
Before operation: R4=A002h R5=F50Ah PC = PCpos
Operation: MOV R4, R5
After operation: R4=A002h R5=A002h PC = PCpos + 2
The first operand is in register mode and depending on the second operand mode, the cycles
required to complete an instruction will differ. Table 4-7 shows the cycles required to complete
an instruction, depending on the second operand mode.

2.6.2 Indexed mode

The Indexed mode commands are formatted as X(Rn), where X is a constant and Rn is one of the
CPU registers. The absolute memory location X+Rn is addressed. Indexed mode addressing is
useful for applications such as lookup tables.
Description: (Rn + X) points to the operand. X is stored in the next word.
Source mode bits: As = 01 (memory location is defined by the word immediately following the
opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the
opcode).

Syntax: X(Rn).
Length: Two or three words.
Comment: Valid for source and destination.
Example 2: Move (copy) the contents at source address (F000h + R5) to destination (register
R4).
Before operation: R4=A002h R5=050Ah Loc:0xF50A=0123h
Operation: MOV F000h(R5), R4
After operation: R4=0123h R5=050Ah Loc:0xF50A=0123h

2.6.3 Symbolic mode

Symbolic mode allows the assignment of labels to fixed memory locations, so that those
locations can be addressed. This is useful for the development of embedded programs.
Description: (PC + X) points to the operand. X is stored in the next word. Indexed mode X(PC)
is used.
Source mode bits: As = 01 (memory location is defined by the word immediately following the
opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the
opcode).
Syntax: ADDR.
Length: Two or three words.
Comment: Valid for source and destination.
Example 3: Move the content of source address XPT (x pointer) to the destination address YPT
(y pointer).

Before operation: XPT=A002h Location YPT=050Ah

Operation: MOV XPT, YPT
After operation: XPT= A002h Location YPT=A002h

2.6.4 Absolute mode

Similar to Symbolic mode, with the difference that the label is preceded by &.
Description: The word following the instruction contains the absolute address. X is stored in the
next word. Indexed mode X(SR) is used.
Source mode bits: As = 01 (memory location is defined by the word immediately following the
opcode).
Destination mode bit: Ad=1 (memory location is defined by the word immediately following the
opcode).
Syntax: &ADDR.
Length: Two or three words.
Comment: Valid for source and destination.
Example 4: Move the content of source address XPT to the destination address YPT.
Before operation: Location XPT=A002h Location YPT=050Ah
Operation: MOV &XPT, &YPT
After operation: Location XPT= A002h Location YPT=A002h

2.6.5 Indirect register mode

The data word addressed is located in the memory location pointed to by Rn. Indirect mode is
not valid for destination operands, but can be emulated with the indexed mode format 0(Rn).
Description: Rn is used as a pointer to the operand.
Source mode bits: As = 10.
Syntax: @Rn.
Length: One or two words.
Comment: Valid only for source operand. The substitute for destination operand is 0(Rn).
Example 5: Move the contents of the source address (contents of R4) to the destination (register
R5). Register R4 is not modified.
Before operation: R4=A002h R5=050Ah Loc:0xA002=0123h
Operation: MOV @(R4), R5
After operation: R4= A002h R5=0123h Loc:0xA002=0123h

2.6.6 Indirect auto increment mode

Similar to indirect register mode, but with indirect auto increment mode, the operand is
incremented as part of the instruction. The format for operands is @Rn+. This is useful for
working on blocks of data.
Description: Rn is used as a pointer to the operand. Rn is incremented afterwards by 1 for byte
instructions and by 2 for word instructions.
Source mode bits: As = 11.
Syntax: @Rn+.
Length: One or two words.
Comment: Valid only for source operand. The substitute for destination operand is 0(Rn) plus
second instruction INCD Rn.
Example 6: Move the contents of the source address (contents of R4) to the destination (register
R5), then increment the value in register R4 to point to the next word.
Before operation: R4=A002h R5=050Ah Loc:0xA002=0123h
Operation: MOV @R4+, R5
After operation: R4= A004h R5=0123h Loc:0xA002=0123h

2.6.7 Immediate mode

Immediate mode is used to assign constant values to registers or memory locations.
Description: The word following the instruction contains the immediate constant N. Indirect
autoincrement mode @PC+ is used.

Source mode bits: As = 11.

Syntax: #N.
Length: Two or three words. It is one word less if a constant in CG1 or CG2 can be used.
Comment: Valid only for source operand.
Example 7: Move the immediate constant E2h to the destination (register R5).
Before operation: R4=A002h R5=050Ah
Operation: MOV #E2h, R5
After operation: R4= A002h R5=00E2h

2.7 Instruction Set

The instructions are thoroughly documented in the section RISC 16-Bit CPU of the family
users guides. The MSP430 has 27 native instructions, and a further 24 emulated instructions are
defined to make life easier for the programmer. These include common operations such as
clear, which is implemented as an ordinary move with a value of 0 provided by the constant
generator. I list all instructions for completeness but concentrate on the unusual features and
traps for the unwary. The instruction set is orthogonal with few exceptions, meaning that all
addressing modes can be used with all instructions and registers. I show the .w form for
operations that can use either bytes or words. Aside: It sounds as though the MSP430 has fewer
instructions than the PIC16 with 35, but trivial comparisons of radically different processors are
always misleading. It might be more accurate to say that the PIC has 28 instructions with up to
three addressing modes. For example, the operand for arithmetic and logic instructions can be a
literal value, taken from a register whose address is given explicitly, or in a register whose
address is specified indirectly in FSR.

2.7.1 Movement Instructions

There is only the one mov instruction to move data. It can address all of memory as either source
or destination, including both registers in the CPU and the whole memory map. This is an
excellent feature. Some processors have distinct instructions for loading a CPU register from
memory, storing it to memory, and memory-to-memory moves if these are available at all:
mov.w src ,dst ; move (copy) dst = src
Note the order of the operands, which is the opposite of the equivalent statement in C (and some
other assembly languages).
Peculiarity: The status bits are not affected by mov. Strings in C end with the null character \0
and other lists are often terminated by 0, so it would be helpful to detect this. The Z flag is
affected by the move itself in many processors but an explicit test must be used in the MSP430.
Stack Operations
These push data onto the stack and pop them off, as described in the section Stack Pointer (SP)
on page 120:
push.w src ; push data onto stack *--SP = src
pop.w dst ; pop data off stack dst = *SP++ emulated
The SP is fixed to be even, so a word of stack space is always consumed, even if only a byte is
added. The pop operation is emulated using postincrement addressing but push requires a special
instruction because predecrement addressing is not available.
2.7.2 Arithmetic and Logic Instructions with Two Operands
Binary Arithmetic Instructions with Two Operands
These are fairly standard. The carry bit should be interpreted as not borrow for subtraction:

The compare operation cmp is the same as subtraction sub except that only the bits in SR are
affected the result is not written back to the destination. There are many examples of operations
on more than one word with the carry/borrow bit in Section 5.1 of Application Reports (slaa024).
Maxfield and Brown [37] give an entertaining account of binary arithmetic.
Arithmetic Instructions with One Operand
All these are emulated, which means that the operand is always a destination:

The test operation is the special case of comparison with 0. In many processors the clear
operation differs from a move with the value 0 because a move sets the flags but a clear does not.
This does not apply to the MSP430 because a move does not set the flags.
Decimal Arithmetic
These instructions are used when operands are binary-coded decimal (BCD) rather than ordinary
binary values. This means that the value of each nibble is restricted to the range of unsigned,
decimal integers 09 instead of the full hexadecimal range 0F. BCD is often used for values to
be displayed in decimal form because it saves having to convert the binary value to a set of
decimal digits. This is useful in a clock, for instance, as we see in the section Simple
Applications of the LCD on page 264. Maxfield has several articles explaining why BCD is
important and how to use iteven signed BCD [60, 63]:

There is only one native instruction for decimal arithmetic, dadd. This adds its source plus the
carry bit decimally to its destination. The result is a BCD number provided that the operands
were valid BCD numbers themselves. Some processors have a decimal adjust instruction
instead, which converts the value in a register from binary to BCD. The emulated instruction
dadc adds only the carry bit decimally to the destination. The CPU itself provides no other
operations on nibbles, but there are routines for converting between BCD and binary numbers in
Section 5.5 of Application Reports (slaa024) and I show an example in the section Conversion
from Binary to Binary-Coded Decimal on page 270. Peculiarity: The mnemonic dadd is
misleading: It would better have been called daddc for decimal add with carry. Make sure that

you set or clear the carry bit before using dadd unless the carry has been determined by a
previous operation.
Logic Instructions with Two Operands
These are not quite the same as in many other processors:

The MSP430 has the usual and and exclusive-OR xor instructions but not an explicit inclusiveOR. The and and bitwise test operations are identical except that bit is only a test and does not
change its destination.
Peculiarity: The Z bit is affected in the usual way by these operations and the carry bit is given
by C = Z. The idea of this is that the carry bit can subsequently be rotated into another register
to ease serialparallel conversion.
The bit set bis and bit clear bic instructions are used with masks to set and clear bits. The bis
operation is very similar to inclusive-OR and bic mask is likewise related to and mask.
Peculiarity: The bis and bic operations do not affect the status bits. Therefore bis is not quite a
substitute for the usual inclusive-OR, which would be expected to affect SR. This is not a serious
loss because the effect of an inclusive-OR operation on the status bits is largely predictable. Bit
operations are called readmodifywrite operations because the CPU cannot operate on bits
individually: It must read the register into the ALU, perform the operation, and write the result
back. This can have unwanted side effects with some special registers. One example is registers
associated with interrupts, where a read may automatically clear flags. Trouble can also arise
with input/output ports in some processors but this is not a problem on the MSP430 with its
separate input and output registers.
Logic Instructions with One Operand
There is only one of these, the invert inv instruction, also known as ones complement, which
changes all bits of 0 to 1 and those of 1 to 0:
inv.w dst ; invert bits dst = dst emulated
It is emulated using xor and inherits its peculiarity C = Z. Its operand is a destination. It is not
the same as changing the sign of a number, which is the twos complement.

Byte Manipulation
These instructions do not need a suffix because the size of the operands is fixed:
swpb src ; swap upper and lower bytes (word only)
sxt src ; extend sign of lower byte (word only)
The swap bytes instruction swpb swaps the two bytes in a word there is no corresponding swap
nibbles for the nibbles in a byte. The sign extend instruction sxt is used to convert a signed byte
into a signed word. It copies the value of bit 7, which gives the sign of the lower byte, into bits
815 and gives flags C = Z. The opposite operation, truncation from a word to a byte, can be
done with mov.b. Multiplication, if present in hardware at all, is performed by a peripheralit is
not implemented in the ALU and does not appear in the instruction set. There are routines for
methods are given in the application note Efficient Multiplication and Division Using MSP430
(slaa329).
Operations on Bits in Status Register
There is a set of emulated instructions to set or clear the four lowest bits in the status register,
those that can be masked using the constant generator: multiplication in software in Section 5.1
of Application Reports (slaa024). Further

The carry bit should be set or cleared before instructions that take it as input unless it is a result
of a previous operation. This applies to adc, addc, sbc, subc, dadc, dadd (particularly easy to
forget because of the mnemonic), and the rotations rlc and rrc. The GIE flag affects only
maskable (general) interrupts see the section Interrupts on page 186.
2.7.2 Shift and Rotate Instructions
Processors often offer three types of shifts and rotations as illustrated in Figure 5.4, although the
treatment of the carry bit varies. They differ in the treatment of the bits that are shifted out of and
into the register:
Logical shift inserts zeroes for both right and left shifts.
Arithmetic shift inserts zeroes for left shifts but the most significant bit, which carries the sign,
is replicated for right shifts.

Rotation does not introduce or lose any bits bits that are moved out of one end of the register
are passed around to the other.
Usually the carry bit is included in rotations and it may gain the bit that is shifted out by
arithmetic or logical shifts.
The MSP430 has arithmetic shifts and rotations, all of which use the carry bit. The right-shifts
are native instructions but the left shifts are emulated, so the left- and right-shifts have different
addressing modes available:

Peculiarities: The mnemonics for the arithmetic shifts imply that they are rotations, which is
misleading. There are no logical shifts in the MSP430 but they have been added to the
MSP430X. A logical shift left is the same as an arithmetic shift left so there is no problem there.
A logical shift right can be emulated by first clearing the carry bit and making a rotation right.
The rotation operation is not available in C so assembly language may be needed if this
instruction is critical. Shifts in C are always logical for unsigned values but the nature of shifts
for signed values is undefined. They are arithmetic in EW430 to match the instruction set.
Multiword shifts can be constructed using the carry bit in much the same way as multiword
arithmetic.
2.7.3 Flow of Control
Subroutines, Interrupts, and Branches
These are mainly straightforward but there is a tricky point about addresses:

Peculiarity: Both br and call can use the full range of addressing modes for a source. The most
common elementary use of call is for a subroutine that begins at a particular label. This label is
translated by the assembler to the address of the first instruction in the subroutine: direct
addressing. This is the value that should be loaded into the PC to call the subroutine and is
therefore like immediate data. It must consequently be given the prefix # like any other
immediate value. For example, call #DelayTenths. This is very easy to forget.We used this in the
section Automatic Control: Use of Subroutines on page 99 and I will remind you of this pitfall
again. The behavior is easier to understand with br, which is emulated. The instruction br label is
translated into mov.w label,PC. This means that label is used as an absolute address so the
contents of the word whose address is label are fetched and loaded into PC. It is more likely that
we want to load the value label itself into the PC, which needs mov.w #label,PC. The call
instruction must be handled in the same way. There is no problem with the jump instructions
because they use offsets rather than full addresses and the compiler or assembler calculates these
automatically. The good side to this is that it is easy to select a branch or subroutine from a table
by using indexed, indirect, or even autoincrement addressing. The interrupt handling for
Timer_A is designed with this in mind. Be sure that subroutines end with ret and interrupt service
routines end with reti the extra letter is crucial. The MSP430X uses calla and reta for
subroutines. The standard no-operation instruction nop is emulated to waste one cycle of the
processor. There are further suggestions in the family users guides for instructions to use more
cycles but their side effects may need care.
Jumps, Unconditional and Conditional
The unconditional jump instruction is less tricky:
jmp label ; unconditional jump
The target is a straightforward label: It does not have the peculiarity (or versatility) of br. The
difference between them is that:
jmp fits in a single word, including the offset, but its range is limited to about 1KB from the
current location.

br can go anywhere in the address space and use any addressing mode but is slower and requires
an extra word of program storage.
The nomenclature varies between manufacturers jump and branch have the opposite meaning in
Freescale processors, for instance. The symbol $ stands for the current value of the program
counter in the assembler so jmp $ is a concise way of getting an empty, infinite loop.
The conditional jumps are the decision-making instructions and test certain bits or
combinations in the status register. It is not possible to jump according to the value of any other
bits in SR or those in any other register. Typically a bit test instruction bit is used to detect the
bit(s) of interest and set up the flags in SR before a jump. Many branches have two names to
reflect different usage. For example, it is clearer to use jc if the carry bit is used explicitlyafter
a rotation, for instancebut jhs is more appropriate after a comparison:

Both mnemonics jl and jlt are used. It is up to the programmer to select the correct instruction.
For example, suppose that two bytes contain 0x99 and 0x01. They are related by 0x99 > 0x01 if
the values are unsigned but 0x99 < 0x01 if they are signed, twos complement numbers because
0x99 is the representation of 0x67 Peculiarities: There are tests for the conditions < and but
not for nor >. It may be possible to choose the source and destination in a comparison to avoid
this problem. Unfortunately the asymmetric addressing modes often prevent this, particularly if
one value is immediate. Two tests may then be necessary.
2.7.5 Instruction Timing

The number of MCLK cycles required for most instructions is limited by access to memory. This
is a typical feature of a RISC-like CPU with a von Neumann architecture and also applies to the
ARM7, for instance. Values for typical instructions are listed in Table 5.1 but there are several
exceptions, including instructions that change the flow of control and those where the destination
is PC. The general principle for Format I instructions (two operands) is as follows. Most of these
must read the instruction and two operands from memory and write the result back. The duration
is set by the modes used to address memory for the operands.
It takes one cycle to fetch the instruction word itself. This is all if both source and
destination are in CPU registers. Values from the constant generators are effectively in
registers.
One more cycle is needed to fetch the source if it is given indirectly as @Rn or @Rn+, in
which case the address is already in the CPU. This includes immediate data.
Alternatively, two more cycles are needed if one of the indexed modes is used. The first
is to fetch the base address, which is added to the value in a CPU register to get the
address of the source. A second cycle is necessary to fetch the operand itself. This
includes absolute and symbolic modes.

Two more cycles are needed to fetch the destination in the same way if it is indexed.
A final cycle is needed to write the destination back to memory if required no allowance
is needed for a register in the CPU.
These are illustrated in Figure 5.5. It is amusing that no dedicated cycles are needed for the
computation itself. A similar principle applies to the arithmetic operations with a single operand
but most instructions with Format II change the flow of control and have individual timings.
Jumps always use two cycles, whether conditional jumps are taken or not. There is no difference
in the timing between bytes and words so it is pointless to squeeze variables into bytes in the

hope of gaining speed. Of course it is an equally bad idea to waste memory by storing large
tables as words when the elements would fit into bytes.

A few instructions have been speeded up in the MSP430X. These include mov, which does not
need to fetch its destination, and bit and tst, which do not produce a result that needs to be
written back. The number of cycles for these instructions with addressing modes as in mov.w
Rs,D(Rd) has been reduced from four to three. The interfaces to subroutines and interrupt service
routines have also been made faster.
2.7.6 Machine Code
Occasionally you may need to decode the binary machine code to deduce the instruction to be
executed. This is an unfulfilling activity and fortunately is rarely needed with modern debuggers.
The layout of the bits within a Format I instruction (two operands) instruction is shown in

Figure 5.6, taken from the family users guide. These are the individual fields:
opcode (4 bits) is the operation code. The highest 12 values are used for Format I
instructions, the remainder for jumps and Format II.
S-Reg and D-Reg (4 bits each) specify the CPU registers associated with the source and
destination the registers either contain the operands themselves or their contents are used
to form the addresses.
As (2 bits) gives the mode of addressing for the source, which has four basic modes.
Ad (1 bit) similarly gives mode of addressing for the destination, which has only two
basic modes.
B/W (1 bit) chooses whether the operand is a byte (1) or a word (0).
Here is a trivial example of a move from register to register with the resulting machine
code:
mov.w R5 ,R6 ; 4506
The instruction can be broken into its fields of opcode = 4, S-reg = 5, Ad = 0, B/W = 0,
As = 0, D-reg = 6. What do these mean?
The opcode of 4 represents a move.
The bit B/W = 0 shows that the operand is a word.
The addressing mode for the source is As = 0, which is register. The register is S-reg = 5,
which is R5 as expected.
Similarly, the addressing mode for the destination is Ad = 0, which again means register.
The register is D-reg = 6 = R6.
Here is an addition rather than a move:
add.w R5 ,R6 ; 5506
The machine code is identical except for the opcode, which is now 5 rather than 4. The
specification of the operands is unchanged. This is because of the orthogonality: All instructions
use the same addressing modes. Let us move an immediate value instead of a register:
mov.w #5,R6 ; 4036 0005
Now there are two words. The fields of the instruction are opcode = 4, S-reg = 0, Ad = 0, B/W =
0, As = 3 = 11b, D-reg = 6. The difference is in the specification of the source, which means
autoincrement. The register is Sreg = 0, which is the PC. Autoincrement addressing on the PC is

the way in which immediate values are implemented. The value itself is contained in the second
word.
Next look at a value of 4 instead, which can be supplied by the constant generator. I use a byte
rather than a word for a change:
mov.b #4,R6 ; 4266
This breaks into opcode = 4, S-reg = 2, Ad = 0, B/W = 1, As = 2 = 10b, D-reg = 6. The B/W bit
flags a byte rather than a word. The source appears to have indirect register mode on
R2/SR/CG1, but this is translated by the constant generator into a value of 0x0004, as required.
Only a single word is needed for the instruction. Next, let us return to the first three active lines
of Listing 4.3, which were reviewed in the section Machine Code

These are a bit more complicated because the source is given as an absolute address rather than a
register. The first instruction breaks into opcode = 4, S-reg = 0, Ad = 1, B/W = 0, As = 3 = 11b,
D-reg = 2. The source has autoincrement addressing on PC, which means an immediate value.
The destination has Ad = 1, which means indexed. The register is Dreg = 0010b = R2/SR/CG1,
which means absolute addressing (the register acts like a base value of 0). The instruction is
followed by words for the immediate value and absolute address. The third line is very similar
but the B/W bit is set to indicate a byte rather than a word. The second line looks rather different
because the constant generator is used to provide the value of 4, as described earlier.
MSP430 Microcontroller Family
Introduction
The MSP430 is a 16-bit microcontroller that has a number of special features not commonly
available with other microcontrollers:
Complete system on-a-chip includes LCD control, ADC, I/O ports, ROM, RAM, basic
timer, watchdog timer, UART, etc.
Extremely low power consumption only 4.2 nW per instruction, typical
High speed 300 ns per instruction @ 3.3 MHz clock, in register and register
addressing mode

RISC structure 27 core instructions

Orthogonal architecture (any instruction with any addressing mode)
Seven addressing modes for the source operand
Four addressing modes for the destination operand
Constant generator for the most often used constants (1, 0, 1, 2, 4, 8)
Only one external crystal required a frequency locked loop (FLL) oscillator derives all

internal clocks
Full real-time capability stable, nominal system clock frequency is available after
only six clocks when the MSP430 is restored from low-power mode (LPM) 3 no
waiting for the main crystal to begin oscillation and stabilize
The 27 core instructions combined with these special features make it easy to program the
MSP430 in assembler or in C, and provide exceptional flexibility and functionality. For example,
even with a relatively low instruction count of 27, the MSP430 is capable of emulating almost
the complete instruction set of the legendary DEC PDP-11.
MSP430 Family
The MSP430 family currently consists of three subfamilies:
MSP430C31x
MSP430C32x
MSP430C33x
All three are described in detail in the MSP430 Family Architecture Users Guide and Module
Library. The hardware features of the different devices are shown in Table 1, Figure 1, Figure 2,
and Figure 3.

2.8.1 MSP430C31x

2.8.2 MSP430C32x

Figure 12. MSP430C32x Block Diagram

2.8.3 MSP430C33x

2.9 MSP430 Application Operating Modes

MSP430 applications fall into two main classes, depending on the power supply:
AC power-driven applications such as electricity meters and AC-powered controllers. In
these applications, the microcontroller needs to be active at all times. The low current
consumption of the MSP430 when active (900 A @ 5 V & fC = 1 MHz) puts it well

within the typical low-power category now (currently < 40 mA) and in the future as
tolerable current consumption diminishes.
Battery-powered applications such as gas meters, water flow meters, heat volume
counters, data loggers, and other controller and remote metering tasks. For these
applications, power consumption is the key issue since operation from a single battery for
10 years or longer is often required. The average current drawn by the MSP430 needs to
be in the range of the self discharge current of the battery, approximately 1 A to 3 A.
MSP430 has six operating modes, each with different power requirements. Three of these
modes are important for battery-powered applications:
Active mode CPU and other device functions run all the time
Low power mode 3 (LPM3) the normal mode for most applications during 99% to
99.9% of the time. This mode is also called done mode or sleep mode
Low power mode 4 (LPM4) the mode typically used during storage. This mode is also
called off mode
2.9.1 Active Mode
Active mode is used for calculations, decision-making, I/O functions, and other activities that
require the capabilities of an operating CPU. All of the peripheral functions may be used,
provided that they are enabled. The examples shown in this document use the active mode.
2.9.2 Low Power Mode 3 (LPM3)
LPM3 is the most important mode for battery-powered applications. The CPU is disabled, but
enabled peripherals stay active. The basic timer provides a precise time base. When enabled,
interrupts restore the CPU, switch on MCLK, and start normal operation. Table 12 lists the
status of the MSP430 system when in LPM3.

2.9.3 Low Power Mode 4 (LPM4)

Low power mode 4 (LPM4) is used if the absolute lowest supply current is necessary or if no
timing is needed or desired (no change of the RAM content is allowed). This is normally the case
for storage preceding or following the calibration process. Table 3 lists the status of the MSP430
system when in LPM4

Once the MSP430 is waked from LPM4, the software has to decide if it is necessary to either
enter LPM4 again (if the wake-up was caused by EMI, for example), or to enter one of the other
operating modes. To ensure the correct decision is made, a code can be placed on a port that can
be checked by the MSP430 software. Then, the active mode is entered only if this code is
present. The start-up frequency of the DCO is approximately 500 kHz and may last up to 4
seconds until a stable MCLK frequency is reached. To enter the LPM4 the following code is
necessary:

The exit from LPM4 is principally the same as described for LPM3. Interrupt handler software
has to determine if the CPU stays active or if a return to a low power mode is necessary. When
entering the LPM4 the information in control registers SCFI0 and SCFI1 of the system clock
frequency integrator (SCFI) remains stored. If at this time the ambient temperature is high,
SCFI1 contains a relatively high value to compensate the negative temperature coefficient of the
DCO. If the LPM4 is later exited and the ambient temperature is very low, it is possible that the
resulting DCO frequency, based on the value in SCFI1, will be outside of the oscillator range. It
is therefore a good programming practice to set the SCFI control register to a low value before
entering LPM4.