Encounter Workshop 2: What You Will Learn - Partitioning A Design

Working a Partition Design and Saving the Partition Work
Encounter Workshop 2
What you will learn - Partitioning a design
Importing a design
Designing a top level floorplan
Specifying partitions
Creating partition pin guides for partitions
Preparing to commit the partitions
Partitioning and generating pins for partitions
Moving partition pins
Viewing into the partitions
Saving partitioned design to directories
Chip assembly information
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Page 1
For Encounter Version SOC6.20
1.
DTMF Design Information
DTMF information - The design in this workshop is a Dual Tone Multi-Frequency

(DTMF) receiver which is one of the common forms of in-band signaling in a telephone
network. For an example, DTMF signals are generated by a touch tone telephone.
The DTMF design contains almost 6,000 instances, 57 IO pads, and about 6,274 nets.
The netlist format is hierarchical Verilog. It has several clock sources and their
hierarchical net names are:
DMA System Clock:
Serial Port Interface Clock:
Scan Clock:
DTMF_INST/clk
DTMF_INST/spi_clk
scan_clk
The design contains 2 scan chains.

The process used is the Artisan 180 nanometer process technology with 6 layers of metal.
These Artisan library files, such as the timing libraries and LEF, must be downloaded
from the Cadence Learning Management System website.
Workshop overview - Virtual prototyping is used to quickly determine the feasibility of
the DTMF design. The design inputs are the netlist, floorplan, clock sources, and timing
constraints. The process/technology inputs are the physical libraries, timing libraries,
process technology libraries. The design is:
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Imported,
Floorplanned
NanoPlaced
Scan chain optimized
Trial routed
Wire parasitic extracted
Setup timing analyzed
Timing optimized for setup timing
Clock tree synthesized
Hold time analyzed
Timing optimized for close timing
NanoRoute routed
Signal integrity analyzed
Fix violating noisy nets
Page 2
2.
Setting up Encounter and the work directory
Note: The following setting up instruction is the same for Workshop1. If you have
already run Workshop 1, you can skip to section 3. Starting an Encounter Session.
The following is the instruction to setup and use the Encounter design tool. You need to
find the installed Encounter directory to get access to the both the Encounter software and
the DTMF design. The design is located in the <install_dir>/share/fe/gift/tutorials/dtmf
directory.
Checklist a. Locate the Encounter install directory.
b. Create a work directory to run the DTMF design.
c. Login to the Cadence Learning Management System at:
http://learning.cadence.com
Setting the Encounter environment In an UNIX window (shell tool, xterm, or etc.), you must set a path to the installation
directory and set an environment variable for the cdslmd license:
set path=(<install_dir>/tools/bin $path)
setenv LM_LICENSE_FILE
\
<install_dir>/share/license/<cdslmd_lic>
which encounter (to see if the path is set properly?)
Note that this UNIX window becomes the Encounter Console where Encounter
commands are entered and Encounter messages are outputted.
Setting up your work directory for the workshop
This requires three steps.
1) Copying the DTMF design data
Copy all the contents (files and directories) from the ~share/fe/gift/tutorial/ directory to
your work directory. Use the UNIX commands:
mkdir <work_directory_name>
cd <work_directory_name>
cp r <install_dir>/share/fe/gift/tutorials/* .
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2) Downloading the Artisan 180nm libraries

To obtain the libraries, you must login to Learning Management System website at
http://learning.cadence.com. After registering with your name, email address, and your
own password, you can download the libraries.
a) After logging in, make sure you click the Catalog link to display the main catalog of
courses. Look under the Digital IC Design catalog selection for Encounter Silicon
Virtual Prototyping (Flat and Hierarchical) Tutorial Download - v5.2.
b) Click on the Internet Learning Module link which leads you to the Learning Activity
Details page.
c) Click the Enroll link and then OK the Cadence license agreement.
d) Click the Launch link and OK the Artisan license agreement. Then click the download
link for the Artisan libraries. There is no charge for the libraries, but you must accept an
Artisan License Agreement.
e) After downloading the library tar file, move the tar file to your work directory, and
untar (GNU version) the tar file. Now, there are four new sub directories in your work
directory and they are captable, cdb, lef, and lib.
3) Running the DTMF design
Your work directory is complete by copying the design, downloading the Artisan library,
and untaring the library file. Now, you are ready to start an Encounter session.
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3.
Starting an Encounter Session
Make sure you are in the dtmf/work_fe work directory and type:
encounter
Now the Encounter Main Window displays.
Menu
Toolbar
Widget
s
Work directory name and Design

name
Status
Select bar
Selectability
toggles
Design
Views
Tool
Widget
Color
Preference
form
Visibility
toggles
Color
options
Design Display Area
Satellite
window
Displays name of
selected or
queried object
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Auto Query
of object
when enabled
Coordinates of
Number of selected objects cursor location
Page 5
Encounter General Mouse Usage

Left Mouse Button (LMB)
Click Selects/Highlights an object and object properties display in the Attribute
Viewer.
Shift-key + Click Selects or deselects an additional object.
Double Click Opens the Attribute Editor form.
1st Click Start point and 2nd Click End point to move or reshape an object.
Middle Mouse Button (MMB)
Click on an object Displays context pop-up menu.
Right Mouse Button (RMB)
Click-and-Drag Zooms-in the display.
Shift-key + Click-and-Drag Pans display.
Encounter General Binding Keys
Key
Action
Description
b
Bind Key
Opens the Binding Key form.
f
Fit Display
Zooms the display to fit the core area.
g
Group
Moves up the hierarchy on the highlighted instance.
G
Ungroup
Moves down the hierarchy on the highlighted Hinstance.
k
Ruler
Create a ruler.
K
Ruler
Removes last ruler displayed.
q
Attribute
Opens the object attribute editor form on selected object.
v
View DB
View the attributes of highlighted object.
U
Redo
Returns the design to state to last Undo command.
u
Undo
Returns the design to state to previous command.
z
Zoom-in
Zooms in the display, 2x.
Z
Zoom-out
Zooms out the display, 2x.
ArrowsPans
Pans the display in direction of arrow.
Control-a
Align
Opens the Align Instance/Module form to align
horizontally or vertically
Control-d
Deselects
Deselects all selected objects in the design display area
Control-r
Redraws
Redraws the window
Delete
DeletesDeletes the selected instance
Shift
Selects
Allows multiple selections and de-selections of objects.
Space Bar
Focus
Changes the focus of stacked objects
Encounter Auto Query Q Binding Keys
Key
n
p
s
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Action
Focus
Focus
Populates
Description
Changes the focus of stacked objects.
Changes the focus of previous stacked object.
Populates the Edit Route form with the net name and more
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Encounter Edit Route Form Binding Keys

Key + Mouse Button Action
Description
Esc button
Ends
Ends the drawing mode for creating special route.
Delete
DeletesRemoves last point/segment.
Arrows
Moves
Moves the current segment in direction of arrow.
Encounter Binding Key Customization

To display or change the Bind Keys, traverse the Menu Design -> Preferences, and on
the Design tab/page, click the Binding Key button. This displays the Binding Key form.
The b-key will also open this form.
Encounter User Guide and Command Help
Encounter help is available and is displayed by an internet browser. Click the left mouse
button (LMB) on the Help button in the upper right corner of the Encounter Main
Window. This displays the Encounter product documentation.
Context sensitive help is done by clicking (LMB) on the Help button in the individual
forms. This displays the related Encounter User Guide page.
Encounter Command help is available by using the Man pages. Type:
man commandName or
help keyword and a list of commands displays pertaining to the keyword.
Table 1 Help Keywords
analysis
browser
buffer
bump
check
clear
clock
crosstalk
cts
delay
design
display
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domain
eco
filler
fix
floorplan
footprint
group
hier
import
load
noise
partition
place
preference
power
restore
route
save
scan
sdf
select
snap
timing
verify
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4.
Importing the Design
Importing the design - The Design Import form is used to load the Verilog netlist,
physical libraries, process technology libraries, timing libraries, and timing constraints.
Other important items are also loaded during design import and they are contained in the
2 tabs of the Design Import form. Open the Design Import form and make the following
entries.
Form Design -> Design Import
Load The configurations file dtmfLef.conf and examine the entries in the Design
Import form.
Click the OK button when ready to import.
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5.
Floorplanning the Blocks
Changing the die size The die size and aspect ratio need to be changed to
accommodate the 2 partitions and blocks, and this is done in the Specify Floorplan form.
Form Floorplan -> Specify Floorplan
Select Die Size by: Width and Height option and
Enter Core Width: 1623.96
Enter Core Height: 1392.12
Click the Apply button when ready.
Now, make sure the Core to IO Boundary option is selected and
Enter Core to Left: 100
Enter Core to Right: 100
Enter Core to Top: 100
Enter Core to Bottom: 100
Click the OK button when ready.
The die shape is now rectangular and the IO pads are spaced away from the core area.
Pre-placing the block in the floorplan The blocks need to be pre-placed and block
halos added. Since this sequence is similar to the relative floorplanning work done in
Workshop1, a floorplan file is loaded.
Form Design -> Load Floorplan
Select file dtmf_p.block.fp and
Click the Open button after selecting the file.
Now, the blocks along with their halos are placed in the floorplan.
Pre-Placing blocks information In this design, there are 4 large blocks and all
were pre-placed before NanoPlace Placement is run. It is not always
recommended to pre-place all block in a design, especially the small size blocks.
The thinking is to pre-place the blocks that are critical in timing and the large size
blocks such as memories (since the arrangement is known). The NanoPlace
Placement program will place all remaining blocks that were not pre-placed along
with the standard cell instances.
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6.
Floorplanning the Partition Modules
Knowing your partitions Designing a partition floorplan starts with knowing exactly
which modules or submodule that is to become a partition. In the DTMF design, there
are 2 submodules that are to become partitions in the design.
Use the Design Browser to view the 2 submodules and this is done by Tools -> Design
Browser. The hierarchical names of the 2 submodules are:
DTMF_INST/TDSP_CORE_INST and DTMF_INST_ARB_INST.
The DTMF_INST/TDSP_CORE_INST contains all standard cell instances and the
DTMF_INST/ARB_INST module contains a block and 24 standard cell instances.
Pushing down the design hierarchy Make sure the design view is in the Floorplan
view. Now, position the view area so you can see the DTMF_INST module (the large
pink colored top module), and this is done by panning left (left arrow key). Select the
DTMF_INST module by clicking on it, and then, enter the G-key (ungroup) or Hierarchy
Down widget in the Toolbar.
We have pushed down 1 level into the design hierarchy and five submodules are now
visible.
Display preference information The display of submodules that contain few
instance in the floorplan view is controlled by the Display page of the Design ->
Preference form. The default Min. Floorplan Module Size is 100, and this means
that any submodule that contains 100 or more instances (standard cell + block) is
displayed. Note that any submodule that contains one or more blocks, this
submoule will always display, no matter of the value entered.
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Guiding submodules in the floorplan The 2 submodules need to be guided into the
floorplan and this is done with the Move/Resize/Reshape widget in the Tools area. Move
the 2 submodules as in Figure 1 or for a closer view see also Figure 2.
Figure 1 - Sample Partition Floorplan
DTMF_INST/TDSP_CORE_INST
DTMF_INST/ARB_INST and child block
(Note: Keep the Target Utilization (TU=#) around 75%)
Fence density information The TU= #% displayed in the module represents

only the visual design size of the module and does not take into account of
obstruction to placement such as placement blockage, block halo, density screen,
routing blockage, partition cut, and etc. The TU= #% can only be changed by
resizing or reshaping the module guide or by the Attribute Editor. After
specifying the modules to become a partition, then the fence placement density
can be calculated. This will be done later and is most important.
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7.
Specifying the Partitions and Creating Partition Pin Guides
Specifying the submodules as partitions After completing the guiding of the 2

submodules, these submodules need to be specified as partitions. The Specify Partition
form is used.
Form Partition -> Specify Partition
Select the DTMF_INST/TDSP_CORE_INST module (LMB) in the floorplan view,
Click the Selected button, and then
Click the Add/Replace button.
Next,
Select the DTMF_INST/ARB_INST module,
Click the Selected button, and then
Click the Add/Replace button.
Leave the remaining default selection but note the pin constraints that can be assigned.
Note the color change in the 2 submodules. The color has changed from pink to orange
which mean the module guides are now fences. Click on each submodule and view the
Attribute Browser to verify that their Constraint Type is a Fence.
Specifying partition information A module must be first guided in the
floorplan before it can be specified as a partition. This order is important.
Always complete the Specify Partition form before running NanoPlace Placement
program. This is important since the Specify Partition form contains placement
constraints.
Calculating Fence/Region placement density information After resizing or
reshaping a module, and has become a fence, partition or region, make sure to
click the Display/Calculate Effective Utilization widget in the Toolbar (icon with
a percentage sign inside a circle. The utilization value for modules that are a
fence or region is printed in the Encounter console and an EU= #% is displayed
along with the TU value. This utilization value takes into account all obstruction
of placement resources. If the EU value is very close to 1.0, then the physical size
of the module must be increased (reduce the TU= #) or some placement
obstruction objects must be removed. The Display/Calculate Effective Utilization
widget is used at least twice in designing the fences which are to become
partitions. The 2nd use of widget comes after specifying the partition. We will do
this later.
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Displaying the Effective Utilization (EU= #%) Click the Display/Calculate Effective
Utilization % widget, and the EU value will display next the TU value on the 2 fences.
Creating a Partition Pin Guide Adding a Partition Pin Guide is optional. The
Partition Pin Guide is used to create pins for the partitions with user assigned a net name,
a bus name, or a net group name, and the pins are created at a specified location and in
the order specified.
Creating a Net Group In this workshop, we are creating a net group and assign it to a
Partition Pin Guide. There are two ways to create a Net Group. The first way is using
the Edit Net Group form.
Form Edit -> Ediing -> Net Group
Enter Name: group1 and Click the Add/Update button which creates group1 net
group.
Enter Add Nets: *rom_data[8] and Click the Add Nets button.
Enter Add Nets: *p_read and Click the Add Nets button.
Enter Add Nets: *p_addrs[5] and Click the Add Nets button.
Now you should have all three net names listed for group1.
The second way is to use the Encounter commands.
Type the following commands in the Encounter console:
createNetGroup group1
(note: group1 is an user assign name)
addNetToNetGroup group1 DTMF_INST/rom_data\[8\]
addNetToNetGroup group1 DTMF_INST/p_read
addNetToNetGroup group1 DTMF_INST/p_addrs\[5\]
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Creating a Partition Pin Guide The Partition Pin Guide is created in the floorplan.
To create the Partition Pin Guide, click on the Partition Pin Guide widget in the Tools
area, then create a pin guide as shown in Figure 2.
Figure 2 Sample Partition Pin Guide
Partition Pin Guide

Assigning Net Group name to the Partition Pin Guide The Net Group name, group1,
needs to be assigned to the created Partition Pin Guide. This is done by opening the
Attribute Editor form.
To open the Attribute Editor form,
Select the created Partition Pin Guide,
Click the MMB, and
Select the Attribute Editor menu item.
Change Name to group1 and
This completes the partition pin guide work.
Partition Pin Guide information For a vertical pin guide overlapping the
horizontal side of the partition, the partition pins start from left side of the pin
guide, and for a horizontal pin guide overlapping the vertical side of the partition,
the pins start from the bottom side. After committing partition, you should see the
yellow colored pins. To view the pin names, select the yellow pin (turns red) and
note the pin name. Note you may have to hit the Space Bar to get the pin
focused.
This completes the floorplanning exercise.
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8.
Creating Power/Ground Rings and Stripes (optional)
Creating the power and ground for the design for this workshop is optional. If you want
to skip this portion, go to Section 9 Preparing to Partition the Design.
Preparing to create power/ground rings Before designing any power and ground
rings or stripes, the global nets for power and ground must be assigned for the entire
design, and this is done with the Global Net Connections form. From the netlist, the
power pins, tie high pins, and tie low pins need to be connected to power and ground
nets. Also, from the LEF file, the vdd! and gnd! ring pins need to be connected to power
and ground nets. There are 6 sets of entries required and they are shown in the table
below.
Form Floorplan -> Connect Global Nets
For Set 1:
Enter Set 1 from table (follow Figure 3).
Click Add to List button.
Continue for Sets 2 through 6 and when done, the completed form looks like Figure 4.
Click the Apply button when all 6 sets appear in the Connection List.
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Entry
Pin Name(s)
Instance
Basename
Tie High
Tie Low
Apply All
To Global Net
n/s = not selected.
Set 1
VDD
*
Set 2
vdd!
*
Set 3
VSS
*
Set 4
gnd!
*
Set 5
n/s
*
Set 6
n/s
*
n/s
n/s
Selected
VDD
n/s
n/s
Selected
VDD
n/s
n/s
Selected
VSS
n/s
n/s
Selected
VSS
n/s
Selected
Selected
VSS
Selected
n/s
Selected
VDD
Figure 3 - Completed Global Net Connections form for Set 1
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Figure 4 - Completed Global Net Connections form for the 6 Sets
After applying the 6 sets, click the Check button. There should be no warning messages.
Viewing Block Information Notice that once you have completed the Global
Net Connections form, the power and ground rings display their VDD and VSS
net names in the 3 rectangular blocks. The pin names in the LEF file are vdd! and
gnd!.
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Creating power/ground rings Now with the power and ground nets assigned, power
planning can be done. In this design, power and ground rings are added around the core
area and around one of the blocks. Power and ground stripes are also added to the top
level design. The Synthesize Power Plan form is used and this form contains design and
block/IP templates which are used to customize the power rings and stripes. See the
Figure 5 which helps identifies the templates. There are 6 major steps in the following
instruction set.
Figure 5 The Synthesize Power Plan form
Note these buttons:
New template form
Opens an existing template form
Opens Specify template

parameter form
Deletes a template
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The 1st major step is to assign power rings to the pllclk block. Make the following
entries:
Form Power -> Power Planning -> Synthesize Power Plan
Enter Total Average Power (mW): 6.0
Select Use template to create power plan
Select IP
Click New template icon (blank sheet icon) and this opens the Edit Power Plan
Template form.
In the Edit Power Plan Template form,
Click the IP Block tab.
Select pllclk in the IP Block List
In the Block Ring tab,
Select Require Block Ring
Deselect Allow sharing with others
Select Offset and enter 1.0.
In the Layer section,
Select M6/M5 and enter 8.0 for Bit width.
No power stripes are required for the pllclk block and the Stripe tab is skipped
Click the Set button and this both bolds pllclk and changes the color blue in the IP Block
List.
Click the Save As button and this opens the Specify Template Name form.
In the Specify Template Name form,
Enter the Template Name: block. This is the power planning template for the block and
will be used later.
Click the OK button to save pllclk block template work.
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The 2nd major step is to assign power rings and stripes to the entire design. Note that the
Synthesize Power Plan form redisplays after you clicked OK in the last step. Keep this
form displaying since it is used several more times. Make the following entries
In the Synthesize Power Plan form, make the selection changes:
Select Design and
Click New template icon (blank sheet icon) and this opens the Edit Power Plan
Template form.
Select Ring and
Select M6/M5.
Select Stripe and
Select M6.
Note the Illustration window that displays the ring and stripes for the entire design.
Enter Region Name: chip
Enter IP Library Template: block (use the down-arrow stepper).
Click the Add/Modify button to set the ring and stripe specifications.
Click the Save As button and this opens the Specify Template Name form.
In the Specify Template Name form,
Enter Template Name: chip.
Note that this is the power planning template for the entire design including the block.
Click the OK button to save design template work.
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The 3rd major step is to assign power planning options for the rings and stripes. Leave
the Synthesize Power Plan form displaying since it will be used once more. Make the
following entries.
Form Power -> Power Planning -> Edit Power Planinng Option
Click Object: Stripe button.
Select Stripe Breaking in the Options window and note the illustration on the
right side of the form.
Underneath the illustration,
Select Omit stripes inside block rings and
Click the Add/Modify button located above the illustration.
Enter Power Planning Option Set breaking and
Click the Save button.
Click the Close button to close this form.
The 4th major step is to assign rings and stripes options to the chip template, and the
Synthesize Power Plan form is used. Make the following entries:
In the Synthesize Power Plan form (which should be displaying), make sure the template
selection are still Design and the template name is chip.
Click Open template icon (sheet with text icon) and this opens the Edit Power Plan
Template form.
Enter Power Planning Option Set: breaking (use the down-arrow stepper) and
Click the Add/Modify button.
Click the Save button to save the final setting for the power planning template. Note that
you can overwrite the chip template file since the content is being modified.
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The 5th step is to assign the width and space parameters to the ring and stripes for the top
level in the Specify Template Parameter form. Make the following entries:
In the Synthesize Power Plan form (which should be displaying), make sure the template
selection are still Design and the template name is chip.
Click Specify Template Parameter icon (text icon on the far right) and this opens the
Specify Template Parameter form.
Note the left side of the form in the Design section which displays the DTMF power and
ground design according to the preceding template work. By selecting/highlighting
DTMF_CHIP: chip, this allows you to assign the parameters to the rings and stripes. By
selecting DTMF_CHIP/PLLCLK_INST: pllclk, this allows you to view the parameters
assigned by the block template. Make sure that DTMF_CHIP: chip is selected before
making the following entries:
In the Ring section, leave the options deselected and make the following changes:
For Metal6-Metal5,
Change Width to 8.0, Spacing to 1.0, and leave Offset at center.
In the Stripe section, leave the Wire Group deselected since only a single set/group of
power stripes is required and make the following changes:
For Metal6,
Change Width to 8.0, Spacing to 1.0, Offset from auto to 70
Select Pitch and
Change Count/Pitch to 100.
In Configure Template section, make sure 6.0 mW is entered for the Total Power.
The 6th and final step is generating the rings and stripes for the entire design after
entering our specification into the power plan templates. This is done in the Synthesize
Power Plan form. Make the following entries:
In the Synthesize Power Plan form (which should be displaying), make sure the template,
Total Average Power entry is 6 mW, selection are still Design, the template name is
chip.
Click the Apply or the OK button.
Now you should see to power and ground rings and stripe created for the design. You can
ignore the Invalid EM message since no EM limits were entered.
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Routing the power/ground structures To route the remaining power and ground
structure, the SRoute form is used. The SRoute program routes the block pins, pad pins,
pad rings, standard cell pins, and unconnected stripes. For our exercise, power and
ground needs to be routed to the block pins, pad pins, and standard cell pins. Make the
following entries:
Form Route -> Special Route
In the Basic page, make the changes in the Route section to:
Deselect Pad rings and
Use the remaining defaults in the Basic page.
Click the Advanced tab and then click Extension control from the list. Make changes to
2 selections as follows:
In the Primary Connection for: and under Standard Cell Pins and stripe section, change
selection to:
Select None
In the Secondary Connection/Stop (Standard Cell Pins Only) (if the primary connection
fails) section, change selection to:
Select Last cell in the row
No changes are required in the Via Generation tab/page.
Now the block pins are connected, power rings are all connected, and standard cell follow
pins are generated and connected.
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Verifying connectivity and geometry After designing the power and ground for the
design, the connections and geometries can be verified (DRC). These 2 tools are in the
Verify menu. To verify the power and ground connectivity, make the following entries:
Form Verify -> Verify Connectivity
In the Net Type section, make a selection change to:
Select Special only and
Deselect Antenna checking.
Use the remaining defaults..
There are violations markers because of antenna warnings and these warning can be
ignored since these are power and ground.
Identifying violation marker information Open the Verify -> Violation
Browser to display the violations. In this form, you can automatically zoom-in to
display the violation location.
The violation markers are cleared using Verify -> Clear Violation menu item.
To verify the geometries, use the Verify Geometry form and make the following entries:
Form Verify -> Verify Geometry
Use the form defaults which do not check for antenna geometries.
Under the Verify menu, clear the DRC markers if any.
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Editing routes - You can also interactively create or edit power and ground nets by using
the Edit Route form, and to display this form, enter the e-key. To use this form, you
must first change the metal layers and enter the route width and spacing, and click the
Nets tab and enter the power/ground net names, such as VDD and VSS. Click the Pencil
widget (in the Tool Widget menu) to start drawing the power/ground routes and each
click (LMB) allows a change in direction. Double-click the (LMB) in end the route
drawing. The Backspace-key removes the most recent drawn segment. The Undo
widget in the Tool Widget menu completely removes the last drawn route.
Routes can be moved by selecting the segment(s), and then selecting the Move Wires
widget in the Tool Widget menu. The moving of the selected segment is done by 3
mouse clicks (LMB). The first click (cursor is circular shape) selects the segment, the
second click starts the interactive move, and third click places the segment. The Undo
widget in the Tool Widget menu undoes the last move. The are also the Add Via, Cut
Wires, Stretch Wires, and Add Polygon widgets to help in editing routes.
9.
Preparing to Partition (Commit Partition) the Design
Clearing the floorplan (optional) This is an optional step. You can use your designed
floorplan but as an option there is a workshop supplied floorplan file. To use workshop
supplied floorplan file, use Load Floorplan file form otherwise, you can skip this step. .
Loading the floorplan file Make the following entries.
(Optional step)
Form Design -> Load -> Floorplan
Select file dtmf_p.fp and
Click the Open button after selecting the file.
Now you see the loaded floorplan which is a result of combined work in the Learning
Floorplanning and Creating Power/Ground Rings and Stripes sections.
Several important steps before partitioning the design The following steps and checks must
be run in the listed sequence. The 6 steps or checks before actually partitioning the design are:
1.
2.
3.
4.
5.
6.
7.
8.
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Completed floorplanning the modules or submodules that are to be a partition.

Partitions are specified (Specify Partition form).
Check the fence Effective Utilization (EU) value of the partition fences. <- Important!
Run NanoPlace Placement.
Run Trial Route.
Check the routability of the designed floorplan.
Save the floorplan to a file.
Run Partition (Partition form).
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Commit partition information Several things must be checked before

committing partition on a design. The design of the floorplan must be a routable
floorplan and the size of the partition modules must not be too small. The design is
routable by viewing the results of running Trial Route which involves viewing
congestion markers and viewing the log file. The size of the partition fences is
checked by the Display/Calculate Effective Utilization % widget in the Toolbar and
the utilization value for must be less than 1.0, preferably around ~0.85.
Final fence density calculation information - After completing the Specify
Partition form, the Core to Left/Right and Core to Top/Bottom entries are taken into
account as placement blockage. The final EU value must be calculated and the fence
EU values should be around ~0.85. The physical size of the fence is changed to meet
the fence utilization value.
The floorplan that is used to commit partition must be saved to a file. This floorplan
file is used later to assemble the chip after design work is complete for each partition
and the top level.
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Running NanoPlace Placement and Trial Route Before the design can be partitioned,
NanoPlace and Trial Route must be run. Running Trial Route is necessary to create the
pins for the partitions and these partition pins are optimally placed since the routes
determine the pin placement (except for the pin in the Partition Pin Guide).
Before running NanoPlace and Trial Route, use the Placement Blockage form to make
standard cell placement constraints.
Specifying placement blockage under power and ground stripes Open the
Placement Blockage form to specify that no standard cell will be placed under power and
ground stripes. This is to avoid routing congestion that may occur under the power and
ground stripes.
Form Place -> Specify -> Placement Blockage
Select M2
Select M3
Select M4
Select M5
Select M6 options and
Use the Place form to run NanoPlace Placement.
Form Place -> Standard Cells and Blocks
Select Run Full Placement and
Deselect Include Pre-Place Optimization
Click the Mode button to bring up the Placement Mode Setup
Keep the defaults
Click the OK button in both the Mode Setup and Place forms.
Use the Trial Route form to run trial routing.
Note - Another way to run Trial Route is to type trialRoute in the Encounter
console.
Form Route -> Trial Route
Select Prototyping
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10.
Partition the Design and Generate Partition Pins
Saving top level floorplan to a file Before partitioning the design, we need to save the
floorplan to a file. This floorplan file will be used to assemble the entire design after
work is done in each partition and the top level.
Form Design -> Save -> Floorplan
Enter File name of your choice.
Click the Save button when ready.
Now, the design can be partitioned (commit partition) and the Partition form is used.
Form Partition -> Commit Partition
Use the defaults and
Note that the 2 submodules have changed to blocks and pins are generated. To view the
generated the pins, make sure you are in the Floorplan view and zoom (RMB) into the
Partition Pin Guide where it overlaps the partition. Click on the pin to view the name.
You may have to cycle through the objects and this is done with the Space Bar-key.
More on commit partition information In the case where the design has been
partitioned and if there are any changes in the floorplan that involves the partitions,
the design must be flattened. This is done by the Partition -> Unpartition form.
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11.
Move and Edit Partition Pins
Moving selected partition pins Groups of pins may be moved from one edge to another
edge on a partition. To move a few partition pins, follow the instructions:
First, make sure the design is in the Physical view. Then zoom into (RMB) an edge of a
partition and locate some pins.
Select (Shift-key + LMB) a few pins (it is best to select pin with same metal layer).
Click the Move/Resize/Reshape widget.
Click one of the selected pins and a white bounding box appears. Move the mouse and the
pins will follow. You can zoom out (Z-key) so you can view the other edges of the partition.
Enter the F3-key and the Group Pin(s) Move form displays, and this allows changing the
metal layer.
Click the location for the final pin placement.
Pin Editor information The editor can be used to view and modify pin
location, depth, width, and spacing. Also, grouping of pins of a bus, grouping
pins into a group, and assigning pins as fixed can be done. The Pin Editor is
located in the Edit menu.
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12.
Viewing into a Partition
To pushdown into a partition, first select the one of the partitions in the Floorplan view
and then choose Partition -> Change Partition View menu item. Now you are only
viewing in that partition. While viewing the partition, note that the power strips are cut
from the top level floorplan. All floorplan objects that belong to this partition is now part
of the partition.
While down in a partition, the Partition -> Change Partition View will bring you back up
to the top level.
13.
Saving the Partition Work
When the design is partitioned, the design is saved. Make sure to change the partition
view to the top level and use the Save Partition form.
Form Design -> Save -> Partition
Select your choice of Output Format and
Enter A name for the Partition Result Directory: PTN
Select your choice of Timing Constraint Output format and
It is important to see what files are created in the 2 partition directories and the top level
directory. These directories are created under the PTN directory, and these are the
directories for you to do your design work for the 2 partitions and the top level. Now,
change directory (cd) into each of the created directories, and you should see files for the
netlist, floorplan, import configuration, and etc. These files are for Encounter and for
third party tool use.
Save Partition information For a partition design, your work is saved by the
Save Partition form. Do not use the Save Design or Save Floorplan form. The
Save Partition form saves the partition work in separate directories for each
partition and the top level. Saved in these directories are design import files,
floorplan files, and many more files.
Once the partitioned design is saved, exit the Encounter session since this ends the
top-down partition design work. Now, the design work begins for each partition
and the top level design in their individual created directories.
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14.
Partition Chip Assemble Information

Working the partition and top level information This exercise in Workshop 2
demonstrates how to partition a design from the top and then saving the partitions
and top level into created directories. The Save Partition form creates a directory
for each partition and one for the top level. Once these directories are created, the
remaining design work for each partition and the top level is done in their
respective directory. The design work done in each partitioned usually includes
floorplanning, running scan optimization, running clock tree analysis and
generating a clock macromodel, running route, running timing analysis, and
running IPO. The work done in the top level usually includes floorplanning,
running scan optimization, running hierarchical clock tree analysis, running route,
running timing analysis, and running IPO.
When the design work is done with each partition and the top level, make sure to
save the design work with the saveDesign command. The Encounter command
usage is (saveDesign <sessionName> def) for each of the completed
partitions and top level. The next step is to assemble the chip.
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Assembling the chip information (top-down) For our top-down partition

workshop, once the design work is complete for all partitions and top level, then
chip assembly must be done. This work involves using the assembleDesign
command and this command does:
1) Concatenates the Verilog netlist files from the partitions back to the top level
(The partition netlists and top level netlist are changed from the time the save
partition step was done), and merges the partition design data (DEF) to the
original top design level.
2) Now, change directory (cd) to the work directory where the original DTMF
design was partitioned. In our case, the original work directory is work_fe.
3) Start an Encounter session and then use the following assembleDesign
command example for this workshop.
assembleDesign PTN/DTMF_CHIP/DTMF_CHIP.enc.dat
PTN/arb/arb.enc.dat PTN/tdsp_core/tdsp_core.enc.dat
-topFP dtmf_p.fp
Now, you are able to run full chip timing analysis on the entire assembled design.
Assembling the chip information (bottom-up) For a bottom-up chip

assembly, the assembleDesign command can also be used. You must have a
floorplan file for the top design level as in the case for this top-down partition
workshop. The assembleDesign command format is:
assembleDesign <topDesignDir> <blockDesignDir> . -topFP <floorplan.fp>
where
The topDesignDir is the path name from the top design directory to the directory
that contains the top level verilog and DEF files created by the (saveDesign
<sessionName> def) command.
The blockDesignDir is the path name from the top design directory to the
directory that contains the partition verilog and DEF files created by the
(saveDesign <sessionName> def) command. An entry is required for
each partition or block to be assembled.
The floorplan.fp is the top design floorplan file and is required. In this floorplan
file, the blocks to be assembled are block instances in the floorplan. These block
instances are replaced by the verilog and DEF data from the saveDesign
command.
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Encounter Workshop 2: What You Will Learn - Partitioning A Design

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Working a Partition Design and Saving the Partition Work

For Encounter Version SOC6.20

Working a Partition Design and Saving the Partition Work

DTMF Design Information

DTMF information - The design in this workshop is a Dual Tone Multi-Frequency

The design contains 2 scan chains.

For Encounter Version SOC6.20

Working a Partition Design and Saving the Partition Work

Setting up Encounter and the work directory

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2) Downloading the Artisan 180nm libraries

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Starting an Encounter Session

Work directory name and Design

Design Display Area

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Encounter General Mouse Usage

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Encounter Edit Route Form Binding Keys

Encounter Binding Key Customization

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Working a Partition Design and Saving the Partition Work

Importing the Design

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Working a Partition Design and Saving the Partition Work

Floorplanning the Blocks

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Floorplanning the Partition Modules

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Fence density information The TU= #% displayed in the module represents

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Specifying the Partitions and Creating Partition Pin Guides

Specifying the submodules as partitions After completing the guiding of the 2

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Partition Pin Guide

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Creating Power/Ground Rings and Stripes (optional)

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Figure 3 - Completed Global Net Connections form for Set 1

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Figure 4 - Completed Global Net Connections form for the 6 Sets

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Opens Specify template

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Working a Partition Design and Saving the Partition Work

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Working a Partition Design and Saving the Partition Work