International Journal Of Scientific Research And Education

||Volume||2||Issue||12||Pages-2563-2569||December-2014|| ISSN (e): 2321-7545

Website: http://ijsae.in

Fast Multi Bit Flip Flop With Ring Counter Delay Buffer
Authors
Indira Priya Mavya Bolla1, G.Shekar Reddy2., Prof. S.Kishore Babu3
1
VLSI M.Tech student, Vikas Group of Institutions,
2
Asst Professor, Vikas Group of Institutions, Nunna.
3
HOD Dept.of ECE, Vikas Group of Institutions, Nunna.
Email-nunna. applemavya1990@gmail.com, gaddamsekharreddy@gmail.com, kish.fr@gmail.com

ABSTRACT

Keywords: Power, multi bit flip flop, delay

Power has become a burning issue in modern

buffers, merge flip flops.

VLSI design. In modern integrated circuits, the

INTRODUCTION

power consumed by clocking gradually takes a

According to Moores law the number of

dominant part. Given a design, we can reduce its

transistor doubling every eighteen months so

power consumption by replacing some flip-flops

reducing the total power consumption is the major

with fewer multi-bit flip-flops. However, this

issue in modern VLSI design. We know that the

procedure may affect the performance of the

power is directly proportional to area and

original circuit. Hence, the flip-flop replacement

frequency hence the reduction in power can also

without timing and placement capacity constraints

reduce the chip area. Reducing the power

violation becomes a quite complex problem. To

consumption not only can enhance the battery life,

deal with the difficulty efficiently, we have

but also can avoid the overheating problem, which

proposed several techniques. First, we perform a

would increase the difficulty of packaging

co-ordinate transformation to identify those flip

,cooling [2][3]. In modern VLSI design power

flops that can be merged and their legal regions.

consumed by clocking has taken a major part of

Besides, we show how to build a combination

the whole design [4]. Several methodologies [5]

table to enumerate possible combinations of flip-

[6] have been proposed to reduce the power

flops provided by a library. Finally, we use a

consumption of clocking. This paper reduces the

hierarchical way to merge flip-flops with delay

clock power by using the multi bit flip flop. Here

buffers. Besides power reduction, the objective of

several flip-flops can share a common clock to

minimizing

avoid unnecessary power waste. The fig 1 shows

considered.

the

total

wire

length

is

also

the block diagrams of 1 and 2 bit flip-flop. If we

Indira Priya Mavya Bolla et al IJSRE Volume 2 Issue 12 December 2014

Page 2563

replace two 1-bit flip-flop by a 2-bit flip-flop. The

reduce the power consumption. This paper

total power consumption can be reduced because

includes 2, 4, bit multi bit flip-flop as shown in

the two one bit flip-flop can share the same clock

fig.

buffer after the replacement the location of the

flip-flop would be changed. So to find the new
location of the flip-flop coordinate transformation
is used. To minimize the wire length Manhattan
distance is used. Other processes to follow the
same work are coordinate transformation and
Manhattan distance but due to these the system
feasibility is reduced. The area occupied and
power utilization will also increase and the
utilization multiple clocks will set to rise. These

Figure 2: 2 bit flipflop.

are the reasons to move for merging bit flip flops.

The following sections are as follows section II is
all about system and how system is designed,
section III is all about related work for the project
to complete the phase, section IV deals with the
results obtained and comparison graphs for the
power utilized under various flip flops, section V
is all about concluding part of the paper how
paper is designed.
Figure 1: 2 bit flip flop before and after merging.
When a common clock is shared by the several
flip-flops the k-bit flip-flop becomes k-bit multi
bit flip-flop. The use of common clock may

SYSTEM MODEL

Figure 3: 8 bit flip flop with single clock

Indira Priya Mavya Bolla et al IJSRE Volume 2 Issue 12 December 2014

Page 2564

Table 4: Shifting process of the Shift Register Using 8 bit flip flop
A0

A1

A2

A3

A4

A5

A6

A7

Initial States

Clock cycle 1

Clock cycle 2

Clock cycle 3

Clock cycle 4

Clock cycle 5

Clock cycle 6

Clock cycle 7

Clock cycle 8

A Register is a device for storing data in Digital

as the input area or input block. When referring to

Circuits. The Register is a collection of two or

computer memory, the input buffer is a location

more Flip-flops with a common CLOCK input.

that holds all incoming information before it

Registers are often used to store a collection of

continues to the CPU for processing. Input buffer

related bits, such as a byte of data in a computer.

can be also used to describe various other

A Shift Register is a Multi-bit Register, which

hardware or software buffers used to store

shifts its stored data by one bit position at each

information before it is processed. Some scanners

CLOCK transition. In the Shift Register, a group

(such as those which support include files)

of Flip-flops are linked up such that the output of

require reading from several input streams. As

a Flip-flop is connected to the input of the next.

flex scanners do a large amount of buffering, one

As a result, data is shifted down the line when the

cannot control where the next input will be read

CLOCK is activated.

from by simply writing a YY_INPUT() which is

For a 8 Bit Shift Register, at every CLOCK

sensitive to the scanning context. YY_INPUT() is

transition from L to H, the Shift Register reads

only called when the scanner reaches the end of its

input DATA and transfers it to output A0. Each

buffer, which may be a long time after scanning a

previous value of bit A0 to A6 is shifted to the

statement such as an include statement which

next bit (that is, A0 to A1, A1 to A2, , A6 to

requires switching the input source.

A7), and the value of A7 is shifted out of the

A ring counter is a type of counter composed of a

register. Table 4 illustrates this operation.

circular shift register. The output of the last shift

For a fast approach the system is set with a delay

register is fed to the input of the first register.

circuit. The Input buffer is also commonly known

There are two types of ring counters:

Indira Priya Mavya Bolla et al IJSRE Volume 2 Issue 12 December 2014

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A straight ring counter or Over beck counter

RELATED WORK

connects the output of the last shift register to the

first shift register input and circulates a single one
(or zero) bit around the ring. For example, in a 4register one-hot counter, with initial register
values of 1000, the repeating pattern is: 1000,
0100, 0010, 0001, 1000... . Note that one of the
registers must be pre-loaded with a 1 (or 0) in
order to operate properly.
A twisted ring counter (also called Johnson
counter or Moebius

counter) connects the

complement of the output of the last shift register

Figure 5: Flip Flow Chart.

to its input and circulates a stream of ones

followed by zeros around the ring. For example, in
a 4-register counter, with initial register values of
0000, the repeating pattern is: 0000, 1000, 1100,
1110, 1111, 0111, 0011, 0001, 0000... . If the
output of a shift register is fed back to the input. A
ring counter results. The data pattern contained
within the shift register will re-circulate as long as
clock pulses are applied. For example, the data
pattern will repeat every four clock pulses in the
figure below.

This design flow can be roughly divided into three

stages. In the beginning, we have to identify a
legal placement region for each flip-flop. First, the
feasible

placement

regions

of

flip-flop

associated with different pins are found based on

the timing constraints defined on the pins. Then
the legal placement region of the flip-flop fi can
be obtained by the overlapped area of these
regions. However, because these regions are in the
diamond shape, it is not easy to identify the
overlapped area. Therefore, the overlapped area
can be identified more easily if we can transform
the coordinate system of cells to get rectangular
regions. In the second stage, we would like to
build a combination table, which defines all
possible combinations of flip-flops in order to get
a new multi-bit flip-flop provided by the library.
The flip flops can be merged with the help of the
table. After the legal placement regions of flip-

Figure 4: Delay buffer with ring counter.

flops are found and the combination table is built,

we can use them to merge flip-flops. To speed up
our program, we will divide a chip into several
bins and merge flip-flops in a local bin. However,

Indira Priya Mavya Bolla et al IJSRE Volume 2 Issue 12 December 2014

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the flip-flops in different bins may be mergeable.

Thus, we have to combine several bins into a

Table 1: Comparison of Power consumption

larger bin and repeat this step until no flip flop can

mode

be merged anymore.
Performance plots were plotted showed using the

FLIP
FLOPS

following table and plotted in the results:

1 BIT
2 BIT
4 BIT
8 BIT

POWER
CONSUMPTIO
N USING
SINGLE BIT
FLIP FLOP
0.95
1.9
3.8
7.6

POWER
CONSUMPTION
USING MULTI
BITS FLIP FLOP
0.93
0.93
0.93
0.93

RESULTS
Table 2: Design Synthesis Report.

Figure 6: RTL Schematic

Indira Priya Mavya Bolla et al IJSRE Volume 2 Issue 12 December 2014

Page 2567

P
O
W
E
R

C
O
N
S
U
M
P
T
I
O
N

7
6

POWER
CONSUMPTION
USING SINGLE BIT
FLIP FLOP

5
4
3

POWER
CONSUMPTION
USING MULTI BITS
FLIP FLOP

2
1
0
1 BIT

2 BIT

4 BIT

8 BIT

FLIP FLOP BITS

Figure 7: Power consumption comparison

algorithm can maintain the performance of power

CONCLUSION

and wire length reduction in the reasonable

This paper has proposed an algorithm for flip-flop

processing time.

replacement for power reduction in digital

integrated circuit design. The procedure of flip-

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