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-- FileName: booth_mult.vhd
-- FPGA: Lattice MACHXO2-1200ZE
-- IDE: Lattice Diamond ver 2.0.1
--- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--- Version History
-- Version 1.0 19/11/2012 Tony Storey
-- Initial Public Release
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity booth_mult is
Generic(
W : integer := 18 -- specify mulitiplier width; must be even value
);
port(
clk
: in std_logic;
start
n_reset
: in std_logic;
: in std_logic;
mcand
mplier
done
: out std_logic;
product
);
end booth_mult;
: string;
-- used for explicit state machine encoding
:
-- this holds the result before
begin
sync_update :
process(clk, n_reset)
incriments sequential logic on rising clock edges
-- process to
begin
if rising_edge(clk) then
if n_reset = '0' then
state_reg <= IDLE;
q_reg <= (others => '0');
prod_reg <= (others => '0');
else
q_reg <= q_next;
state_reg <= state_next;
prod_reg <= prod_next(2*W) & prod_next(2*W downto 1);
-- shift prod register each time
control_logic :
process(state_reg, q_reg, result_reg, start, prod_reg, mplier, mcand )
begin
-- init signals and no reg update
q_add <= '0';
q_reset <= '0';
done <= '0';
state_next <= state_reg ;
prod_next <= prod_reg ;
result_next <= result_reg;
case state_reg is
when IDLE =>
if (start = '1') then -- load numbers to multiply
mcand_reg <= mcand;
prod_next(2*W downto W+1) <= (others =>
'0'); -- fill prod_next reg with [0000...0000(mplier)0]
prod_next(W downto 1) <= mplier;
prod_next(0) <= '0';
state_next <= BUSY;
end if;
-- Add Mcand
-- Subtract Mcand
-- Just
end case;
end process;
end arch;