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Tutorial 1 - Introduction to ASIC Design Methodology

ECE-520/ECE-420 ~ Spring 1999 ~ Rev. 99.1


Dr. Paul Franzon, Scott Perelstein, Amber Hurst
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1 Introduction:
Typical ASIC design flow requires several general steps that are perhaps best illustrated using a
process flow chart:
Figure 1: Process Flow Chart
HDL Design Capture
Design Specification

Behavioral Description

RTL Description

RTL
Verification Vectors

Functionality

No

Verified?
Yes

HDL Design Synthesis

RTL to Logic

Constraints

Logic Optimization

Logic to Technology

Constraints

Timing/Area
Optimization

Scan Path Insertion &


Test Vector Generation

Netlist
Logic & Timing

No

Verified?
Yes

Design Implimentation

Floor Planning

Place & Route

Physical Layout

Layout
Function & Timing
Verified?

Yes
Chip Production

No