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DAP018A/B/C/D/F
PWM Current-Mode
Controller for High-Power
Universal Off-Line Supplies
Autorecovery internal output shortcircuit protection
Typical Applications
OPP
OVP
CTimer
Jittering
Fold
FB
14
= Device Version
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbFree Package
DAP018x
AWLYWWG
1
PIN CONNECTIONS
MARKING
DIAGRAM
SOIC14
D SUFFIX
CASE 751A
14
Features
CS
14
13
12
11
10
HV
NC
OTP
BO(B&D)
VCC
DRV
GND
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
DAP018A/B/C/D/F
Vbulk
ROPPU
OVP
ROPPL
+
14
13
12
11
10
*See
Note
+
NC /
A&C
Ramp
Vout
Gnd
*This resistor
prevents from
negatively biasing
the HV pin (14) at
poweroff. Typical
value is 4.7 kW.
+
OTP
Foldback
Adj.
Timer
Delay
Freq.
Jitter
Gnd
Pin No.
Pin Name
Function
Pin Description
OPP
A resistive divider from the auxiliary winding to this pin sets the
OPP compensation level.
OVP
CTimer
Timer
Jitter
Foldback / skip
Frequency foldback /
skip cycle adjustment
By connecting a resistor to ground, it becomes possible to reduce the level at which frequency foldback occurs.
FB
Feedback pin
CS
Current sense +
ramp compensation
This pin monitors the primary peak current but also offers a
means to introduce ramp compensation.
GND
DRV
Driver output
10
VCC
11
BO
12
OTP
NTC connection
This pin connects to a pulldown NTC resistor for over temperature protection (OTP).
13
NC
14
HV
Highvoltage input
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DAP018A/B/C/D/F
ORDERING INFORMATION
ON Semiconductor Device
Frequency
Brown
Out
Short
Circuit
Package
Shipping
DAP018ADR2G
SCY99079ADR2G
65 kHz
No
Auto
Recovery
SOIC14
(PbFree)
DAP018BDR2G
SCY99079BDR2G
65 kHz
Yes
Auto
Recovery
SOIC14
(PbFree)
DAP018CDR2G
SCY99079CDR2G
100 kHz
No
Auto
Recovery
SOIC14
(PbFree)
DAP018DDR2G
SCY99079DDR2G
100 kHz
Yes
Auto
Recovery
SOIC14
(PbFree)
DAP018FDR2G
SCY99079FDR2G
65 kHz
Yes
Latched
SOIC14
(PbFree)
Delta Device
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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DAP018A/B/C/D/F
OPP
Latch
Softstart ended?
Yes = 1, No = 0
+
-
VOTP
+
+
+
Vlatch
20 ms time
constant
from fault
in OCP
latched versions
Timer 3
5 V on
VCC Reset
IpFlag
13 NC
VCC and Logic
Management
5 V reset
VDD
fault
+
-
IC1
B and D versions
VCCON
VCC(min)
VCClatch
turned
off when
BO ok
BO ok
VDD
VDD
Frequency
Modulation
iCjit
+
-
20 ms time
constant
Power On
Reset
Q
Q
Clamp
+
+
Vfold
+
-
Skip
+
-
+
Vskip
5 ms
SS
Rramp
VDD
RFB
+
/4.2
Standby?
bias
reduction
VOPP
/4.2
IpFlag
Vfold
CS
10 VCC
Frequency
Foldback
Ifold
FB
IBO
9 Drv
VDD
Fold
11 BO
VBO
65/100 kHz
Clock
S
2.iCjit
12 OTP
IpFlag
IOTP
BO (dble
hiccup reset)
Power
on reset
BO release
(B & D)
Itim
Jitter
14 HV
Q
Q
Vtimfault
+
VDD
Fault
LEB
Vlimit + VOPP
8
Vlimit
GND
DAP018A/B/C/D/F
MAXIMUM RATINGS TABLE
Symbol
Rating
VCCmax
ICCmax
Value
Unit
0.3 to 28
$30
mA
0.3 to 10
IOPP
mA
RJA
120
C/W
TJMAX
150
60 to +150
kV
180
0.3 to 500
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTES:This device(s) contains ESD protection and exceeds the following tests:
Human Body Model 2000V per JEDEC Standard JESD22A114E
Machine Model 200V per JEDEC Standard JESD22A115A
This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78 except pin 12.
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = 25C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
10
14
15
16
VCC(min)
10
10
VCClatch
10
7.2
7.5
8.0
VCCreset
10
resetHyst
VCCTSD
6.5
ICC1
10
1.9
mA
SUPPLY SECTION
VCCON
ICC1light
0.8
V
7.1
10
1.5
mA
ICC2
10
2.7
mA
ICC3
10
ITSD
0.6
400
mA
mA
Rating
Pin
Min
Typ
Max
Unit
IC2
14
mA
IC1
14
150
650
1200
mA
VTh
14
Ileak
14
15
30
mA
Pin
Min
Typ
Max
Unit
40
ns
0.9
DRIVE OUTPUT
Symbol
Tr
1.
2.
3.
4.
Rating
Output voltage risetime @ CL = 1 nF, 1090% of a 12 V output signal
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DAP018A/B/C/D/F
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = 25C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)
DRIVE OUTPUT
Symbol
Pin
Min
VDRVlow
VDRVhigh
Tf
Isource
Isink
Rating
Typ
Max
Unit
25
ns
500
mA
800
mA
7.6
10
15
17
Pin
Min
Typ
Max
Unit
CURRENT COMPARATOR
Rating
Symbol
IIB
VLimit
TDEL
TLEB
TSS
0.02
0.76
mA
0.8
0.84
100
150
ns
140
ns
ms
IOPPo
37.5
IOOPv
IOPPs
0.46
0.5
0.54
V
%
INTERNAL OSCILLATOR
Symbol
Rating
Pin
Min
Typ
Max
Unit
fOSC
60
65
70
kHz
fOSC
92
100
108
kHz
Dmax
Maximum dutycycle
76
80
84
fjitter
fswing
300
Hz
ICjit
18
mA
VCjitP
2.2
VCjitV
0.8
FEEDBACK SECTION
Rating
Symbol
Rup
RFB
Iratio
Pin
Min
Typ
Max
Unit
20
kW
16
kW
4.2
kW
FREQUENCY FOLDBACK
Symbol
1.
2.
3.
4.
Rating
Pin
Min
Typ
Max
Unit
8.5
10
11.5
mA
Ifold
Vfold
Iskip
Ftrans
Vskip
21
30
25
320
29
kHz
mV
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DAP018A/B/C/D/F
ELECTRICAL CHARACTERISTICS
(For typical values TJ = 25C, for min/max values TJ = 25C to +125C, Max TJ = 150C, VCC = 12 V unless otherwise noted)
INTERNAL RAMP COMPENSATION
Symbol
Rating
Pin
Min
Typ
Max
Unit
Vramp
3.0
Rramp
20
kW
PROTECTIONS
Rating
Pin
Min
Typ
Max
Unit
2.85
3.25
Tlatchdel
20
VtimFault
4.3
12
mA
100
ms
VBO
11
0.95
1.05
IBO
11
10
11
mA
IBO
Hysteresis current, Vpin 11 < VBO B & D versions, 25C < TJ < 25C
11
8.6
10
11
mA
IBObias
11
0.02
mA
TBOdel
20
ms
IOTP
12
101
113
124
mA
VOTP
12
0.95
1.05
TSD
Temperature shutdown
140
Symbol
Vlatch
Itim
TimerL
TSD_hys
1.
2.
3.
4.
ms
C
40
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DAP018A/B/C/D/F
8
5.1
4.6
4.1
7.6
3.6
ICC (ma)
VCC_LATCH (V)
7.8
7.4
7.2
1.6
1.1
15
10
35
60
85
110
0.6
40
135
10
35
60
85
110
TEMPERATURE (C)
35
160
30
140
135
120
TDEL (ns)
20
15
10
100
80
60
40
5
0
40
15
TEMPERATURE (C)
25
ILEAK (mA)
2.6
2.1
7
6.8
40
3.1
20
15
10
35
60
85
TEMPERATURE (C)
110
0
40
135
15
10
35
60
85
TEMPERATURE (C)
110
135
5.1
0.85
0.84
0.83
0.82
VLIMIT (V)
VTIMFAULT (V)
4.6
4.1
0.81
0.8
0.79
0.78
3.6
0.77
0.76
3.1
40
15
10
35
60
85
110
0.75
40
135
15
10
35
60
85
110
135
TEMPERATURE (C)
TEMPERATURE (C)
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DAP018A/B/C/D/F
125
73
71
69
FOSC (kHz)
IOTP (mA)
120
115
110
67
65
63
61
105
59
100
40
15
10
35
60
85
110
57
135
40
15
10
35
60
85
110
TEMPERATURE (C)
TEMPERATURE (C)
135
15.9
85
84
83
15.4
VCC(ON) (V)
DMAX (%)
82
81
80
79
78
14.9
14.4
77
76
75
40
15
10
35
60
85
110
13.9
40
135
TEMPERATURE (C)
15
10
35
60
85
TEMPERATURE (C)
110
135
7.9
9.9
7.4
VCC(LATCH) (V)
VCC(MIN) (V)
9.4
8.9
6.9
6.4
5.9
8.4
5.4
7.9
40
15
10
35
60
85
110
4.9
40
135
15
10
35
60
85
110
TEMPERATURE (C)
TEMPERATURE (C)
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9
135
DAP018A/B/C/D/F
4.9
5.9
4.4
5.4
RESETHYST (V)
VCC(RESET) (V)
3.9
4.9
4.4
3.9
3.4
2.9
2.4
1.9
3.4
2.9
40
1.4
15
10
35
60
85
110
60
85
110
4.6
4.6
4.1
4.1
ICC1(LIGHT) (mA)
ICC1 (ma)
35
3.1
2.6
2.1
3.1
2.6
2.1
1.6
1.1
1.1
15
10
35
60
85
110
0.6
40
135
15
10
35
60
85
110
TEMPERATURE (C)
TEMPERATURE (C)
0.44
0.34
Vth (V)
0.54
0.24
135
3.6
1.6
135
2
1
0.14
0.04
40
10
TEMPERATURE (C)
5.1
0.6
40
15
TEMPERATURE (C)
3.6
ICC3 (mA)
0.9
40
135
15
10
35
60
85
110
0
40
135
15
10
35
60
85
110
135
TEMPERATURE (C)
TEMPERATURE (C)
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DAP018A/B/C/D/F
18
18
17
16
VDR(HIGH) (V)
VDRV(LOW) (V)
16
14
12
10
15
14
13
12
8
6
40
11
15
10
35
60
85
TEMPERATURE (C)
110
10
40
135
340
3.4
290
2.9
240
15
10
35
60
85
110
1.4
40
135
TEMPERATURE (C)
135
15
10
35
60
85
TEMPERATURE (C)
110
135
21
3.4
19
3.3
3.2
17
VLATCH (V)
RRAMP (kW)
110
2.4
15
13
3.1
3
2.9
11
9
40
35
60
85
TEMPERATURE (C)
1.9
190
140
40
10
VRAMP (V)
VLSKIP (mV)
15
2.8
15
10
35
60
85
110
2.7
40
135
TEMPERATURE (C)
15
10
35
60
85
110
135
TEMPERATURE (C)
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11
1.06
1.06
1.04
1.04
1.02
1.02
VBO (V)
VOTP (V)
DAP018A/B/C/D/F
0.98
0.98
0.96
0.96
0.94
40
15
10
35
60
85
110
0.94
40
135
15
10
35
60
85
110
135
TEMPERATURE (C)
TEMPERATURE (C)
10.9
IBO (mA)
10.4
9.9
9.4
8.9
40
15
10
35
60
85
110
135
TEMPERATURE (C)
8.9
1800
1600
7.9
1400
1200
IC1 (mA)
IC2 (mA)
6.9
5.9
4.9
1000
800
600
400
3.9
200
2.9
40
15
10
35
60
85
110
0
40
135
15
10
35
60
85
110
135
TEMPERATURE (C)
TEMPERATURE (C)
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DAP018A/B/C/D/F
Application Information
Introduction
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13
DAP018A/B/C/D/F
typ.), the source delivers IC1 (around 500 mA typical), then,
when VCC reaches 1.8 V, the source smoothly transitions to
IC2 and delivers its nominal value. As a result, in case of
shortcircuit between VCC and GND, the power dissipation
will drop to 370 x 500 m = 185 mW. Figure 33 portrays this
particular behaviour:
VCC
VCC(on)
IC2 min
CVCC = 33 mF
IC1 min
Startup Sequence
Vth
+
-
t1
HV
IC1 or 0
10
+
VCC(on)
VCClatch
t2
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14
DAP018A/B/C/D/F
VCC
VCC(on)
VCC(min)
VCClatch
VCCreset
VFB
Feedback loops
reacts...
Full power
User
Powers up!
regulation
Freq. foldback / skip level
Current
setpoint
IpFlag
Ip,max
SS = 5 ms
No error has
been confirmed
Timer
100ms
An error flag gets asserted as soon as the current setpoint reaches its upper limit (0.8 V/Rsense). Here the timer lasts 100 ms,
a 0.22 mF capacitor being connected to pin 3.
Shortcircuit or Overload Mode
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DAP018A/B/C/D/F
Can be very
slow...
VCC(on)
VCC
VCC(min)
VCClatch
VCCreset
VFB
Duration given
by aux. cap.
regulation
IpFlag
Current loop
action keeps FB
OK (CC operation)
Timer
Drv
< 100ms
< 100ms
First fault mode case, the auxiliary winding collapses but feedback is still there (0.22 mF timer capacitor)
2. In the second case, the converter operates in
regulation, but the output is severely overloaded.
However, due to the bad coupling between the
power and the auxiliary windings, the controller
VCC does not go low. The peak current is pushed
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DAP018A/B/C/D/F
Vout is overloaded (aux is alive)
VCC
VCC(on)
VCC(min)
VCClatch
VCCreset
VFB
Duration given
by timer
Reg.
IpFlag
Timer
Drv
< 100ms
100ms
100ms
Figure 36. This Case is Similar to a Shortcircuit where Vaux does NOT Collapse
VCC
VCC(on)
VCC(min)
VCClatch
VCCreset
VFB
Reg.
Duration given
by aux. cap.
IpFlag
Timer
Drv
< 100ms
< 100ms
Figure 37. This Case is Similar to a Shortcircuit where Vaux Does Collapse
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DAP018A/B/C/D/F
The recurrence in hiccup mode can easily be adjusted by either reducing the timer or increasing the VCC capacitor. Figure 38
details the various time portion a hiccup is made of:
VCC
VCC(on)
t3
t1
VCC(min)
t2
t1
t2
VCClatch
VCCreset
Drv
timer
timer
t + CDV
I
VCCaux
Rupper
V = 9 6.5 = 2.5 V t1 = 91 ms
t2: I = 3 mA, V = 15 6.5 = 8.5 V t1 = 62 ms
t3: I = 600 mA, V = 15 6.5 = 8.5 V t1 = 311 ms
t1 = t1 = 91 ms
t2 = t2 = 62 ms
The total period duration is thus the sum of all these events
which leads to Tfault = 617 ms. If the timer lasts 100 ms, then
our dutycycle in autorecovery burst equals 100/(617 +
100) 13%, which is good. Should the user like to further
decrease or, to the contrary, increase this dutycycle,
changing the VCC capacitor is an easy job.
2
+
-
C1
10 nF
Rlower
20 ms
time
constant
+
Vlatch
aux.
Latched
Fault
Q
R
5 V Reset
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DAP018A/B/C/D/F
VCC
VCC(on)
VCC(on)
VCC(min)
VCC(min)
VCClatch
VCCreset
The user has unplugged, reset!
Drv
Vlatch
Fault!
Vlatch
If for any reason the latch pin level grows above Vlatch, the
part immediately stops pulsing and stays latched in this
position until the user cycles down the power supply. The
reset actually occurs if VCC drops below 5 V, e.g. if the
adapter user disconnects it from the mains. Figure 40 details
the operating diagrams in case of a fault. Please note the
presence of RC time constant on the comparator output,
aimed to filtering any spurious oscillations linked to an
eventual noise presence. The typical value of this time
constant is 20 ms.
On both OVP and OTP events and in the case of a
latchedOCP version, the latch reset occurs in the following
conditions:
a user reset via a mains interruption (unplug and replug
adapter) which is long enough to let the VCC capacitor
discharge to the controller reset level of 5 V.
vss
Plot1
vss in volts
1.30
Softstart
vcc
Ip(t)
5 ms
900m
500m
100m
300m
8.56m
Plot2
vcc in volts
13.0
9.23m
VCC
9.90m
10.6m
11.2m
VCC(on)
12.0
11.0
10.0
9.00
7.95m
8.95m
9.95m
time in seconds
10.9m
11.9m
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DAP018A/B/C/D/F
The softstart is activated in the following conditions:
Startup sequence: when the user powers the adapter, the
peak current smoothly rampsup from a low value
towards a maximum value defined by the sense resistor.
In autorecovery burstmode (e.g. during a
nonlatched shortcircuit), each new set of pulses starts
with a softstart sequence.
When the brownout pin senses a reset on the bulk
voltage, the controller restarts via a softstart sequence,
just like a fresh poweron sequence.
V out ) V f @ NS
P
LP
R comp +
R ramp @ divratio
20 k 0.225
+
+ 5.8 kW
1 * 0.225
(1 * divratio)
Brownout Protection
1.8 V
0V
bulk
ON
Latch
Reset
20 k
CS
Rcomp
Brown Out
Rsense
L.E.B.
from FB Setpoint
Rupper
3.3Meg
+
-
BO
VBO
1V
IBO
10 m
Rlower
10k
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DAP018A/B/C/D/F
When the input voltage is low, below VBO(on), the BO
comparator output is low and the current source is activated,
drawing 10 mA from the BO pin (pin 11) to ground. The
controller is silent, and no driving pulses are delivered to the
power MOSFET. When the input is sufficiently high, the BO
comparator toggles high and shuts down the current source,
providing the necessary hysteresis to the circuit. When
toggling high, the BO signal also resets ALL the internal
logic circuits including an eventual latch state triggered by
VCC
VCC(on)
Double hiccup 1
VCC(min)
VCClatch
VCCreset
BO acknowledged
here: hiccup reset
Vbulk
VBO(on)
Mains
Interruption
VBO(off)
BO
signal
General
internal reset
(latch...)
Drv
When the bulk comes back to its normal level, the controller waits for the next VCC(on) event to restart pulsing. If the
controller was in a doublehiccup mode, the logic circuit is reset to accelerate the restart to the next VCC(on) event.
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DAP018A/B/C/D/F
Controller waits for the next VCC(on) event (fresh restart)
VCC
restart
VCC(on)
VCC(min)
VCClatch
VCCreset
Vbulk
VBO(on)
Mains interruption
VBO(off)
BO
signal
V BO,on * V BO,off
R lower +
I BO
V BOR upper
V BO,off * V BO
(eq. 1)
(eq. 2)
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DAP018A/B/C/D/F
currents. When the feedback pin reaches the Vfold level, the
peak current is set to Vfold /4.2 and cannot decrease
anymore. The feedback voltage continues to go down but it
now changes the switching frequency down to 26 kHz
Figure 46. The Controller Changes its Operating Frequency in Light Load Conditions
V fold
10 m
(eq. 3)
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DAP018A/B/C/D/F
VDD
Ifold
10 m
Vfold
Foldback
Circuitry
5
C1
10 nF
Clock
Rload
/ 4.2
300 mV
6
+
-
Skip Cycle
Comparator
Reset
/ 4.2
This point cannot
be lower than
Vfold / 4.2
0.8 V
Current Sense
Comparator
LEB
7
ICjit
Frequency Jittering
Jitter
Frequency
Modulation
To Clock
Circuit
+
-
Ctimer
2.iCjit
+
VCjitP
VCjitV
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DAP018A/B/C/D/F
Jitter ramp
68.9kHz
65kHz
61.1kHz
Internal
sawtooth
adjustable
Figure 50. Modulation Effects on the Clock Signal by the Jittering Sawtooth
Over Power Protection
1 v(24)
40.0
offtime
Plot1
v(24) in volts
20.0
N1(Vout + Vf)
1
20.0
N2Vbulk
ontime
40.0
464u
472u
480u
time in seconds
488u
496u
Figure 51. The Signal Obtained on the Auxiliary Winding Swings Negative During the Ontime
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(eq. 4)
DAP018A/B/C/D/F
RoppU
VCC aux
Swings to:
N1Vout during toff
N2Vin during ton
from FB
VDD
Reset
SUM2
K1
OPP
K2
Iopp
ref
CS
0.8 V 5%
RoppL
Figure 52. The OPP Circuitry Affects the Maximum Peak Current Setpoint by
Summing a Negative Voltage to the Internal Voltage Reference
375 + 60 V
(eq. 5)
(eq. 6)
(eq. 7)
375
Vbulk
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DAP018A/B/C/D/F
RoppU
Dz
VCC aux
Rbias
from FB
VDD
Reset
K1
OPP
SUM2
K2
Iopp
Swings to:
N1Vout during toff
N2Vout during ton
ref
CS
0.8 V 5%
RoppL
0.16 + 24 V
Peak current
setpoint
100%
(eq. 8)
20%
150
(eq. 9)
Vbulk
375 ) 24 + 36 V
375
(eq. 10)
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DAP018A/B/C/D/F
PACKAGE DIMENSIONS
SOIC14
D SUFFIX
CASE 751A03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
A
14
P 7 PL
0.25 (0.010)
D 14 PL
0.25 (0.010)
K
T B
DIM
A
B
C
D
F
G
J
K
M
P
R
R X 45 _
T
SEATING
PLANE
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
SOLDERING FOOTPRINT
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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DAP018/D