10 - A CS6201 DPSD

JAYA SAKTHI ENGINEERING COLLEGE
Thiruninravur-602024
Academic Year 2016 - 2017 (Even Semester)
LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
Name of the Faculty : MR.M.HARIHARAN
Department : ECE
Subject Name: DIGITAL PRINCIPLES AND SYSTEM DESIGN
Subject Code: CS6201

Branch: CSE
Semester : II
Over all Plan:

Units
II
III
IV
Proposed
(To be filled at the
Beginning of the semester
based the No. of Hours
alloted in the Time table)
Actual
(To be filled at the end of
each unit)
Total No. of Hours
Reason for deviation

each unit)
Signature of Faculty
each unit)
Signature of HoD
each unit)
Previous Year
Target result for Current Year
Pass %
Highest grade
Class Average
Faculty handled the
subject in the previous
year
PREPARED BY
APPROVED BY
Name: MR.M.HARIHARAN
Name:MRS.J.JESU MEJULA
Signature:
Signature:
(Completion report- After completing all the Units
(Completion report- After completing all the Units
Signature of the faculty)
Signature of the HoD)

1

LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT I
BOOLEAN ALGEBRA AND LOGIC GATES
Review of Number Systems Arithmetic Operations Binary Codes Boolean Algebra and Theorems Boolean
Functions Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods Logic Gates
NAND and NOR Implementations.
Topics to be covered
Period
Ref.
Books
Models (Teaching aids)

Prepared by the faculty
Review of Number Systems
T1
BLACK BOARD
Arithmetic Operations Binary Codes
T1
BLACK BOARD
Boolean Algebra and Theorems
T1
BLACK BOARD
Simplification of Boolean Functions
T1
BLACK BOARD
Boolean Functions using Karnaugh Map
T1
BLACK BOARD
Boolean Functions using Karnaugh Map
T1
BLACK BOARD
Tabulation Methods
T1
BLACK BOARD
Logic Gates
T1
BLACK BOARD
NAND and NOR Implementations.
T1
BLACK BOARD
NUMBER OF PERIODS PLANNED
PROPOSED DATE OF COMPLETION
Future Scope for the students

Ideas for doing Mini
projects/Models for easy
understanding/workshops etc
ACTUAL DATE OF COMPLETION :

DEVIATION (IF ANY)
REFERENCES / WEBSITES: T1
T1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, 2008.
NO. OF MINI PROJECTS DONE BY THE STUDENTS:
SIGNATURE OF THE FACULTY
SIGNATURE OF HOD
(To be filled at the end of each unit)
Note: 1. Faculty should get HoDs signature after completing every unit.
2. The Faculty member can prepare a single Model/ Mini project for all the 5 units (if a model can be used for
all the 5 units or for each unit/topic if possible.
3. After completing each Unit, students should be encouraged to do a mini project and present in the class in front of all the
Students.

LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT II
COMBINATIONAL LOGIC
Combinational Circuits Analysis and Design Procedures Circuits for Arithmetic Operations, Code
Conversion Decoders and Encoders Multiplexers and Demultiplexers Introduction to HDL HDL Models
of Combinational circuits.
Period
Ref.
Books

Combinational Circuits
T1
BLACK BOARD
Analysis and Design Procedures
T1
BLACK BOARD
Circuits for Arithmetic Operations
T1
BLACK BOARD
Code Conversion
T1
BLACK BOARD
Decoders
T1
BLACK BOARD
Encoders
T1
BLACK BOARD
Multiplexers and Demultiplexers
T1
BLACK BOARD
Introduction to HDL
T1
BLACK BOARD
HDL Models of Combinational circuits.
T1
BLACK BOARD


DEVIATION (IF ANY)
SIGNATURE OF HOD
Students

LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT III
SYNCHRONOUS SEQUENTIAL LOGIC
Sequential Circuits Latches and Flip Flops Analysis and Design Procedures State Reduction and State
Assignment Shift Registers Counters HDL for Sequential Logic Circuits.
Period
Ref.
Books

Sequential Circuits
T1
BLACK BOARD
Latches
T1
BLACK BOARD
Flip Flops
T1
BLACK BOARD
Analysis and Design Procedures
T1
BLACK BOARD
State Reduction and State Assignment
T1
BLACK BOARD
Shift Register
T1
BLACK BOARD
Counters
T1
BLACK BOARD
Counters
T1
BLACK BOARD
HDL for Sequential Logic Circuits.
T1
BLACK BOARD

IDEAS FOR MINI PROJECTS

DEVIATION (IF ANY)
SIGNATURE OF HOD
Students

LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT IV
ASYNCHRONOUS SEQUENTIAL LOGIC
Analysis and Design of Asynchronous Sequential Circuits Reduction of State and Flow Tables Race-free
State Assignment Hazards.
Period
Ref.
Books

Analysis of Asynchronous Sequential Circuits
T1
BLACK BOARD
Design of Asynchronous Sequential Circuits
T1
BLACK BOARD
Design of Asynchronous Sequential Circuits
T1
BLACK BOARD
Reduction of State and Flow Tables
T1
BLACK BOARD
Reduction of State and Flow Tables
T1
BLACK BOARD
Race-free State Assignment.
T1
BLACK BOARD
Race-free State Assignment.
T1
BLACK BOARD
Hazards
T1
BLACK BOARD
Hazards
T1
BLACK BOARD

CHART

DEVIATION (IF ANY)
SIGNATURE OF HOD
Students

LECTURE PLAN
JEC/Academic/ 10A/01/20.10.2016
UNIT V
MEMORY AND PROGRAMMABLE LOGIC
RAM and ROM Memory Decoding Error Detection and Correction Programmable Logic Array
Programmable Array Logic Sequential Programmable Devices Application Specific Integrated Circuits.
Period
Ref.
Books

RAM and ROM
T1
BLACK BOARD
Memory Decoding
T1
BLACK BOARD
Error Detection and Correction
T1
BLACK BOARD
Programmable Logic Array
T1
BLACK BOARD
Programmable Array Logic
T1
BLACK BOARD
Sequential Programmable Devices
T1
BLACK BOARD
Sequential Programmable Devices
T1
BLACK BOARD
Application Specific Integrated Circuits
T1
BLACK BOARD
Application Specific Integrated Circuits
T1
BLACK BOARD

CHART

DEVIATION (IF ANY)
SIGNATURE OF HOD
Students

10 - A CS6201 DPSD

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

10 - A CS6201 DPSD

Transféré par

Droits d'auteur :

Formats disponibles

JAYA SAKTHI ENGINEERING COLLEGE

Academic Year 2016 - 2017 (Even Semester)

Name of the Faculty : MR.M.HARIHARAN

Subject Name: DIGITAL PRINCIPLES AND SYSTEM DESIGN

Subject Code: CS6201

Over all Plan:

Total No. of Hours

Reason for deviation

Target result for Current Year

(Completion report- After completing all the Units

(Completion report- After completing all the Units

Signature of the faculty)

Signature of the HoD)

JAYA SAKTHI ENGINEERING COLLEGE

Academic Year 2016 - 2017 (Even Semester)

Models (Teaching aids)

Review of Number Systems

Arithmetic Operations Binary Codes

Boolean Algebra and Theorems

Simplification of Boolean Functions

Boolean Functions using Karnaugh Map

Boolean Functions using Karnaugh Map

NAND and NOR Implementations.

NUMBER OF PERIODS PLANNED

PROPOSED DATE OF COMPLETION

Future Scope for the students

ACTUAL DATE OF COMPLETION :

SIGNATURE OF THE FACULTY

(To be filled at the end of each unit)

(To be filled at the end of each unit)

JAYA SAKTHI ENGINEERING COLLEGE

Academic Year 2016 - 2017 (Even Semester)

Models (Teaching aids)

Analysis and Design Procedures

Circuits for Arithmetic Operations

Multiplexers and Demultiplexers

HDL Models of Combinational circuits.

NUMBER OF PERIODS PLANNED

PROPOSED DATE OF COMPLETION

Future Scope for the students

ACTUAL DATE OF COMPLETION :

SIGNATURE OF THE FACULTY

(To be filled at the end of each unit)

(To be filled at the end of each unit)

JAYA SAKTHI ENGINEERING COLLEGE

Academic Year 2016 - 2017 (Even Semester)

Models (Teaching aids)

Analysis and Design Procedures

State Reduction and State Assignment

HDL for Sequential Logic Circuits.

NUMBER OF PERIODS PLANNED

PROPOSED DATE OF COMPLETION

Future Scope for the students

IDEAS FOR MINI PROJECTS

ACTUAL DATE OF COMPLETION :

SIGNATURE OF THE FACULTY

(To be filled at the end of each unit)

(To be filled at the end of each unit)

JAYA SAKTHI ENGINEERING COLLEGE

Academic Year 2016 - 2017 (Even Semester)

Models (Teaching aids)

Analysis of Asynchronous Sequential Circuits

Design of Asynchronous Sequential Circuits