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2 authors, including:
Zlia M. A. Peixoto
Pontifcia Universidade Catlica de Minas G
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INTRODUCTION
drives with a good cost-benefit ratio. In this context, analyses were performed associating space vector modulation
(SVPWM) and level shifted - phase disposition modulation
(LSPWM - PDPWM) strategies with control techniques for
the intermediate voltage levels, such as the minimizing of
the squared error between measured and reference flying
capacitor voltages, 3 and 2-level comparators.
The main contributions of this work can be summarized
as the following. Firstly, an balancing-voltage algorithm
that includes restrictions of the number of switchings under
conditions of charging/discharging and the maximum current
in the flying capacitors (FC). In this case, the purpose is
to reduce the harmonic distortion of the output signals and,
simultaneously, to reduce the stress of the static switches.
Furthermore, redundant switching states controllers are developed enabling the application of a modified version of
the PDPWM (PDPWM-THI) technique to the 3-level flying
capacitor topologies. The PDPWM-THI method includes an
appropriate portion of the third harmonic component that
increases of maximum voltage value obtained from the DC
bus.
All techniques were analyzed by simulations, in MatLab
environment. Aditionally, an experimental case study involving all voltage-balancing techniques and the SVPWM method
has been shown up good accordance with the simulation
results. Both analyses prove a good performance of the
proposed balancing-voltage method and its suitability to the
PWM methods.
II.
TECHNICAL BACKGROUND
x = px (k) nx (k)
SC
T
(2)
TABLE I
Switching states of a 3-level flying capacitor inverter
States
P
OA
OB
N
Sx1
1
1
0
0
Sx2
1
0
1
0
Sx3
0
1
0
1
Sx4
0
0
1
1
m=
2
(van + avbn + a2 vcn )
3
Vm
E
(3)
Vxg
E
E - VCx
VCx
0
(1)
III.
Jx =
n2
2
1X
Cjx VCjx VCjxref ) , x {a, b, c}
2 j=1
(5)
Vm
, (0 ma 1)
Vcr (n 1)
(4)
Where Vm and Vcr are the maximum values of the modulating signal and carrier wave, respectively, and n is inverters
number of levels. It can be expected maximum values lower
than in other modulation strategies. Alternatively, the adding
of a zero sequence harmonic third term to the sinusoidal
reference signal increases the modulation index, without to
affect the quality of the output signals. An increase around
15 % in the index modulation can be achieved by including a
voltage component with triple frequency and one sixth of the
amplitude reference signal [10].
TABLE II
OA /OB states selection
Input signals
VCjx < VCjxref
VCjx < VCjxref
VCjx > +VCjxref
VCjx > +VCjxref
VCjxref < VCjx < +VCjxref
VCmax =
Ix
Ix > 0
Ix < 0
Ix > 0
Ix < 0
-
Px
-1
1
1
-1
-
ixmax Tox
+ 2 VCjx
Cx
Selected State
B
A
A
B
-
(7)
IV.
SIMULATION RESULTS
Initially, the performance of all voltage balancing algorithms was evaluated in relation to the harmonic content of
output signals. The PowerGUI Block, a resource available in
MatLab-Simulink Toolbox, was used to perform the spectral
analyses. In these analyses, the magnitudes of harmonics
are calculeted in relation to magnitude of the fundamental
frequency of 60Hz. Although the harmonic frequency range
has been adjusted between 0 to 1M Hz, the results are shown
until the 20st frequency component, highlighting the range
where this load type is more susceptible.Therefore, it is worth
to observe that a large contribution to the THD is located
around the switching frequency, in this case, around 80 times
the machines rated frequency. Other aspect of these spectral
analysis refers to the presence of interharmonic components,
studies more detailed can be found in [14].
These simulations were carried out by a three-level FC
inverter supplying a three-phase induction machine (IM). The
load modeling was developed from the physical parameters
of an actual IM, the same motor used in the experimental
setup. The DC bus voltage was E = 200 VDC , the flying
capacitors were calculated as C = 470F, the frequency of
the reference voltage vector was 60Hz and the switching
frequency (FP W M ) equal to 4.8kHz, corresponding to a
frequency ratio equal to 60. At first, the amplitude modulation
index was adjusted in m = 0, 5.
A. SVPWM Method with Hysteresis Comparators
In this type of comparator, the voltage range or hysteresis
around the flying capacitor reference voltage must be defined
as a function of the estimated noise. For these simulations,
it was chosen a range VCjxref = 1V , x {a, b, c}. The
voltage waveform on the flying capacitor of the phase a is
shown in Fig. 7.
If compared with 2-level controllers, the hysteresis comparators involve a smaller number of commutations between
the states OA and OB and, despite the increased of ripple
voltage on the flying capacitors, the total distortion of output
current and voltage is reduced and the inverters present more
robustness in relation to the measurement noise.
Fig. 8 shows the frequency espectrum for the phase-tophase Vab . The amplitude of the fundamental component
(V1 = 173.2 V for rated frequency = 60 Hz) was not shown
to emphasize the incidence of other harmonics. The total
harmonic distortion was evaluated as T HD = 20.93%.
C. PDPWM Method
The simulation of the PDPWM method was performed
using assymetrical sampling, where the reference signals are
sampled twice per PWM period, at their positive and the
negative peak values. This value keeps constant during only
half time. The assymetrical sampling frequency results in
switching frequency twice higher and a better approximation
between the output voltages and the reference signals [8].
Experiments were carried out using simple 2-level controllers for the flying capacitor voltage balancing. Equivalent
results were achieved if compared to the applying of the
SVPWM technique and 3-level comparators. The flying
capacitor voltage of the phase a can be read off from Fig.
11 . As expected, the average value is equal to E/2 and the
oscillations are smaller than previous studied cases.
tion index m = 0.5 for all strategies but with different PWM
switching frequencies.
Vm = ma
E
2
(8)
ma
2
(9)
Table III depicts the resultant values for THD and rms
voltage for SVPWM, PDPWM without and includind the 3rd
harmonic component (ITH). It is clear the improvement of
the performance betweeen PDPWM and SVPWM as well as
PDPWM-ITH in relation the these previous methods.
TABLE III
Comparison of the strategies (m = 0.5 / ma = 1)
FP W M (Hz)
600
1200
2400
4800
9600
SVPWM
THD
VRM S
34,70%
127,6
35,08%
129,3
21,92%
129,4
21,08%
128,1
14,77%
129,2
PDPWM
THD
VRM S
36,39%
130,0
33,24%
129,8
25,71%
129,1
18,98%
129,7
19,53%
129,4
PDPWM-ITH
THD
VRM S
27,83%
146,5
25,82%
146,6
20,07%
144,6
15,01%
144,2
16,67%
144,7
FP W M (Hz)
4800
9600
SVPWM
THD
VRM S
21,49%
91,40
14,77%
91,41
PDPWM
THD
VRM S
26,63%
93,21
24,03%
93,17
PDPWM-ITH
THD
VRM S
24,10%
106,5
18,15%
104,9
TABLE V
Comparison of the strategies (m = 0.4) / ma = 0.8)
FP W M (Hz)
4800
9600
V.
SVPWM
THD
VRM S
24,91%
105,3
17,46%
103,4
PDPWM
THD
VRM S
26,28%
105,3
20,57%
104,6
PDPWM-ITH
THD
VRM S
23,31%
118,7
15,32%
119,7
(a) Phase-to-phase output voltage (b) Voltage oscillations across the aphase capacitor
Vab
A 3-level flying capacitor inverter prototype was implemented to drive a three-fase induction motor of 1/4 HP 230V/460V, Model 5K33GN2A, manufactured by Marathon.
The main components of the inverter are Semikron Module
IGBT SKM50GB063D, flying capacitors of 470F/450V and
digital signal processor TMS320F2812 (Texas Instruments
Inc.).The operating conditions were adjusted to the same
parameter settings used in the simulation. The control signals
comprising the three reference voltages, output currents and
flying capacitor voltages were sampled once time by each
modulation period.
Initially, there are presented some results using the traditional 2-level comparators. Fig. 15 shows output phase-tophase voltage waveform and details of the capacitor voltages
where one can be clearly observed the presence and effects of
measurement noise.
The output phase-to-phase voltage Vab and voltage oscillations across the a-phase flying capacitor, using SVPWM
technique associated with hysteresis controllers and current
observers, are presented in Fig. 18. As shown in the 2-level
controller, it can be noted the improvement of distribution
and balancing of the intermediary levels, despite the presence
of noise in signals measured. This demonstrates a greater
robustness in relation to the external disturbances.
(a) Phase-to-phase output voltage (b) Voltage oscillations across aphase flying capacitor
Vab
(a) Phase-to-phase output voltage (b) Voltage oscillations across the aphase capacitor
Vab
The output phase-to-phase voltage Vab and voltage oscillations across the a-phase flying capacitor, using SVPWM
technique associated with hysteresis controllers, are shown in
Fig. 16. It can be noted the improvement of distribution and
balancing of the intermediary levels, despite the presence of
noise in signals measured.
VI.
CONCLUSION
Oxford