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DCR01
Series
01
DCR
01
Miniature, 1W Isolated
REGULATED DC/DC CONVERTERS
FEATURES
APPLICATIONS
UL1950 RECOGNIZED
DIP-18, SO-28
53W/in3 (3.3W/cm3) POWER DENSITY
DEVICE-TO-DEVICE SYNCHRONIZATION
THERMAL PROTECTION
1000Vrms ISOLATION
DESCRIPTION
400kHz SWITCHING
The DCR01 family is a series of high-efficiency, inputisolated, output-regulated DC/DC converters. In addition to
1W nominal, galvanically-isolated output power capability,
this range of DC/DCs offer very low output noise, thermal
protection, and high accuracy.
The DCR01 family is implemented in standard molded IC
packaging, giving standard JEDEC outlines suitable for
high-volume assembly.
The DCR01 is manufactured using the same technology
as standard IC packages, thereby achieving very high reliability.
VREC
SYNC
ENABLE
VS
Input
Controller
LDO
Regulator
ERROR
VOUT
0VIN
0VOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000-2003, Texas Instruments Incorporated
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ORDERING INFORMATION
DCR01
05
05
(P)
PACKAGE/ORDERING INFORMATION
PRODUCT
DCR010503P
DCR010503U
DCR010505P
DCR010505U
DCR011203P
DCR011203U
DCR011205P
DCR011205U
DCR012403P
DCR012403U
DCR012405P
DCR012405U
PACKAGE-LEAD
PACKAGE
DESIGNATOR
DIP-18
SO-28
DIP-18
SO-28
DIP18
SO-28
DIP-18
SO-28
DIP-18
SO-28
DIP-18
SO-28
NVE
DVB
NVE
DVB
NVE
DVB
NVE
DVB
NVE
DVB
NVE
DVB
SPECIFIED
TEMPERATURE
RANGE
40C
40C
40C
40C
40C
40C
40C
40C
40C
40C
40C
40C
to
to
to
to
to
to
to
to
to
to
to
to
+85C
+85C
+85C
+85C
+85C
+85C
+85C
+85C
+85C
+85C
+85C
+85C
PACKAGE
MARKING
ORDERING
NUMBER
DCR010503P
DCR010503U
DCR010505P
DCR010505U
DCR011203P
DCR011203U
DCR011205P
DCR011205U
DCR012403P
DCR012403U
DCR012405P
DCR012405U
DCR010503P
DCR010503U/1K
DCR010505P
DCR010505U/1K
DCR011203P
DCR011203U/1K
DCR011205P
DCR011205U/1K
DCR012403P
DCR012403U/1K
DCR012405P
DCR012405U/1K
TRANSPORT
MEDIA, QUANTITY
Rails, 20
Tape and Reel,
Rails, 20
Tape and Reel,
Rails, 20
Tape and Reel,
Rails, 20
Tape and Reel,
Rails, 20
Tape and Reel,
Rails, 20
Tape and Reel,
1000
1000
1000
1000
1000
1000
DCR01 Series
SBVS013C
ELECTRICAL CHARACTERISTICS
At TA = +25C, VS = nominal, IO = 10mA, CO = 0.1F, unless otherwise specified.
DCR01 SERIES
PARAMETER
CONDITIONS
OUTPUT
Setpoint
DCR010503
DCR010505
DCR011203
DCR011205
DCR012403
DCR012405
Setpoint Accuracy
Maximum Output Current
DCR010503P
DCR010503U
DCR010505P
DCR010505U
DCR011203P
DCR011203U
DCR011205P
DCR011205U
DCR012403P
DCR012403U
DCR012405P
DCR012405U
Output Short-Circuit Protected
Line Regulation
DCR010503
DCR010505
DCR011203
DCR011205
DCR012403
DCR012405
Over Line and Load
DCR010503
DCR010505
DCR011203P
DCR011203U
DCR011205
DCR012403P
DCR012403U
DCR012405
Versus Temperature
Ripple and Noise
MIN
TYP
3.3
5
3.3
5
3.3
5
0.5
MAX
UNITS
2.0
V
V
V
V
V
V
%
300
300
200
200
390
300
200
200
390
300
200
200
Duration
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Infinite
1
1
1
1
1
1
5.5V Line
5.5V Line
13.2V Line
13.2V Line
13.2V Line
26.4V Line
26.4V Line
26.4V Line
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
mV/V
mV/V
mV/V
mV/V
mV/V
mV/V
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
%
%
%
%
%
%
%
%
%
DCR010503P
DCR010503P
DCR010503U
DCR010503U
Ripple
Noise
Ripple
Noise
5
35
8
23
mVp-p
mVp-p
mVp-p
mVp-p
DCR010505P
DCR010505P
DCR010505U
DCR010505U
Ripple
Noise
Ripple
Noise
6
20
9
20
mVp-p
mVp-p
mVp-p
mVp-p
DCR011203P
DCR011203P
DCR011203U
DCR011203U
Ripple
Noise
Ripple
Noise
10
54
8
22
mVp-p
mVp-p
mVp-p
mVp-p
DCR011205P
DCR011205P
DCR011205U
DCR011205U
Ripple
Noise
Ripple
Noise
6
45
6
21
mVp-p
mVp-p
mVp-p
mVp-p
DCR012403P
DCR012403P
DCR012403U
DCR012403U
Ripple
Noise
Ripple
Noise
10
22
8
22
mVp-p
mVp-p
mVp-p
mVp-p
DCR012405P
DCR012405P
DCR012405U
DCR012405U
Ripple
Noise
Ripple
Noise
10
22
13
32
mVp-p
mVp-p
mVp-p
mVp-p
DCR0105xx
DCR0112xx
DCR0124xx
5
12
24
V
V
V
%
INPUT
Nominal Voltage (VS)
Voltage Range
DCR01 Series
SBVS013C
10
+10
DCR010503U
DCR010505P
DCR010505U
DCR011203P
DCR011203U
DCR011205P
DCR011205U
DCR012403P
DCR012403U
DCR012405P
DCR012405U
CONDITIONS
MIN
ERROR FLAG
Logic High Open Collector Leakage
Logic Low Output Voltage
MAX
UNITS
IO = 0mA
IO = 10mA
IO = 300mA
IO = 0mA
IO = 10mA
IO = 300mA
18
28
335
24
33
339
mA
mA
mA
mA
mA
mA
IO = 0mA
IO = 10mA
IO = 200mA
IO = 0mA
IO = 10mA
IO = 200mA
25
40
306
25
40
306
mA
mA
mA
mA
mA
mA
IO = 0mA
IO = 10mA
IO = 390mA
IO = 0mA
IO = 10mA
IO = 390mA
13
17
173
13
17
136
mA
mA
mA
mA
mA
mA
IO = 0mA
IO = 10mA
IO = 200mA
IO = 0mA
IO = 10mA
IO = 200mA
13
18
125
14
19
123
mA
mA
mA
mA
mA
mA
IO = 0mA
IO = 10mA
IO = 390mA
IO = 0mA
IO = 10mA
IO = 390mA
17
18
97
15
17
75
mA
mA
mA
mA
mA
mA
IO = 0mA
IO = 10mA
IO = 200mA
IO = 0mA
IO = 10mA
IO = 200mA
20MHz Bandwidth, 100% Load
CIN = 2.2F, CFILTER = 1F
15
18
69
15
18
67
8
mA
mA
mA
mA
mA
mA
mAp-p
25
kVrms
kVrms
pF
1s Flash Test
60s Test, UL1950(2)
1
1
Input/Output Capacitance
OUTPUT ENABLE CONTROL
Logic High Input Voltage
Logic High Input Current
Logic Low Input Voltage
Logic Low Input Current
VREC
VREC
TYP
2.0
2.0 < VENABLE < VREC
VREC
100
0.2
0 < VENABLE < 0.5
All 3.3V Outputs
All 5V Outputs
0.5
100
3.3
5
VERROR = 5V
Sinking 2mA
10
0.4
THERMAL SHUTDOWN
Junction Temperature
Temperature Activated
Temperature Deactivated
720
720
2.5
0
TEMPERATURE RANGE
Operating
40
800
2.5
A
V
C
C
150
130
SYNCHRONIZATION PIN
Max External Capacitance on SYNC Pin
Internal Oscillator Frequency
External Synchronization Frequency
External Synchronization Signal High
External Synchronization Signal Low
V
nA
V
nA
V
V
3
880
880
5.0
0.4
pF
kHz
kHz
V
V
+85
NOTES: (1) CIN = 2.2F, CFILTER = 1F, COUT = 0.1F. (2) During UL approval only.
DCR01 Series
SBVS013C
PIN CONFIGURATIONS
Top View
SO
DIP
VS
18 SYNC
VS
28 SYNC
NC
17 0VIN
VS
27 0VIN
NC
26 0VIN
DCR01
DCR01U
VREC
12 ERROR
VREC 12
17 ERROR
0VOUT
11 ENABLE
0VOUT 13
16 ENABLE
VO
10 DNC
PIN #
PIN NAME
PIN #
PIN NAME
VS
Voltage Input
VS
NC
No Connection
VS
Voltage Input
VREC
Rectified Output
NC
No Connection
0VOUT
Output Ground
12
VREC
Rectified Output
VO
Voltage Output
13
VOUT
Output Ground
10
DNC
Do Not Connect
14
VO
Voltage Output
11
ENABLE
15
DNC
Do Not Connect
12
ERROR
17
0VIN
18
SYNC
DCR01 Series
SBVS013C
DESCRIPTION
15 DNC
VO 14
16
ENABLE
Input Ground
17
ERROR
Synchronization Input
26
0VIN
27
0VIN
28
SYNC
DESCRIPTION
Voltage Input
TYPICAL CHARACTERISTICS
At TA = +25C, VS = 5V, IO = 10mA, CFILTER = 1F, CO = 0.1F, unless otherwise specified.
18
80
16
70
14
60
12
Noise (mVp-p)
10
8
6
40
30
20
10
0
0
20
40
60
80
100
20
40
60
80
Load (%)
Load (%)
3V OUTPUT EFFICIENCY
(5V and 12V Input Devices)
30.0
70
25.0
60
100
85C
50
20.0
Efficiency (%)
50
15.0
10.0
40C
40
25C
30
20
5.0
10
0
0
0
20
40
60
80
100
10
20
30
40
50
60
70
Load (%)
Load (%)
5V OUTPUT EFFICIENCY
(5V and 12V Input Devices.
80
90
100
80
90
100
80
60
+85C
70
50
+25C
40
Effeciency (%)
Efficiency (%)
60
30
20
50
40
40C
30
20
10
10
0
0
0
10
20
30
40
50
Load%
60
70
80
90
100
10
20
30
40
50
60
70
Load (%)
DCR01 Series
SBVS013C
EFFICIENCY vs LOAD
DCR0112405 P and U DEVICES
70
70
60
60
50
50
Efficiency (%)
Efficiency (%)
40
30
30
20
20
10
10
0
0
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
Load (%)
Load (%)
120.0
60.0
100.0
50.0
80.0
40.0
Noise (mVp-p)
Noise (mVp-p)
40
60.0
40.0
90
100
30.0
20.0
10.0
20.0
0
0
20
40
60
80
40%
20%
0%
100
80%
60%
Load (%)
Load%
3V OUTPUT vs LOAD
(all devices except DCR010503P)
3.305
100%
3.325
85C
3.3
3.325
3.305
3.29
VOUT (V)
VOUT (V)
3.295
3.285
25C
3.28
3.295
3.285
3.275
3.275
3.27
40C
3.265
3.265
0
10
20
30
40
50
Load (%)
DCR01 Series
SBVS013C
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
LOAD vs VOUT
(for all 5V Output Devices)
5.04
5.02
40mA/div
VOUT (V)
5.00
4.98
4.96
4.94
4.94
0
10
20
30
40
50
60
70
80
90
100
500ns/div
Load (%)
20mA/div
200mV/div
500ns/div
10s/div
Load Current
Load Current
20mV/div
200mV/div
150mA Changing
to 300mA
Load Current
Output Voltage
Output Voltage
10s/div
Output Voltage
200ns/div
DCR01 Series
SBVS013C
200mV/div
5mV/div
20mA Changing
to 200mA
Output Voltage
200ns/div
10s/div
200mV/div
20mV/div
100mA Changing
to 200mA
Load Current
Output Voltage
10s/div
200ns/div
5mV/div
200ns/div
DCR01 Series
SBVS013C
FUNCTIONAL DESCRIPTION
OVERVIEW
The DCR01 series offers isolation from an unregulated
power supply operating from a choice of input voltages. The
DCR01s provide a variety of regulated output voltages at a
nominal output power of 1W or above.
POWER STAGE
The input supply is chopped at a frequency of 400kHz
(internal oscillator divided by 2), which is used to drive the
center-tapped toroidal transformer.
CONSTRUCTION
The DCR01 is manufactured using the same technology as
standard IC packages. There is no substrate within the
package. The DCR01 is constructed using a driver IC, lowdropout voltage regulator, rectifier diodes, and a wound
magnetic toroid, all mounted on a leadframe. The DCR01
requires no special PCB assembly processing, as there is no
solder within the package. The result is an isolated DC/DC
converter with inherently high reliability.
RECTIFICATION
The transformers output is full wave rectified and smoothed
by the external capacitor connected to VREC.
REGULATOR
The internal low drop-out regulator provides a well-regulated output voltage, throughout the operating range of the
device.
ADDITIONAL FUNCTIONS
DISABLE/ENABLE
The DCR01 can be disabled or enabled by driving the SYNC
pin using an open drain CMOS gate. If the SYNC pin is
pulled LOW, the DCR01 will be disabled. The disable time
depends upon the external loading. The internal disable
function is implemented in 2s. Removal of the pull down
will enable the DCR01.
Capacitance loading on the SYNC pin should be minimized
in order to prevent a reduction in the internal oscillators
frequency. See Application Report (SBAA035) External
Synchronization of the DCP01/02 Series of DC/DC Converters. This document contains information on how to null
the effects of additional capacitance on the SYNC pin. The
oscillators frequency can be measured at VREC, as this is the
fundamental frequency of the ripple component.
SYNCHRONIZATION
If more than one DCR01 is being used, beat frequencies and
other electrical interference can be generated. This is due to
the small variations in switching frequencies between the
converters.
The DCR01 overcomes this by allowing devices to be
synchronized to one another. Up to eight devices can be
synchronized by connecting the SYNC pins together, with
care being taken to minimize the capacitance of tracking.
Significant stray capacitance on the SYNC pin will have the
effect of reducing the frequency of the internal oscillator. If
this is large, the DCR01 may be taken outside its optimized
operating parameters, and saturation of the magnetics may
result, damaging the device.
OUTPUT ENABLE/DISABLE
The regulated output of the DCR01 can be disabled by pulling
the ENABLE pin LOW (connect ENABLE to 0VOUT). Holding the ENABLE pin HIGH (connect ENABLE to VREC)
enables the regulated output voltage, thus allowing the output
to be controlled from the isolated side, see Figure 1.
U1
VIN
VS
VO1
VOUT
RERR = 10k
CIN
DCR
SYNC
0V
01
ERROR
VREC
ERROR
REN = 10k
ENABLE
0V
SW1
see text
CFILTER = 1F
COUT = 0.1F
0VOUT
DCR01 Series
SBVS013C
APPLICATION NOTES
ERROR FLAG
The DCR01 has an ERROR pin which provides a power
good flag, as long as the internal regulator is in regulation.
DECOUPLING
Ripple Reduction
Due to the very low forward resistance of the DMOS
switching transistors, high current demands are placed upon
the input supply for a short time. By using a good quality
low Equivalent Series Resistance (ESR) capacitor of 2.2F
(minimum) for the 5V input devices and a 0.47F capacitor
for the 12V and 24V devices, placed close to the IC supply
input pins, the effects on the power supply can be minimized.
The high switching frequency of 400kHz allows relatively
small values of capacitors to be used for filtering the rectified output voltage. A good quality low ESR capacitor of
1F placed close to the VREC pin and output ground will
reduce the ripple.
It is not recommended that the DCR01 be fitted using an
IC socket as this will degrade performance.
The output at VREC is full wave rectified and produces a
ripple of 800kHz.
It is recommended that a 0.1F low ESR capacitor is
connected close to the output pin and ground to reduce noise
on the output. The capacitor values listed are minimum
values. If lower ripple is required then the filter capacitor
should be increased in value to 2.2F.
NOTE: As with all switching power supplies the best
performance is only obtained with low ESR capacitors
connected close to the switcher. If low ESR capacitors are
not used, the ESR will generate a voltage drop when the
capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose when a low ESR smaller
capacitance would perform as well.
U1
VIN
VS
VO1
VOUT
RERR = 10k
ERROR
CIN(1)
DCR
01
ERROR
VREC
COUT = 0.1F
ENABLE
SYNC
0V
0V
CFILTER = 1F
0VOUT
U2
VIN
VS
VO2
VOUT
RERR = 10k
ERROR
CIN(1)
DCR
01
SYNC
0V
ERROR
VREC
COUT = 0.1F
ENABLE
0V
CFILTER = 1F
DCR01 Series
SBVS013C
11
PCB LAYOUT
RIPPLE AND NOISE
Careful consideration should be given to the layout of the
PCB in order for the best results to be obtained.
The DCR01 is a switching power supply and as such can
place high peak current demands on the input supply. In
order to avoid the supply falling momentarily during the fast
switching pulses, ground and power planes should be used
to track the power to the input of DCR01 (this will also serve
to reduce noise on the circuit). If this is not possible, the
supplies must be connected in a star formation, with the
tracks made as wide as possible.
THERMAL MANAGEMENT
Due to the high power density of this device, it is advisable
to provide a ground plane on the output. The output regulator is mounted on a copper leadframe, and a ground plane
will serve as an efficient heatsink.
U1
VIN
VS
VPOS O/P
VOUT
ERROR
DCR
CIN(1)
01
VREC
COUT = 0.1F
ENABLE
SYNC
0V
0V
CFILTER = 1F
0V
U2
VIN
VS
VOUT
ERROR
DCR
CIN(1)
01
SYNC
0V
VREC
COUT = 0.1F
ENABLE
VNEG O/P
0V
CFILTER = 1F
12
DCR01 Series
SBVS013C
www.ti.com
7-Jan-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
DCR010503P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
DCR010503P
DCR010503U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010503U
DCR010503U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010503U
DCR010503UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010503U
DCR010505P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
DCR010505P
DCR010505U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010505U
DCR010505U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010505U
DCR010505U/1KE4
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010505U
DCR010505UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR010505U
DCR011203P
ACTIVE
PDIP
NVE
10
20
TBD
CU NIPDAU
Level---
DCR011203P
DCR011203U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR011203U
DCR011203U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR011203U
DCR011203UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR011203U
DCR011205P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
DCR011205P
DCR011205U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR011205U
DCR011205U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR011205U
DCR011205UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR011205U
Addendum-Page 1
Samples
www.ti.com
7-Jan-2015
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
DCR012403P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
DCR012403P
DCR012403U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR012403U
DCR012405P
ACTIVE
PDIP
NVE
10
20
Pb-Free
(RoHS)
CU NIPDAU
DCR012405P
DCR012405U
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR012405U
DCR012405U/1K
ACTIVE
SOP
DVB
12
1000
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR012405U
DCR012405UE4
ACTIVE
SOP
DVB
12
28
Pb-Free
(RoHS)
CU NIPDAU
Level-3-260C-168 HR
DCR012405U
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
www.ti.com
7-Jan-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
MECHANICAL DATA
MPDI055 APRIL 2001
NVE (R-PDIP-T10/18)
PLASTIC DUAL-IN-LINE
0.920 (23,37)
0.880 (22,35)
18
10
0.280 (7,11)
0.240 (6,10)
D
Index
Area
E
0.070 (1,78)
0.045 (1,14)
0.195 (4,95)
0.115 (2,92)
Base
Plane
C
Seating
Plane
0.325 (8,26)
0.300 (7,62)
0.210 (5,33)
MAX
E
0.005 (0,13)
MIN 4 PL
Full Lead D
0.100 (2,54)
0.022 (0,56)
0.014 (0,36)
0.010 (0,25) M C
0.150 (3,81)
0.115 (2,92)
0.300 (7,63)
0.014 (0,36)
0.008 (0,20)
0.015 (0,38)
MIN
0.060 (1,52)
0.000 (0,00)
0.430 (10,92)
MAX
F
4202497/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001-AC with the exception
of lead count.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the
leads unconstrained.
G. A visual index feature must be located within the
cross-hatched area.
PACKAGE OUTLINE
DVB0012A
10.65
10.01
SEATING PLANE
PIN 1 ID
AREA
28
18.1
17.7
NOTE 3
0.1 C
8X 1.27
2X 16.51
14
15
B
7.6
7.4
12X
0.51
0.33
0.25
C A
0.32
TYP
0.23
SEE DETAIL A
2.65 MAX
8
0
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4222497/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MS-013.
www.ti.com
DVB0012A
12X (2)
SYMM
1
28
12X (0.6)
(R0.05)
TYP
SYMM
(16.51)
8X (1.27)
14
15
(9.3)
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
DVB0012A
12X (2)
1
SYMM
28
12X (0.6)
(R0.05)
SYMM
(16.51)
8X (1.27)
14
15
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222497/A 10/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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