Introduction to Parallel Computing

CS4355/5325
Assignment 1
Due Date: September 17, 2009

1) Consider a processor with two pipelines with ability to simultaneously issue two instructions per
cycle.
a. Do the execution schedule for the code fragments in figure 2.1 (ii) and figure 2.1 (iii) in
the text book.
b. Do the utilization trace of the processor for both cases(figure 2.1 (ii) and figure 2.1 (iii))
2) Consider 1 GHz processor with 100 ns (nano second) latency DRAM. We have cache with size 32
KB with latency of 1 ns (1 cycle is 1 ns). Assume that we will multiply two 32x32 matrices
(A.B=C). Each matrix has integer values which are one word. A word size is 32 bits. Assume
memory to cache latency is 100 ns. According to the above given specifications, show explicit
solutions for the followings:
a. What is the total number of operations for this matrix multiplication?
b. What is total time for the computation?
c. What is the peak computation rate?
3) What is the route taken from node # 13 to node # 42 for hypercube topology with e-cube
routing algorithm with the least significant bit approach? Calculate each hop step by step.
13 (001101)->42(101010)