Lecture 330 - High Speed Comparators: CMOS Analog Circuit Design, 2

Lecture 330 High Speed Comparators (3/28/10)
Page 330-1
LECTURE 330 HIGH SPEED COMPARATORS

LECTURE ORGANIZATION
Outline
Speed limitations of comparators
High speed comparators
Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 461-464 and 483-487
CMOS Analog Circuit Design
P.E. Allen - 2010
Page 330-2
SPEED LIMITATIONS OF COMPARATORS

Speed Limitations of Comparators
The speed of a comparator is limited by either:
Linear response response time is inversely proportional to the magnitude of poles
j
Increase for
speed
Gain
vout Propagation
Time Delay
Increase
bandwidth
060810-01
VOH
VOL
Slew rate delay is proportional to capacitance and inversely proportional to

current sinking or sourcing capability
VDD
ISource
ISink
vout
VOH
+
CL vout
VOL
Propagation
Time Delay
dvout = I
dt
CL
t
060810-02
P.E. Allen - 2010
Page 330-3
Maximizing the Linear Response

Consider the amplifier of Example 270-3 given below:
VDD
VPB1
5
I5
+
Vin
3
1
I4
I3
4
V
out + 2
I2
I1
VPB1
I6
I7
7
VNB1
060711-01
One stage of this amplifier had a gain of 10 and a dominant pole at 551MHz. The
response of this amplifier to a step input is
V out(t) = 10Vin (1-e-p1t)
If the output signal swing is 1V and the step is 0.1V, the propagation time delay is,
V in(min) = 1/10 = 0.1V k = 1
2k
2
1

1

ln 2-1 = 0.20 ns
tp = ln 2k-1 =
6
2551x10
p1
P.E. Allen - 2010
Page 330-4
Trading Speed for Sensitivity (Gain)

In the previous example, the gain was too small for good sensitivity. To enhance the
sensitivity, cascade three of the gain of 10 stages. The result is,
Vin
A1
10V/V
p1=551MHz
A2
10V/V
p1=551MHz
A3
Vout
10V/V
p1=551MHz
The frequency response of this amplifier is,

V out(s)
1000
=
V in(s) (1+s/p1)3
The step response of this amplifier is
Ao
Ao
Ao
vout(t) = 2 V inp13t2e-p1t 2 V inp13t2[1 - p1t + p12t2- ] 2 V inp13t2 if p1t<1
The propagation delay time is
V OH-V OL 1
1
tp2 =
=

tp = 0.0049 ps if k = 1
3
Ao
V inp1 kp13
The speed of the amplifier will be limited by the slew capability!
P.E. Allen - 2010
Page 330-5
Maximizing Speed for Slew Rate Limitation

The key is to make the sourcing/sinking current large and the capacitance small.
Best possible sinking/sourcing circuit in CMOS is:
VDD
M2
ISource
vOUT
vIN
M1 ISink
CL
060810-03
Assuming a W/L ratio of 42 for M1 and 200 for M2, if the input can swing to VDD
(=2.5V) and ground, the sourcing and sinking currents are:
Kp' W
25200
ISourcing = 2L (VDD |VTP|)2 = 2 (2.5V-0.5)2 A = 10.0 mA
Kn' W
12042
ISinking = 2L (VDD VTN)2 = 2 (2.5V-0.5)2 A = 10.1 mA
If larger currents are required, cascaded stages can be used to optimize the delay versus
the current output.
P.E. Allen - 2010
Page 330-6
Driver Delay of a Push-Pull Inverter

If too much current is required, the device sizes become large and the driver delay
increases. For the previous example, the input capacitance for the driver assuming Cox
6fF/m2 and the channel lengths are 0.5m, is,
Cin = Cgs1 + Cgs2 = 2(2/3) Cox(W 1L1 + W2L2)
= 1.336fF/m2(121m2) = 0.968 pF
M2
200m
0.5m
Driver
M1
Cin
070510-02
42m
0.5m
CLoad
If the effective resistance of the driver is 30k, then the delay is 29 ns which is much too
large.
P.E. Allen - 2010
Page 330-7
Optimizing the Delay of a Chain of Push-Pull Inverters

For a series of N inverters as shown below, the W/L is increased by a factor of f for each
succeeding stage.
W/L = 1
f2
f N-2
f N-1
Cin
CLoad = fNCin
070510-01
ln(CLoad/Cin)
ln f
The delay of a single, push-pull inverter can be expressed as,
C

j

tinv = invCj-1+inv
where
inv = ReffCin
(Reff is the effective output resistance of the inverter)
Cself Cjunction
inv = Cin = Cin
(Cjunction is the bulk-drain capacitances)
From the above figure we see that CLoad = f NCin _ N =
P.E. Allen - 2010
Page 330-8
Optimizing the Delay of a Chain of Push-Pull Inverters Continued

The total delay of the chain of inverters is
C

j

ttotal = N invCj-1+inv
Cj
Setting f = Cj-1 gives
ln(CLoad/Cin)
inv (f + inv)
ln f
Plotting the total delay versus f for various values of inv shows that the optimum value of
f lies in the range of 2.5 to 4.
ttotal =
D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd ed., McGrawHill Book Co., 2004, Chapter 6.
P.E. Allen - 2010
Page 330-9
Example 330-1 Finding the Optimum Delay for a Chain of Inverters

Assume that CLoad is 5pf, Cin = 50fF, inv = 10ps , and inv = 0.5. If f = 3.6, find the
optimal number of stages and the total delay of this chain of inverters.
Solution
From above we get the optimal number of stages as,
ln(CLoad/Cin) ln(100)
N=
=
= 3.59
ln f
ln 3.6
If we choose N = 4, then f can be recomputed as
1
f = 3.16
ln f = ln(100)
4
The total delay is,
C

j
ttotal = N invC +inv = 410ps(3.16 + 0.5) = 146ps
j-1
P.E. Allen - 2010
Page 330-10
Self-Biased Differential Amplifier

Not as good as the push-pull inverter but interesting.
VDD
VBias
VDD
M6
M6
M4
M3
M4
M3
vin+
vin-
vout
vin+
M1
M1
Extremely
large sourcing
current
vinM2
M2
M5
VBias
M5
VSS
VSS
Advantage:
Large sink or source current with out a large quiescent current.
Disadvantage:
Poor common mode range (vin+ slower than vin-)
Fig. 8.3-4
M. Bazes, Two Novel Full Complementary Self-Biased CMOS Differential Amplifiers, IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, Feb.
1991, pp. 165-168.
P.E. Allen - 2010
Page 330-11
Two-Stage Comparator with Increased Speed

Clamp the input stage with 1/gm loads to decrease the signal swing and avoid slew rate
limitation in the first stage.
VDD
M6
M4
M8
M3
vn
M1
vout
M2
CL
vp
M5
M9
+
VBias
-
M7
Metal
060808-06
Comments:
Gain reduced Larger input resolution
Push-pull output Higher slew rates
Can increase the current drive by cascading the output stage
P.E. Allen - 2010
Page 330-12
Comparators that Can Drive Large Capacitive Loads

VDD
M8
M3
M10
M4
M6
vn
M1
vout
M2
vp
CL
+
VNB1
-
M5
M7
M9
M11
060808-08
Comments:
Slew rate = 3V/s into 50pF
Linear rise/fall time = 100ns into 50pF
Propagation delay time 1s
Loop gain 32,000 V/V
The quiescent dc currents in the output stages are not well defined
Use the principle of optimizing the delay in cascaded inverters
P.E. Allen - 2010
Page 330-13
HIGH SPEED COMPARATORS

A Study in Exponentials
The step response of an amplifier with a gain of Ao and a dominant pole at A is,
vout(t) = Ao[1 exp(-At)] Vin
vout
AoVin
Slow rising
Fast rising
t
060810-04
The latch response to a step input of Vin is,

t
vout(t) = Vin exp tL
vout
Fast rising
2.72Vin
Slow rising
0
t
060810-05
P.E. Allen - 2010
Page 330-14
A High-Speed Comparator Architecture

Cascade an amplifier with a latch to take advantage of the exponential characteristics of
the previous slide.
Preamplifier
+
Vin
+
Vo1
Ao
+
Vout
Latch
060810-06
In order to keep the bandwidth of the amplifier large, the gain will be small. To achieve
Preamplifier 1
+
Vin
Ao1/n
Preamplifier n
Preamplifier 2
+
Vo1
Ao1/n
+
Vo2
Gain = Ao
+
Von-1
Ao1/n
+
Von
Latch
+
Vout
060810-08
Therefore, the question is how many stages of the amplifier and what is the gain of each
stage for optimum results?
P.E. Allen - 2010
Page 330-15
Ex. 330-2 Optimizing the Propagation Time Delay

A comparator consists of an amplifier cascaded with a latch as shown below. The
amplifier has a voltage gain of 10V/V and f-3dB = 100MHz and the latch has a time constant
of 1ns. The maximum and minimum voltage swings of the amplifier and latch are V OH and
V OL. When should the latch be enabled after the application of a step input to the amplifier
of 0.05(VOH-V OL) to get minimum overall propagation time delay? What is the value of the
minimum propagation time delay?
vin = 0.05(VOH-VOL)
t=0
Amplifier
Av(0)=10V/V
f-3dB=100MHz
voa
vil
Comparator
Latch
L=1ns
vout
070606-01
Enable
Solution
The solution is based on the figure shown.
We note that,
voa(t) = 10[1-e--3dBt]0.05(VOH-V OL).
If we define the input voltage to the latch as,
vil = x(VOH-V OL)
then we can solve for t1 and t2 as follows:
Amplifier
VOH
Latch
x(VOH-VOL)
t2
VOL
t1
t
S01E3S1
P.E. Allen - 2010
Page 330-16
Example 330-2 - Continued

x(VOH-V OL) = 10[1-e--3dBt1]0.05(VOH-V OL) x = 0.5[1-e--3dBt1]
This gives,
1
1

t1 = -3dB ln
1-2x
From the propagation time delay of the latch we get,
V -V
1
OH

OL

t2 = L ln 2vil = L ln
2x
1
1
1
dtp

tp = t1 + t2 = -3dB ln
1-2x + L ln
2x dx = 0 gives
2L-3dB
0.4
2x = 2+2L-3dB = 2+0.4 = 0.3859
(x = 0.1930)

10ns
1

t1 = 2 ln
1-0.3859 = 1.592ns0.4875 = 0.7762 ns

1
and t2 = 1ns ln
0.3859 = 0.9522ns
tp = t1 + t2 = 0.776 ns + 0.952 ns = 1.728 ns
P.E. Allen - 2010
Page 330-17
Minimizing the Propagation Delay Time in Comparators

Facts:
The input signal is equal to Vin(min) for worst case
Amplifiers have a step response with a negative argument in the exponential
Latches have a step response with a positive argument in the exponential
If the amplifiers rise too quickly, they will be slew limited
Approach:
Use a cascade of low-gain, wide-bandwidth amplifiers to take a small input signal and
amplify it without suffering slew limit
Use a latch to take the amplified input and quickly reach 0.5(VOH-V OL)
P.E. Allen - 2010
Page 330-18
Minimization of the Propagation Delay Time

Minimization of tp:
Q. If the preamplifer consists of n stages of gain A having a single-pole response, what is
the value of n and A that gives minimum propagation delay time?
A. n = 6 and A = 2.62 but this is a very broad minimum and n is usually 3 and A 6-7
to save area.
Preamplifier 1
+
Vin
Ao1/3
Preamplifier 3
Preamplifier 2
+
Vo1
Ao1/3
+
Vo2
Gain = Ao
Ao1/3
+
Vo3
Latch
+
Vout
070509-06
P.E. Allen - 2010
Page 330-19
Fully Differential, Three-Stage Amplifier and Latch Comparator

Circuit:
FB
Cv1
Sample
+
vin Sample
Reset
Cv2
060810-08
+ -+
FB
FB
FB
Cv3
FB
Reset
FB
+ -
+ -
FB
-+
-+
FB
+
Latch vout
FB
Reset
Cv6
Cv4
FB
Cv5
Reset
FB
FB
Clock
Comments:
Autozero and reset phase followed by comparison phase
In the autozero phase, switches labeled Reset and FB are closed.
In the sample phase, switches labeled Sample and FB are closed.
Can run as high as 200Msps
P.E. Allen - 2010
Preamplifier and Latch Circuits

Gain:
gm1
gm2
KN(W 1/L1)
Av = - gm3 = - gm4 = Kp(W 3/L3)
Dominant Pole:
gm3 gm4
|pdominant| = C = C
where C is the capacitance seen from the
output nodes to ground.
Page 330-20
VDD
M3
FB
M4
Q
Reset
M1
FB
M5
M6
M2
If (W1/L1)/(W 3/L3) = 100 and the

Latch
Enable
bias current is 100A, then A = -3.85
Latch
Preamplifier
and the bandwidth is 15.9MHz if C =
0.5pF.
VBias
Comments:
Fig. 8.6-4
If a buffer is used to reduce the output
capacitance, one must take into account the loss of the buffer.
The use of a preamplifier before the latch reduces the latch offset by the gain of the
preamplifier so that the offset is due to the preamplifier only.
P.E. Allen - 2010
Page 330-21
An Improved Preamplifier
Circuit:
VDD
VBiasP
vout- M5
M3
VBiasP
M4
vout+
M6
Reset
FB M11
M12
M10
M8
M7
VBias
vin+
VBiasN
vin-
M2
M1
FB
M9
Fig. 8.6-5
Gain:
gm1
Av = - gm3 = -
KN(W 1/L1)I1
KN(W 1/L1)
=
KP(W 3/L3)I3
KP(W 3/L3)
If I5 = 24I3, the gain is increased by a factor of 5
I5
1+I3
P.E. Allen - 2010
Page 330-22
Improved Frequency Response of the Amplifier

If the ratio of transconductance W/L is much larger than the load W/L, the frequency
response will suffer. Using the technique of the previous slide, we can keep the ratio of
the W/Ls to a more reasonable value. The result is higher frequency response.
Amplifier of Example 270-3:
VDD
VPB1
5
I5
+
Vin
3
1
I3
I4
4
V
out + 2
I2
I1
VNB1
I6
VPB1
6
I7
7
060711-01
Gain = 20dB
f-3dB = 551MHz
P.E. Allen - 2010
Page 330-23
High-Speed CMOS Comparator

The comparator used in a 12-bit, 200 Msps ADC is shown below. The comparator is
used in each of the 4-bit pipeline stages which requires 15 comparators.
The comparators consist of three stages including (a.) differential input pairs, (b.) a crosscoupled latch, and (c.) an SR latch to hold the comparator output until the next clock
cycle.
VDD
1
1
iout1
vout1
iout2
vin1
VNB1
1
iin1
iin2
vin2
Vref1
VDD
vout2
S
Q
Vref2
NMOS Input Pair
Latch
SR-Latch
070511-01
T. Liechti, Design of a High-Seed 12-bit Differential Pipelined A/D Converter, Diploma Project, Feb. 2004, Microelectronic Systems Laboratory,
Swiss Federal Institute of Technology, Lausanne.
P.E. Allen - 2010
Page 330-24
High Speed CMOS Comparator Continued

Schematic of the fully differential comparator:
Clock waveforms:
Mean comparator power
dissipation is 140W
under typical conditions
P.E. Allen - 2010
Page 330-25
High Speed CMOS Comparator Continued

Transistor sizes:
Transistor
W(m)
L(m)
M0a, M1a, M2a, M3a, M4a, M5a, M6a,

M0b, M1b M2b, M3b M4b M5b M6b
M0c,
M2c,
M0d
M2d
1.5
6
3.6
3
1
1
0.24
1
2.5 0.18 0.18 0.18 0.18 0.18
M7
M8a, M9a, M10a, M11a

M8b M9b M10b M11b
0.5
0.18
2
2.5
0.18 0.18
3
0.18
0.24
0.18
Comparator offsets (worst case):
P.E. Allen - 2010
Page 330-26
SUMMARY
Comparators are limited in speed either by bandwidth or slew rate
Increasing the magnitude of the poles improves the bandwidth limitations
Increasing the current sinking/sourcing ability improves the slew rate limitation
Most high speed comparators use a combination of preamplifier followed by a latch
- The preamplifier uses bandwidth to quickly build up the input
- The latch uses positive feedback to take the signal to its final state
P.E. Allen - 2010

Lecture 330 - High Speed Comparators: CMOS Analog Circuit Design, 2

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Lecture 330 - High Speed Comparators: CMOS Analog Circuit Design, 2

Transféré par

Droits d'auteur :

Formats disponibles

Lecture 330 High Speed Comparators (3/28/10)