EECE-457 (VLSI II)

MOS Transistor Behavior

Major Md Tawfiq Amin, PhD
Department of Electrical, Electronic, and Communication Engineering
Military Institute of Science and Technology (MIST)

Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (DV/Dt) -> Dt = (C/I) DV
Capacitance and current determine speed

MIST- Major Md Tawfiq Amin, PhD

MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
Vg < 0

+
-

polysilicon gate
silicon dioxide insulator
p-type body

(a)

0 < V g < Vt

+
-

depletion region

(b)

V g > Vt
+
-

inversion region
depletion region

(c)

MIST- Major Md Tawfiq Amin, PhD

Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs
Vgd = Vg Vd
Vds = Vd Vs = Vgd - Vgs
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Vg
Cutoff
+
Linear
+
Vgs
Vgd
Saturation
Vs
MIST- Major Md Tawfiq Amin, PhD

Vds

Vd
4

nMOS Cutoff
No channel
Ids = 0
Vgs 0

Vgs = 0

+
-

+
-

n+

n+

Vgd

p-type body
b

MIST- Major Md Tawfiq Amin, PhD

nMOS Linear
Channel forms
Current flows from d to s
e- from s to d
Ids increases with Vds
Similar to linear resistor

Vgs > Vt

+
-

+
-

n+

n+

Vgd = Vgs

Vds = 0

p-type body
b

Vgs > Vt

+
-

+
d

n+

n+

Vgs > Vgd > Vt

Ids
0 < Vds < Vgs-Vt

p-type body
b

MIST- Major Md Tawfiq Amin, PhD

nMOS Linear I-V

In Linear region, Ids depends on
How much charge Qchannel is in the channel
How much time each carrier takes to cross

Qchannel
I ds
t
W
Cox
L

W
= Cox
L

V V
V
gs
ds
t
2

V
Vgs Vt ds Vds = (Vgs-Vt )Vds -Vds2/2 = (Vgs-Vt )Vds
2

Vds

It is a region called linear region. Here Ids varies linearly, with

Vgs and Vds when the quadratic term Vds2/2 is very small. Vds << VgsVt
MIST- Major Md Tawfiq Amin, PhD

nMOS Saturation

Channel pinches off

Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt

+
-

+
-

Vgd < Vt

d Ids

n+

n+

Vds > Vgs-Vt

p-type body
b

MIST- Major Md Tawfiq Amin, PhD

nMOS Saturation I-V

If Vgd < Vt, channel pinches off near drain
When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
Qchannel
I ds
t
W
Cox
L

V V Vds V
gs
t
2 ds

V
Vgs Vt ds Vds = (Vgs-Vt )Vds -Vds2/2
2

Where 0 < Vgs Vt <Vds, considering (Vgs-Vt )=Vds we have

Ids = (Vgs-Vt ) 2/2
MIST- Major Md Tawfiq Amin, PhD

nMOS I-V Summary

0
Vgs Vt
cutoff

Vds
I ds Vgs Vt
Vds Vds Vdsat
linear

Vgs Vt
Vds Vdsat saturation

MIST- Major Md Tawfiq Amin, PhD

10

Example
Consider a nMOS transistor in a 0.6 m process.
tox = 100
2.5
V =5
2
= 350 cm /V*s
2
Vt = 0.7 V
1.5
V =4
Plot Ids vs. Vds
1
V =3
Vgs = 0, 1, 2, 3, 4, 5
0.5
V =2
V =1
Use W/L = 4/2
0
Ids (mA)

gs

gs

gs

gs

gs

Vds

3.9 8.85 1014 W

W
Cox 350

8
L
100 10
L
MIST- Major Md Tawfiq Amin, PhD

120

A
/
V

11

pMOS I-V
All dopings and voltages are inverted for pMOS
Mobility p is determined by holes
Typically 2-3x lower than that of electrons n
120 cm2/V*s in 0.6 m process
Thus pMOS must be wider to provide same current
In this class, assume n / p = 2

MIST- Major Md Tawfiq Amin, PhD

12

Capacitance
Any two conductors separated by an insulator have
capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because
associated with source/drain diffusion

MIST- Major Md Tawfiq Amin, PhD

it

is

13

Gate Capacitance
Approximate channel as connected to source
Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m (90 and 65 nm)

polysilicon
gate
W
tox
n+

n+

SiO2 gate oxide

(good insulator, ox = 3.90)

p-type body

MIST- Major Md Tawfiq Amin, PhD

14

Diffusion Capacitance
Csb, Cdb
Undesirable, called parasitic capacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Varies with process

MIST- Major Md Tawfiq Amin, PhD

15

Electric Field Effects

Vertical electric field: Evert = Vgs / tox
Attracts carriers into channel
Long channel: Qchannel Evert
Lateral electric field: Elat = Vds / L
Accelerates carriers from drain to source
Long channel: v = Elat

MIST- Major Md Tawfiq Amin, PhD

16

Mobility Degradation
High Evert effectively reduces mobility
Collisions with oxide interface

MIST- Major Md Tawfiq Amin, PhD

17

Velocity Saturation
At high Elat, carrier velocity rolls off
Carriers scatter off atoms in silicon lattice
Velocity reaches vsat
Electrons: 107 cm/s
Holes: 8 x 106 cm/s
Better model

MIST- Major Md Tawfiq Amin, PhD

18

Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2
2
W Vgs Vt

I ds Cox
Vgs Vt
L
2
2
2

Velocity-saturated ON current increases with VDD

I ds CoxW Vgs Vt vmax

Real transistors are partially velocity saturated

MIST- Major Md Tawfiq Amin, PhD

19

Channel Length Modulation

Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
Leff = L Ld
Shorter Leff gives more current
Ids increases with Vds Even in saturation
GND
Source

VDD
Gate

VDD
Drain
Depletion Region
Width: Ld

n
+

L
Leff
p GND

n
+
bulk Si

MIST- Major Md Tawfiq Amin, PhD

20

Chan-Length Mod I-V

1
W
2
I D nCox VGS VTH 1 VDS
2
L

MIST- Major Md Tawfiq Amin, PhD

21

 and L

Unlike the Early voltage in BJT, the channel- length modulation

factor can be controlled by the circuit designer.
For long L, the channel-length modulation effect is less than that
of short L.
MIST- Major Md Tawfiq Amin, PhD
22

Threshold Voltage Effects

Vt is Vgs for which the channel starts to invert
Ideal models assumed Vt is constant
Really depends (weakly) on almost everything else:
Body voltage: Body Effect
Drain voltage: Drain-Induced Barrier Lowering
Channel length: Short Channel Effect

MIST- Major Md Tawfiq Amin, PhD

23

Body Effect
Body is a fourth transistor terminal
Vsb affects the charge required to invert the channel
Increasing Vs or decreasing Vb increases Vt

Vt Vt 0

s Vsb s

s = surface potential at threshold

s 2vT ln

NA
ni

Depends on doping level NA

And intrinsic carrier concentration ni
= body effect coefficient

MIST- Major Md Tawfiq Amin, PhD

tox

ox

2q si N A
2q si N A
Cox
24

Body Effect Cont.

For small source-to-body voltage, treat as linear

MIST- Major Md Tawfiq Amin, PhD

25

Short Channel Effect

In small transistors, source/drain depletion regions
extend into the channel
Impacts the amount of charge required to invert
the channel
And thus makes Vt a function of channel length
Short channel effect: Vt increases with L
Some processes exhibit a reverse short channel
effect in which Vt decreases with L

MIST- Major Md Tawfiq Amin, PhD

26

Leakage
What about current in cutoff?
Simulated results
What differs?
Current doesnt go to 0 in cutoff

MIST- Major Md Tawfiq Amin, PhD

27

Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Dominant source in contemporary transistors
Gate leakage
Tunneling through ultrathin gate dielectric
Junction leakage
Reverse-biased PN junction diode current

MIST- Major Md Tawfiq Amin, PhD

28

Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt 0 Vds k Vsb

I ds I ds 0e

nvT

Vds

1 e vT

n is process dependent
typically 1.3-1.7
Rewrite relative to Ioff on log scale

S 100 mV/decade @ room temperature

MIST- Major Md Tawfiq Amin, PhD

29

Gate Leakage
Carriers tunnel thorough very thin gate oxides
Exponentially sensitive to tox and VDD

A and B are tech constants

Greater for electrons
So nMOS gates leak more

Negligible for older processes (tox > 20 )

Critically important at 65 nm and below (tox 10.5 )
MIST- Major Md Tawfiq Amin, PhD

30

Junction Leakage
Reverse-biased p-n junctions have some leakage
Ordinary diode leakage
Band-to-band tunneling (BTBT)
Gate-induced drain leakage (GIDL)

p+

n+

n+

p+

p+

n+

n well
p substrate

MIST- Major Md Tawfiq Amin, PhD

31

Diode Leakage
Reverse-biased p-n junctions have some leakage
VvD
I D I S e T 1

At any significant negative diode voltage, ID = -Is

Is depends on doping levels
And area and perimeter of diffusion regions
Typically < 1 fA/mm2 (negligible)

MIST- Major Md Tawfiq Amin, PhD

32

Gate-Induced Drain Leakage

Occurs at overlap between gate and drain
Most pronounced when drain is at VDD, gate is at
a negative voltage
Thwarts efforts to reduce subthreshold leakage
using a negative gate voltage

MIST- Major Md Tawfiq Amin, PhD

33

Temperature Sensitivity
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature

MIST- Major Md Tawfiq Amin, PhD

34

So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation

MIST- Major Md Tawfiq Amin, PhD

35

Parameter Variation
Transistors have uncertainty in parameters
Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)
Leff: short
Vt: low
tox: thin
Slow (S): opposite
Not all parameters are independent for nMOS and
pMOS

MIST- Major Md Tawfiq Amin, PhD

36

Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low

Corner

Voltage

Temperature

1.98

0C

1.8

70 C

1.62

125 C

MIST- Major Md Tawfiq Amin, PhD

37

Process Corners
Process corners describe worst case
variations
If a design works in all corners, it will
probably work for any variation.

Describe corner with four letters (T, F, S)

nMOS speed
pMOS speed
Voltage
Temperature

MIST- Major Md Tawfiq Amin, PhD

38

Thanks
MIST- Major Md Tawfiq Amin, PhD

39

Q&A

MIST- Major Md Tawfiq Amin, PhD

40