FT/GN/68/01/23.01.

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SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY

Page 1 of 6
LP: CS6303

Department of Electronics And Communication

B.E/B.Tech/M.E/M.Tech : ECE
PG Specialisation

Rev. No: 00
Date: 29/01/2016

Regulation: 2013

: N/A

Sub. Code / Sub. Name : CS6303 / COMPUTER ARCHITECTURE

Unit

:I
Unit Syllabus:

Eight ideas Components of a computer system Technology Performance Power wall Uniprocessors to
multiprocessors; Instructions operations and operands representing instructions Logical operations control
operations Addressing and addressing modes.
Objective:

To make students understand the basic structure and operation of digital computer.

Session
No *

Topics to be covered

Ref

Teaching
Aids

1.

Introduction to the unit and discussion on the fundamentals

PPT

2.

Eight ideas, Components of a computer system

PPT

3.

Technology , Performance , Power wall

PPT

4.

Discussion on Uniprocessors to multiprocessors

PPT

5.

Introduction to Instructions

BB

6.

operations and operands , representing instructions

BB

7.

Logical operations, control operations

BB

8.

Addressing and addressing modes

PPT

9.

Discussion on the overall unit.

Content beyond syllabus covered (if any):

* Session duration: 50 minutes

PPT

FT/GN/68/01/23.01.16

SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY

Page 2 of 6

Sub. Code / Sub. Name: CS6303 / COMPUTER ARCHITECTURE

Unit II: ARITHMETIC OPERATIONS
Unit Syllabus:

ALU - Addition and subtraction Multiplication Division Floating Point operations Subword
parallelism.
Objective:

To familiarize the students with arithmetic and logic unit and implementation of fixed point and
floating-point arithmetic operations.

Session
No *

Topics to be covered

Ref

Teaching
Aids

10.

Introduction to the unit

PPT

11.

ALU

PPT

12.

Addition and subtraction

BB

13.

Multiplication

BB

14.

Division

BB

15.

Floating Point operations

BB

16.

Subword parallelism

PPT

17.

Coding for all arithmetic operations

6&7

BB

18.

Discussion on the overall unit

Content beyond syllabus covered (if any):

* Session duration: 50 mins

FT/GN/68/01/23.01.16

SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY

Page 3 of 6

Sub. Code / Sub. Name: CS6303 / COMPUTER ARCHITECTURE

Unit III : PROCESSOR AND CONTROL UNIT

Unit Syllabus :

Basic MIPS implementation Building datapath Control Implementation scheme Pipelining

Pipelined datapath and control Handling Data hazards & Control hazards Exceptions.
Objective:

To expose the students to the concept of pipelining.

Session
No *

Topics to be covered

Ref

Teaching
Aids

19.

Introduction to the unit

PPT

20.

Basic MIPS implementation

PPT

21.

Building datapath

PPT

22.

Control Implementation scheme

PPT

23.

Pipelining

PPT

24.

Pipelined Datapath and control

PPT

25.

Handling Data hazards and Control Hazards

PPT

26.

Exceptions

PPT

27.

Discussion on the overall unit

Content beyond syllabus covered (if any):

* Session duration: 50 mins

PPT

FT/GN/68/01/23.01.16

SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY

Page 4 of 6

Sub. Code / Sub. Name: CS6303 / COMPUTER ARCHITECTURE

Unit IV: PARALLELISM
Unit Syllabus:

Instruction-level-parallelism Parallel processing challenges Flynn's classification

Hardware multithreading Multicore processors
Objective:

To familiarize the students with the concept of pipelining

Session
No *

Topics to be covered

Ref

Teaching
Aids

28.

Introduction to the unit

PPT

29.

Instruction level parallelism

PPT

30.

Parallel processing challenges

PPT

31.

Flynns classification

BB

32.

Continuation with Flynns classification

BB

33.

Hardware multithreading

PPT

34.

Multicore processors

PPT

35.

Discussion about the unit

Content beyond syllabus covered (if any):

* Session duration: 50 mins

PPT

FT/GN/68/01/23.01.16

SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY

Page 5 of 6

Sub. Code / Sub. Name: CS6303 / COMPUTER ARCHITECTURE

Unit V: MEMORY AND I/O SYSTEMS

Unit Syllabus:
Memory hierarchy - Memory technologies Cache basics Measuring and improving cache
performance - Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts,
I/O processors.
Objective:
To familiarize the students with hierarchical memory system including cache memories and virtual
memory and also the different ways of communicating with I/O devices and standard I/O interfaces.

Session
No *

Topics to be covered

Ref

Teaching
Aids

36.

Introduction to the unit

PPT

37.

Memory hierarchy

38.

Memory technologies

39.

Cache basics

40.

Measuring and improving cache performance

41.

Virtual memory

42.

TLBs Input/Output system

43.

Programmed I/O, I/O processors

44.

DMA and interrupts

45.

Discussion on the unit and previous year question papers

Content beyond syllabus covered (if any):

* Session duration: 50 mins

PPT
PPT
BB
PPT
BB
PPT
PPT
PPT
PPT

FT/GN/68/01/23.01.16

SRI VENKATESWARA COLLEGE OF ENGINEERING

COURSE DELIVERY PLAN - THEORY

Page 6 of 6

Sub Code / Sub Name: CS6303 / COMPUTER ARCHITECTURE

REFERENCES:
1. David A. Patterson and John L. Hennessey, Computer Organization and Design, Fifth
edition, Morgan Kauffman / Elsevier, 2014.
2. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, Computer Organisation, VI
edition, Mc Graw-Hill Inc, 2012.
3. William Stallings Computer Organization and Architecture, Seventh Edition , Pearson
Education, 2006.
4. Vincent P. Heuring, Harry F. Jordan, Computer System Architecture, Second Edition,
Pearson Education, 2005.
5. Govindarajalu, Computer Architecture and Organization, Design Principles and Applications",
first edition, Tata Mc Graw Hill, New Delhi, 2005.
6. John P. Hayes, Computer Architecture and Organization, Third Edition, Tata Mc Graw Hill,
1998.
7. http://nptel.ac.in/.