Académique Documents
Professionnel Documents
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p Voltage
g Domains
(with Software Labs)
Material from Vazgen Melikyan, Synopsys
Co-developed for MSE Conference 2009
and Synopsys University Program
Prof. Dejan Markovi
Electrical Engineering Department
University of California, Los Angeles.
1
Logic Synthesis
Libraries
RTL Simulation
Physical Implementation
Verification
Signoff
UPF
UPF: Definition
UPF Definition
Define power distribution architecture
Power domains
Supply rails
Switches
UPF
Logic Synthesis
Gate Level
UPF
Physical Synthesis
Gate Level
PG Gate Level
UPF
Power Aware
RTL and Gate Level
Functional Verification
Like Simulation Pattern to Verify
Power states from PST
Isolation value
Retention
Identified in .lib by
Isolation cells
is_isolation_cell : true;
Identified in .lib by
Retention registers
retention_cell : cell_type;
Identified in .lib by
switch_cell_type : coarse_grain;
Benefits
pg_pin(VDD) {
std_cell_main_rail : true ;
voltage_name : VDD;
pg_type
: primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type
: primary_ground;
}
Chi T
ChipTop
GENPP is an always-on PD
within Multiplier
PwrCtrl
InstDecode
GPRs
1900um2
1197um2
34150um2
Multiplier
46089um2
Single clock
Number of clocked elements:
Combinational area:
Noncombinational area:
Dynamic Power:
Leakege Poower :
719
92.315um2
1650996um2
2.6193mW
1.39 mW
MemX
MemY
GENPP
174304.8um2
174304.8um2
26009um2
10
GPRs
(Low Volt, High Volt.
OFF)
MemXHier
(Low Volt, OFF)
MemX
Multiplier
(High Volt, OFF)
GENPP
(High Volt)
MemYHier
(Low Volt, OFF)
MemY
PwrCtrl
11
VDDG
VDD
on/off
InstDecode
GPRs
0.8V
on/off
0.8V
VDDIS
1.0V
VDDGS
1.0V
OFF
OFF
inst_on
VSS
VSS
gprs_on
mult_on
Multiplier
ChipTop
1.0V
on/off
1.0V
GENPP
OFF
1.0V
VDDMS
VSS
12
VDDI
InstDecode
GPRs
on/off
0.8V
VDDIS
1.0V
OFF
RR
LS
NRESTORE
VDDGS
1.0V
OFF
ISO
on/off
0.8V
ELS
ISO
RR
LS
VSS
ELS
VSS
SAVE
VDD
VDD
on/off
Multiplier
1 0V
1.0V
OFF
GENPP
ISO
1.0V
ChipTop
VDDMS
ISO
1.0V
VSS
13
14
15
insert_clock_gating
propagate_constraints
-gate_clock
16
#Reading UPF
source ./inputs/chiptop+.upf
#Reading constraints
source ./inputs/chiptop+_s0.sdc
#Compiling
compile
-exact_map -gate_clock
./results/compile.upf
17
18
19
create_supply_port
create_supply_net
connect_supply
pp y_net
set_domain_supply_net
Connects supply
pp y nets and p
ports
Sets power domains power/ground nets
20
10
set_isolation
set_isolation_control
set_retention
set_retention_control
map_retention_cell
Defines the UPF retention control signals for the defined UPF
retention strategy
Defines how to map the unmapped sequential cells to retention
cells for the specified retention strategy of the power domain.
21
-elements GPRs
create_supply_port
create_supply_net
create_supply_net
connect_supply_net
VDD
VDD
VDD
VDD
-domain TOP
-domain GPRS reuse
-ports VDD
create_supply_port
create_supply_net
create_supply_net
connect_supply_net
VSS
VSS
VSS
VSS
-domain TOP
-domain GPRS -reuse
-ports VSS
create_supply_net
VDDGS
Creating power
domains
Creating supply
nets
-domain GPRS
set_domain_supply_net
t d
i
l
t TOP
\
-primary_power_net VDD \
-primary_ground_net VSS
set_domain_supply_net GPRS \
-primary_power_net VDDGS \
-primary_ground_net VSS
Setting primary
power/ground
nets
22
11
create_power_switch gprs_sw \
-domain GPRS \
-input_supply_port {in VDD} \
-output_supply_port
l
{
{out
VDDGS}
} \
-control_port {gprs_sd PwrCtrl/gprs_sd} \
-on_state {state2002 in {gprs_sd}}
set_isolation gprs_iso_out \
-domain GPRS \
-isolation_power_net VDD \
-isolation_ground_net VSS \
-clamp_value 1 \
-applies_to outputs
Setting Isolation
set_isolation_control gprs_iso_out \
-domain GPRS \
-isolation_signal PwrCtrl/gprs_iso \
-isolation_sense low \
-location parent
Setting Isolation
control options
23
Setting
Retention
control
options
Mapping
Retention
cells to
librarys cell
{HV
{HV
{HV
{HV
{HV
HV}
HV}
OFF}
OFF}
OFF}
Port state
definition
Creating Port
State Table
24
12
#Reading constraints
source ./inputs/chiptop+_s0.sdc
#Compiling
compile
#Writing out results
change_names -rule verilog hier
write -f verilog
-h -out
./results/compile.v
write -f ddc
-h -out ./results/compile.ddc
save_upf ./results/compile.upf
#Reading UPF
source ./inputs/chiptop+.upf
25
Macro
cells
I/O
cells
Design Library
Gate-level Netlist
(Verilog / VHDL)
Logic Synthesis
(DC)
Standard
cells
Physical Design
(ICC)
UPF
Design
Constraints
UPF
GDS II
26
13
27
28
14
create_supply_port
create_supply_net
connect_supply_net net
name -ports port
name
set_domain_supply_net
set_level_shifter
29
-elements GPRs
create_supply_port
create_supply_net
create_supply_net
connect_supply_net
VDD
VDD
VDD
VDD
-domain TOP
-domain GPRS reuse
-ports VDD
create_supply_port
create_supply_net
create_supply_net
connect_supply_net
VSS
VSS
VSS
VSS
-domain TOP
-domain GPRS -reuse
-ports VSS
create_supply_net
VDDGS
Creating power
domains
Creating supply
nets
-domain GPRS
set_domain_supply_net
t d
i
l
t TOP
\
-primary_power_net VDD \
-primary_ground_net VSS
set_domain_supply_net GPRS \
-primary_power_net VDDGS \
-primary_ground_net VSS
Setting primary
power/ground
nets
30
15
Setting Isolation
set_isolation_control gprs_iso_out \
-domain GPRS \
-isolation_signal PwrCtrl/gprs_iso \
-isolation_sense low \
-location parent
Setting Isolation
control options
add_port_state VDD
-state {HV 1.2}
add_port_state VDDGS -state {LV 0.7}
31
#Reading constraints
source ./inputs/chiptop+_s0.sdc
#Compiling
compile
#Writing out results
change_names -rule verilog hier
write -f verilog
-h -out
./results/compile.v
write -f ddc
-h -out ./results/compile.ddc
save_upf ./results/compile.upf
32
16
33
34
17