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13

6 The table shows the assembly language instructions for a processor which has one general purpose register – the Accumulator.

Instruction

Op Code

Operand

Explanation

LDD <address>

Load using direct addressing

STO <address>

Store the contents of the Accumulator at the given address

LDI <address>

Load using indirect addressing

LDX <address>

Load using indexed addressing

INC

Add 1 to the contents of the Accumulator

END

End the program and return to the operating system

(a)

Write on the diagram to explain the assembly language instruction shown below. Show the contents of the Accumulator after the execution of the instruction.

 

LDD 66

Main memory

 

60

0110

0000

61

0100

0000

 

Accumulator

62

1111

1110

 

63

1111

0000

 

64

0101

1101

65

0001

0001

66

1010

1000

67

1100

0001

65 0001 0001 66 1010 1000 67 1100 0001 200 1001 1111 (b) Write on the
65 0001 0001 66 1010 1000 67 1100 0001 200 1001 1111 (b) Write on the

200

1001

1111

(b)

Write on the diagram to explain the assembly language instruction shown. Show the contents of the Accumulator after the execution of the instruction.

 

[2]

LDI 61

Main memory

 

60

0110

0000

61

0100

0000

 

Accumulator

62

1111

1110

 

63

1111

0000

 

64

0101

1101

65

0001

0001

66

1010

1000

67

1100

0001

0000   64 0101 1101 65 0001 0001 66 1010 1000 67 1100 0001 200 1001
0000   64 0101 1101 65 0001 0001 66 1010 1000 67 1100 0001 200 1001

200

1001

1111

 

[3]

For

Examiner's

Use

© UCLES 2012

9691/33/M/J/12

1

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14

(c) Trace this assembly language program using the given trace table. The first instruction of
(c)
Trace this assembly language program using the given trace table. The first instruction
of the program is loaded into main memory at address 200.
200
LDD 208
201
INC
202
STO 208
203
LDD 207
204
INC
205
STO 207
206
END
207
16
208
150
Memory Address
Accumulator
207
208
16
150
[4]
(d)
Explain the relationship between assembly language instructions and machine code
instructions.

[1]

© UCLES 2012

9691/33/M/J/12

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For

Examiner's

Use

Page 6 Mark Scheme: Teachers’ version Syllabus Paper GCE A LEVEL – May/June 2012 9691
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Mark Scheme: Teachers’ version
Syllabus
Paper
GCE A LEVEL – May/June 2012
9691
33
6
(a)
LDD 66
Main memory
60
0110
0000
61
0100
0000
Accumulator
62
1111
1110
1010
1000
63
1111
0000
64
0101
1101
65
0001
0001
66
1010
1000
67
1100
0001
100
1001
1111
Mark as follows:
- Sensible annotation which makes clear 66 used
- Final value in Acc
[2]
(b)
LDI 61
Main memory
60
0110
0000
61
0100
0000
Accumulator
62
1111
1110
0101
1101
63
1111
0000
64
0101
1101
65
0001
0001
66
1010
1000
67
1100
0001
200
1001
1111
Mark as follows
- Go to address 61 // shows arrow to 61
- Pick up the forwarding address 64 // shows arrow to 64
Correct final contents copied to Acc // shows arrow from contents of 64 to Acc
[3]

© University of Cambridge International Examinations 2012

3

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Syllabus

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GCE A LEVEL – May/June 2012

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33

(c) Memory Address Accumulator 207 208 16 150 150 151 151 16 17 17
(c)
Memory Address
Accumulator
207
208
16
150
150
151
151
16
17
17

Mark as follows

- 150 to Acc

- Incremented to 151 and copied to 208

- 16 copied to Acc and

- incremented to 17 copied to address 207

(d) Every assembly language instruction is translated into exactly one machine code instruction /

there is a 1-to-1 relationship between them

[1]

Total: 10

© University of Cambridge International Examinations 2012

4

12

5 The table shows the assembly language instructions for a processor which has one general purpose register – the Accumulator.

Instruction

Op Code

Operand

Explanation

LDD <address>

Load using direct addressing

STO <address>

Store the contents of the Accumulator at the given address

LDI <address>

Load using indirect addressing

LDX <address>

Load using indexed addressing

INC

Add 1 to the contents of the Accumulator

END

End the program and return to the operating system

(a)

Write on the diagram to explain the instruction shown. Show the contents of the Accumulator after the execution of the instruction.

 

LDD 105

Main memory

 
 

100

0100

0000

101

0110

1000

 

Accumulator

102

1111

1110

   

103

1111

1010

 

104

0101

1101

105

0001

0001

106

1010

1000

107

1100

0001

105 0001 0001 106 1010 1000 107 1100 0001 200 1001 1111   [2] (b) Write
105 0001 0001 106 1010 1000 107 1100 0001 200 1001 1111   [2] (b) Write

200

1001

1111

 

[2]

(b)

Write on the diagram to explain the instruction shown. Show the contents of the registers after the execution of the instruction.

 

LDX 101

Main memory

 

100

 

0100

0000

101

 

0110

1000

 

Accumulator

102

 

1111

1110

   

103

 

1111

1010

 

104

 

0101

1101

105

 

0001

0001

 

Index Register

106

 

1010

1000

0000 0011

 

107

 

1100

0001

 
   
 
   

200

 

1001

1111

 

[4]

© UCLES 2012

9691/31/M/J/12

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For

Examiner's

Use

13

(c) Trace this assembly language program using the trace table below. 500 LDD 507 501
(c)
Trace this assembly language program using the trace table below.
500
LDD 507
501
INC
502
STO 509
503
LDD 508
504
INC
505
STO 510
506
END
507
22
508
170
509
0
510
0
Memory Address
Accumulator
507
508
509
510
22
170
0
0
[5]
(d)
Explain the relationship between assembly language instructions and machine code
instructions.

[1]

For

Examiner's

Use

© UCLES 2012

9691/31/M/J/12

6

[Turn over

 

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Mark Scheme: Teachers’ version

Syllabus

Paper

 

GCE A LEVEL – May/June 2012

9691

31

5

(a)

LDD 105

Main memory

 

100

0100

0000

101

0110

1011

Accumulator

102

1111

1110

0001 0001

103

1111

1010

 

104

0101

1101

105

0001

0001

106

1010

1000

107

1100

0001

200

1001

1111

Mark as follows:

- Sensible annotation which makes clear 105 is the address used

- Final value in Acc

[2]

© University of Cambridge International Examinations 2012

7

Page 5 Mark Scheme: Teachers’ version Syllabus Paper GCE A LEVEL – May/June 2012 9691
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Syllabus
Paper
GCE A LEVEL – May/June 2012
9691
31
(b)
LDX 101
Main memory
100
0100
0000
101
0110
1011
Accumulator
102
1111
1110
0101 1101
103
1111
1010
104
0101
1101
105
0001
0001
Index Register
106
1010
1000
00000011
107
1100
0001
200
1001
1111
Mark as follows:
- IR contents converted to 3
- Computed address of 101 + 3 = 104
// explanation: add contents of IR to address part of instruction
- Then, ‘direct addressing’ to 104
- Final value in Acc
[MAX 4]
(c)
Memory Address
Accumulator
507
508
509
510
22
170
0
0
22
23
23
170
171
171

Mark as follows

- 22 to Accumulator

- Incremented to 23

- 23 copied to address 509

- 170 copied to Accumulator and incremented to 171

- 171 in address 510

[5]

(d) Every assembly language instruction is translated into exactly one machine code instruction /

there is a 1-to-1 relationship between them

[1]

[Total: 11]

© University of Cambridge International Examinations 2012

8

6

3 The table shows the assembly language instructions for a processor which has one general purpose register – the Accumulator (ACC), and an index register (IX).

Instruction

 

Op Code

Operand

Explanation

LDD <address>

Direct addressing. Load the contents of the given address to ACC

STO <address>

Store the contents of ACC at the given address

LDI <address>

Indirect addressing. At the given address is the address to be used. Load the contents of this second address to ACC

LDX <address>

Indexed addressing. Form the address as <address> + the contents of IX. Copy the contents of this address to ACC

INC <register>

Add 1 to the contents of the register (ACC or IX)

ADD <address>

Add the contents of the given address to the contents of ACC

OUT

Output the contents of ACC (as a denary number) to the monitor

IN

Input a denary number from the keyboard and store in ACC

END

End the program and return to the operating system

© UCLES 2013

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9

For

Examiner's

Use

7

The diagram shows a program loaded in main memory starting at location 100.

Two of the op-codes have been partially blanked out.

Locations 200 onwards contain data which is used by the program.

(a)

The instruction at address 100 is fetched. Shown are the contents of the registers after execution.

 

100 LD■ 202

101 INC ACC

 

ACC

 

102 INC ACC

 

88

103 LD■ 203

 

104 INC ACC

105 LDI 203

 

IX

106 INC ACC

 

2

 

107 END

 
 
 

200

38

201

205

202

88

203

200

204

48

205

126

 

Which mode of addressing was used by this load instruction at address 100?

[1]

(b)

The instruction at address 103 is fetched. Shown are the contents of the registers after execution.

ACC

126

IX

2

Which mode of addressing was used by this load instruction at address 103?

[1]

For

Examiner's

Use

© UCLES 2013

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10

[Turn over

8

(c) The instruction at address 105 is fetched and executed.

Draw on the diagram to explain how this instruction is executed and show the contents of ACC after execution.

 

100 LD■ 202

101 INC ACC

ACC

102 INC ACC

   

103 LD■ 203

 

104 INC ACC

105 LDI 203

IX

106 INC ACC

   

107 END

 
 
 

200

38

201

205

202

88

203

200

204

48

205

126

© UCLES 2013

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11

[2]

For

Examiner's

Use

9

(d) Trace this assembly language program using the trace table below. The user inputs 19
(d)
Trace this assembly language program using the trace table below.
The user inputs 19 followed by 37.
100 IN
101 INC ACC
102 STO 109
103 IN
104 INC ACC
105 ADD 109
106 STO 110
107 OUT
108 END
Memory location
ACC
109
110
Output
[5]
(e)
In (d) the program was shown in assembly language. In practice this must be machine
code in order to execute the program.

Explain how the assembler software translates a program from assembly language into machine code.

[3]

For

Examiner's

Use

© UCLES 2013

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GCE A LEVEL – May/June 2013

9691

31

3

(a)

(b)

(c)

(d)

(e)

Direct addressing / LDD

Indexed addressing / LDX

Annotation to show 203 used as a forwarding address

Accumulator contains 38

[1]

[1]

[1]

[1]

   

Memory location

ACC

109

110

19

(must be the first column entry)

0

20

 

20

 

37

   

38

   

58

 

58 /ft

Output 58 /ft
Output
58 /ft

1 mark for each of the emboldened numbers in the correct column and sequence

[MAX 5]

Labels added to a (symbol) table // creates a list of addresses

Labels are later looked up to determine the actual address / Assembler must allocate addresses to labels

Mnemonic looked up to give binary code/machine code

Macro instructions are expanded into a group of instructions

The software makes two passes through the source program

[1]

[1]

[1]

[1]

[1]

[MAX 3]

[Total: 12]

© Cambridge International Examinations 2013

13

6

3 The table shows the assembly language instructions for a processor which has one general purpose register – the Accumulator (ACC), and an index register (IX).

Instruction

 

Op Code

Operand

Explanation

LDD

<address>

Direct addressing. Load the contents of the given address to ACC

STO

<address>

Store the contents of ACC at the given address

LDI

<address>

Indirect addressing. At the given address is the address to be used. Load the contents of this second address to ACC

LDX

<address>

Indexed addressing. Form the address as <address> + the contents of IX. Copy the contents of this address to ACC

LIX

<address>

Load the contents of the given address to IX

INC

<register>

Add 1 to the contents of the register (ACC or IX)

ADD

<address>

Add the contents of the given address to the contents of ACC

OUT

Output the contents of ACC (as a denary number) to the monitor

IN

Input a denary number from the keyboard and store in ACC

JMP

<address>

Jump (unconditionally) to the given address

END

End the program and return to the operating system

The diagrams on the next page show a program loaded in main memory starting at address

100.

Two of the op-codes have been partially blanked out.

Locations 200 onwards contain data which is used by the program.

© UCLES 2013

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For

Examiner's

Use

7

(a)

The instruction at address 100 is fetched and executed. Shown are the contents of the registers after execution.

 

100 LD■ 202

101 INC ACC

 

ACC

 

102 INC ACC

 

42

103 LD■ 203

 

104 INC ACC

105 LDD 204

 

IX

106 INC ACC

 

3

 

107 END

 
 
 

200

38

201

205

202

88

203

200

204

48

205

42

 

Which mode of addressing was used by this load instruction at address 100?

[1]

(b)

The instruction at address 103 is fetched. Shown are the contents of the registers after execution.

 

100 LD■ 202

101 INC ACC

ACC

102 INC ACC

38

 

103 LD■ 203

 

104 INC ACC

105 LDD 204

IX

106 INC ACC

3

 

107 END

 
 
 

200

38

201

205

202

88

203

200

204

48

205

42

Draw on the memory diagram to explain how this instruction works. Which mode of addressing was used by this load instruction at address 103?

[2]

For

Examiner's

Use

© UCLES 2013

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[Turn over

8

(c)

Refer to the program used in (a) and (b). The instruction at address 105 is fetched and executed.

Show the contents of ACC after execution.

 
 

ACC

IX

 

[1]

(d)

Trace the first two iterations of this assembly language program using the trace table below.

© UCLES 2013

100

LIX

120

101

LDX

200

102

INC

ACC

103

OUT

104

INC

IX

105

JMP

101

 

120

0

200

165

201

93

202

107

ACC

0 … … 200 165 201 93 202 107 ACC IX 9691/33/M/J/13 16 Output [4] For

IX

0 … … 200 165 201 93 202 107 ACC IX 9691/33/M/J/13 16 Output [4] For

9691/33/M/J/13

16

Output

0 … … 200 165 201 93 202 107 ACC IX 9691/33/M/J/13 16 Output [4] For

[4]

For

Examiner's

Use

9

(e) In (d) the program was shown in assembly language. In practice this must be machine code in order to execute the program.

Explain how the assembler software translates a program from assembly language into machine code.

[3]

For

Examiner's

Use

© UCLES 2013

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Syllabus

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GCE A LEVEL – May/June 2013

9691

33

3

(a)

Indexed addressing // LDX

[1]

(b)

Indirect addressing Annotation to explain that address 203 is used as a forwarding address

[2]

(c)

48

[1]

(d)

 

ACC

IX

Output

0 165 166 166 1 93 94 94 (2)
0
165
166
166
1
93
94
94
(2)
 

Mark as follows:

Index register contain 0

[1]

Sequence of first box (or subsequent sequence for the same instructions)

[1]

Index register contains 1

[1]

Sequence for final box

[1]

 

(e)

Labels added to a (symbol) table // creates a list of addresses

[1]

Labels are later looked up to determine the actual address / Assembler must allocate

addresses to labels

[1]

Mnemonic looked up to give binary code/machine code

[1]

Macro instructions are expanded into a group of instructions

[1]

The software makes two passes through the source program

[1]

MAX 3

[Total: 11]

© Cambridge International Examinations 2013

18

6

3

(a)

Describe what is meant by a register.

 
 

[2]

 

(b)

(i)

Convert the denary number 60 into hexadecimal.

[1]

 

(ii)

Convert the hexadecimal number 10F into denary.

[1]

© UCLES 2013

9691/32/O/N/13

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For

Examiner's

Use

7

(iii) Why do computer scientists often write binary numbers in hexadecimal? For Examiner's Use [1]
(iii) Why do computer scientists often write binary numbers in hexadecimal?
For
Examiner's
Use
[1]
(c) The diagram shows a program loaded into main memory starting at memory address
30 Hex.
Address
Main memory
(contents shown in
Hex.)
30
2150
31
A351
32
A552
33
FFFF
58
003C
59
103C
5A
010B
(i)
How many bytes are used to store each program instruction?
[1]
(ii)
Describe the steps in the fetch stage of the fetch-execute cycle.
Refer to the instruction at address 30 to illustrate your answer.
[5]
© UCLES 2013
9691/32/O/N/13
[Turn over

20

8

(d) The following table shows some of a processor’s instruction set in assembly language.

Instruction

 

Op Code

Operand

Explanation

LIX

<address>

Load the contents of the address to the Index register (IX)

LDX

<address>

Indexed addressing. Form the address as <address> + the contents of IX. Copy the contents of this address to ACC

STO

<address>

Store the contents of ACC at the given address

ADD

<address>

Add the contents of the given address to the ACC

INC

<register>

Add 1 to the contents of the register (ACC or IX)

JMP

<address>

Jump to the given address

The following program is to be executed. Shown are:

the first six instructions of this program

the memory locations which will be accessed by this program.

Main memory

Address

contents

100

LIX

200

101

LDX

200

102

ADD

204

103

STO

204

104

INC IX

105

JMP

101

200 102 ADD 204 103 STO 204 104 INC IX 105 JMP 101 200 1 201
200 102 ADD 204 103 STO 204 104 INC IX 105 JMP 101 200 1 201

200

1

201

13

202

14

203

22

204

0

© UCLES 2013

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For

Examiner's

Use

9

Complete the trace table below for three iterations of the loop.

Show each change to the contents of the registers and memory location 204.

© UCLES 2013

ACC

of the registers and memory location 204. © UCLES 2013 ACC IX 9691/32/O/N/13 22 Main memory

IX

9691/32/O/N/13

22

Main memory

address 204

0
0

[4]

For

Examiner's

Use

[Turn over

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GCE A LEVEL – October/November 2013

9691

32

3

(a)

Temporary storage location

[1]

 

general purpose/special (purpose)

[1]

Inside the (micro)processor

[1]

 

MAX 2

 

(b)

(i)

3C

[1]

 

(ii)

271

[1]

(iii)

Fewer digits used to represent any number // long string difficult to interpret

[1]

 

Less likely to make a mistake when copying/converting a digit string

[1]

Easy to convert from binary to hex (vice versa) than binary to denary

[1]

 

MAX 1

R. Hex is easier to understand/write

© Cambridge International Examinations 2013

23

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GCE A LEVEL – October/November 2013

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32

(c)

(i)

2 bytes

 

(ii)

The Program Counter contains 30

 

MAR

← [PC]

// MAR given the contents of the PC

PC ← [PC] + 1 // PC is incremented

MDR

← [[MAR]] // The contents of the address in MAR is copied to MDR

CIR ← [MDR]

// The contents of MDR are copied to CIR

OR … If the candidate’s answer uses the suggested instruction:

The Program Counter contains 30 PC contents are copied to MAR PC contents are incremented to 31 The contents of address 30 / 2150 is copied to MDR MDR contents / 2150 is copied to CIR

(d)

Memory

Address

ACC IX 204 1 0 13 (13) 13 / ft 2 14 27 27 3
ACC
IX
204
1
0
13
(13)
13 / ft
2
14
27
27
3
22
49
49
4

[1]

[1]

[1]

[1]

[1]

[1]

[1]

[1]

[1]

[1]

[1]

MAX 5

[4]

[Total: 15]

© Cambridge International Examinations 2013

24

6

3

(a)

Most modern computers are designed using Von Neumann architecture.

 
 

Explain what is meant by Von Neumann architecture.

 

[2]

 

(b)

(i)

Convert the hexadecimal number 7A to denary.

[1]

 

(ii)

Convert the binary number 0101 1100 to hexadecimal.

[1]

© UCLES 2013

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For

Examiner's

Use

7

(iii) Why do computer scientists often write binary numbers in hexadecimal?

[1]

(c) The diagram shows a program loaded into main memory starting at memory address 7A Hex.

Address

Main memory (contents shown in Hex.)

7A

2150

7B

A351

7C

A552

7D

FFFF

Address Main memory (contents shown in Hex.) 7A 2150 7B A351 7C A552 7D FFFF 90
Address Main memory (contents shown in Hex.) 7A 2150 7B A351 7C A552 7D FFFF 90

90

003C

(i) How many bits are used for each main memory location?

[1]

The trace table below is used to show how the contents of the special-purpose registers change as the program is executed. The steps in the fetch stage of the fetch-execute cycle are shown in the first column using register transfer notation. (For example, MAR ← [PC] means the content of the Program Counter is copied to the Memory Address Register.)

(ii) Complete the trace table for the fetching of the first program instruction (2150):

Show the changing contents of the registers

Put a tick in the Address bus/Data bus column to show when the signals on that bus change.

Fetch

Special purpose registers (Contents shown in Hex.)

Buses

stage

PC

MAR

MDR

CIR

Address bus

Data bus

 

7A

         

MAR ← [PC]

           

PC ← [PC] + 1

           

MDR ← [[MAR]]

           

CIR ← [MDR]

           

[5]

For

Examiner's

Use

© UCLES 2013

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26

[Turn over

8

(d) The following table shows some of a processor’s instruction set in assembly language.

Instruction

 

Op Code

Operand

Explanation

LDD

<address>

Direct addressing. Load the contents of the given address to ACC

LDI

<address>

Indirect addressing. At the given address is the address to be used. Load the contents of this second address to ACC

LIX

<address>

Load the contents of the address to the Index register (IX)

LDX

<address>

Indexed addressing. Form the address as <address> + the contents of IX. Copy the contents of this address to ACC

The following program is to be executed. Shown are:

the first four instructions only of this program

the memory locations which are accessed by this program.

Address

Main memory

100

LIX

200

101

LDD

201

102

LDI

201

103

LDX

201

200 101 LDD 201 102 LDI 201 103 LDX 201 200 3 201 216 202 99
200 101 LDD 201 102 LDI 201 103 LDX 201 200 3 201 216 202 99

200

3

201

216

202

99

203

217

204

63

LDD 201 102 LDI 201 103 LDX 201 200 3 201 216 202 99 203 217
LDD 201 102 LDI 201 103 LDX 201 200 3 201 216 202 99 203 217

216

96

217

97

Complete the trace table below for the first four program instructions. Show each change in the contents of the registers.

 

Register

Instruction

Accumulator (ACC)

Index Register (IX)

LIX

200

   

LDD

201

   

LDI

201

   

LDX

201

   

© UCLES 2013

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[4]

For

Examiner's

Use

Page 3

Mark Scheme

Syllabus

Paper

 

GCE A LEVEL – October/November 2013

9691

31

3

(a)

a single processor

 
 

program consists of a sequence of stored instructions

[1]

Instructions + data

[1]

are stored (in a continuous block) of primary/main memory

[1]

instructions are executed in sequence

[1]

 

MAX 2

 

(b)

(i)

122

[1]

 

(ii)

5C

[1]

(iii)

Fewer digits used to represent any number // long string difficult to interpret

[1]

 

Less likely to make a mistake when copying/converting a digit string

[1]

Easy to convert from binary to hex (vice versa) than binary to denary

[1]

 

MAX 1

© Cambridge International Examinations 2013

28

Page 4 Mark Scheme Syllabus Paper GCE A LEVEL – October/November 2013 9691 31 (c)
Page 4
Mark Scheme
Syllabus
Paper
GCE A LEVEL – October/November 2013
9691
31
(c)
(i)
16 bits
[1]
(ii)
Fetch
Special purpose registers
Busses
stages
Address
PC
MAR
MDR
CIR
Data bus
bus
7A
MAR ← [PC]
7A
PC ← [PC] + 1
7B
2150
MDR ←[[MAR]]
CIR ← [MDR]
2150
For the buses column penalise once for any additional incorrect ticks
MAX 5
(d)
 

Register

Instruction

Accumulator

Index Register

(ACC)

(IX)

LIX

200

 

3

LDD

201

216

 

LDI

201

96

 

LDX

201

63

 

1 per contents

[4]

[Total: 15]

© Cambridge International Examinations 2013

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6

3

(a)

Describe what is meant by a register.

 

For

 

Examiner's

Use

 

[2]

 

(b)

(i)

Convert the hexadecimal number 7F into denary.

[1]

 

(ii)

Convert the denary number 291 into hexadecimal.

[1]

 

(iii)

Why do computer scientists often write binary numbers in hexadecimal?

 

[1]

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7

(c) The diagram shows a program loaded into main memory starting at memory address 40 Hex.

Address

Main memory (Contents shown in Hex.)

40

7324

41

A351

42

A552

43

FFFF

Main memory (Contents shown in Hex.) 40 7324 41 A351 42 A552 43 FFFF 68 003C
Main memory (Contents shown in Hex.) 40 7324 41 A351 42 A552 43 FFFF 68 003C

68

003C

69

103C

6A

010B

(i) How many bytes are used to store each program instruction? [1] (ii) Describe the
(i)
How many bytes are used to store each program instruction?
[1]
(ii)
Describe the steps in the fetch stage of the fetch-execute cycle.
Use the instruction at address 40 to illustrate your answer.
[5]

For

Examiner's

Use

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[Turn over

8

(d) The following table shows some of a processor’s instruction set in assembly language.

Instruction

 

Op Code

Operand

Explanation

LDD <address>

Direct addressing. Load the contents of the given address to ACC

LDI <address>

Indirect addressing. At the given address is the address to be used. Load the contents of this second address to ACC

STO <address>

Store the contents of ACC at the given address

ADD <address>

Add the contents of the given address to the ACC

INC <register>

Add 1 to the contents of the register (ACC or IX)

JMP <address>

Jump to the given address

The following program is to be executed. Shown are:

the first seven instructions in this program

the memory locations which will be accessed by this program.

Address

Main memory

130

LDI 160

131

ADD 153

132

STO 153

133

LDD 160

134

INC ACC

135

STO 160

136

JMP 130

STO 153 133 LDD 160 134 INC ACC 135 STO 160 136 JMP 130 150 13
STO 153 133 LDD 160 134 INC ACC 135 STO 160 136 JMP 130 150 13

150

13

151

23

152

11

153

0

STO 153 133 LDD 160 134 INC ACC 135 STO 160 136 JMP 130 150 13
STO 153 133 LDD 160 134 INC ACC 135 STO 160 136 JMP 130 150 13

160

150

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For

Examiner's

Use

9

Complete the trace table below for two iterations of the loop. Show each change in the contents of the register and memory locations.

Register Memory location ACC 153 160 0 150
Register
Memory location
ACC
153
160
0
150

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[4]

For

Examiner's

Use

[Turn over

Page 3

Mark Scheme

Syllabus

Paper

 

GCE A LEVEL – October/November 2013

9691

33

3

(a)

Temporary storage location

 

[1]

 

Inside the (micro)processor

[1]

 

(b)

(i)

127

[1]

 

(ii)

123

[1]

(iii)

less digits used to represent any number

[1]

 

Less likely to make a mistake when copying/converting a digit string

[1]

Easy conversion between binary and hex (vice versa) than binary and denary

[1]

 

MAX 1

 

(c)

(i)

2 bytes

 

[1]

 

(ii)

MAR

← [PC]

// MAR given the contents of the PC

[1]

 

PC ← [PC] + 1 // PC is incremented

[1]

MDR

← [[MAR]] // The contents of the address in MAR is copied to MDR

[1]

CIR ← [MDR]

// The contents of MDR are copied to CIR

[1]

OR, if the candidate uses the suggested instruction …. MAR is given value 40 // PC contents of 40 are copied to MAR

[1]

7324/The contents of address 40 is copied to the MDR

[1]

PC is incremented from 40 to 41

[1]

7324/contents of location 40 is copied to CIR

[1]

 

MAX 5

© Cambridge International Examinations 2013

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Page 4

Mark Scheme

Syllabus

Paper

GCE A LEVEL – October/November 2013

9691

33

(d)

Memory address ACC 153 160 13 0 13 13 150 151 151 23 36 36
Memory address
ACC
153 160
13
0
13
13
150
151
151
23
36
36
151
152
152

[4]

[Total: 15]

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