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CMR Institute of Technology, Bangalore

Department: ELECTRONICS & COMMUNICATION ENGINEERING


Semester: 05

Section(s): B & C

Fundamentals of CMOS VLSI

10EC56

Lectures/week: 05

Course Instructor: SUNIL KUMAR K H


Course duration:

Jul 2015 Dec 2015

Unit1: BASIC MOS TECHNOLOGY


Integrated circuits era. Enhancement and depletion mode MOS transistors. nMOS fabrication.
CMOS fabrication. Thermal aspects of processing. BiCMOS technology. Production of E-beam
masks
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Distinguish between enhancement and depletion mode operation of MOSFETs


Explain with diagrams, the main steps in the twin-tub process.
Compare CMOS and Bipolar technologies.
Explain with structure the step-by-step flow of n-well fabrication process.
Write the steps ivolved in production of E-beam masks.
Describe in detail BiCMOS fabrication in n-well process.
What are the advantages of BiCMOS process over CMOS technology?
Describe in detail step-by-step procedure of the P-well CMOS fabrication process and write
the mask sequence.
9 Explain the nMOS fabrication process with neat diagrams.
10 Discuss the difference in thermal sequence between nMOS and CMOS process.
11 How many mask layers are required in a basic nMOS process? Explain the function of each
of these masks.
MOS TRANSISTOR THEORY
Introduction, MOS Device Design Equations, The Complementary CMOS Inverter DC
Characteristics, Static Load MOS Inverters, The Differential Inverter, The Transmission Gate,
Tristate Inverter.

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List the expression for threshold voltage of an nMOS transistor and narrate the significance
of each term in this equation.
Derive the expression for Vin(switching point voltage) in the region C of CMOS inverter.
Calculate the threshold voltage with
= 11.7 ,
= 3.9 for an nMOS transistor with
=2
,
= 190 . Assume
= 0.85,
= 0, = 1.45
.
Discuss the effect of channel length modulation on the performance of an nMOS transistor.
Define noise margin for both high and low levels.
What do you mean by static load inverters? Derive the output voltage for the pseudo inverter
by discussing its DC transfer characteristics.
In a 0.5
process
= 44.69
,
= 14.1
and the
= . The nMOS has
= 0.71 and
= 1.5 . At what levels of
,will the MOSFET reach pinch off
mode? Hint: (
= 3.9 )
What is the functionality of the circuit shown in figure below? Is it correct method to connect
the circuit as shown in figure? Justify your answer.

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Draw the CMOS circuit for half adder. (Hint:


= , carry = AB Inverted inputs are
allowed)
Explain the design equations of MOS devices and VI characteristics for n and p devices.
A nMOS transistor has a threshold voltage of 0.75V, the body effect co-efficient equal to
0.54 compute the threshold voltage for
= 5 and 2
= 0.6 .
What is body effect? Which parameters are responsible for it?
An nMOS transistor is operating in active region with following parameters
=
3.9 ,
=1 ,
= 100,
= 90 / . Find and drain to source resistance.
Explain in detail regions of operation and mid-point voltage equation for CMOS inverter
Explain the CMOS inverter transfer characteristics highlighting the region of operation of the
MOS transistors.
Explain the transfer plot of CMOS inverter with necessary expression for Vout in each region
Write a note on transmission gate.
Explain the influence of / on the DC transfer characteristics of inverter.
Explain the working of enhancement mode transistor with neat nMOSFET structures at
different conditions of applied voltages. Also draw the output characteristics and identify the
different regions of operation.
What is a noise margin? Obtain the values of VIL, VOL, VIH and VOH from transfer
characteristics of a typical inverter.
Explain the nMOS enhancement mode transistor for different conditions of Vgs and Vds.
What is a tristate inverter? Explain.

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23 Derive the CMOS-inverter dc characteristics graphically, from p-device & n-device characteristics

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and show all operating regions.


Define noise margin. Calculate the noise margins for the transfer characteristic of typical
inverter, shown in figure

25 Explain briefly the circuit operation of a basic differential inverter and a Tristate inverter.
26 List the threshold voltage equations and emphasize each of them.

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Unit2: CIRCUIT DESIGN PROCESSES


MOS layers. Stick diagrams. Design rules and layout lambda-based design and other rules.
Examples. Layout diagrams. Symbolic diagrams. Tutorial exercises.
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List the color, stick encoding, mask layout encoding and CIF layers for the following layers
used in VLSI technology : i) n - diffusion ii) Poly silicon iii) Metal 1 iv) Impact
Write the stick diagram for a parity generator using nMOS logic.
Draw the circuit diagram for the layout diagram shown in figure

What are the basic layers of MOS circuit?


What are the different MOS layers? Draw the based design rules for layers and transistor.
List based design rules for CMOS.
Draw the stick diagram for nMOS EX-OR gate.
What is transmission gate? And design stick diagram for transmission gate.
With neat diagram, explain based design rules for diffusion layers, metal layers, contact
cuts and Vias.
Write a note on double metal MOS process rules for contact cut.
Draw the cross section of buried contact. What are the advantages of lambda based design
rule?
With neat diagrams, explain based design rules for pMOS, nMOS and nMOS depletion
mode transistor.
List the color, stick encoding, and mask layout encoding layers for a simple metal nMOS
process.

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14 What is -based design? What are the merits and demerits?


15 Obtain the stick diagram and layout of a two-way selector with enable.
16 Distinguish burried and butting contacts with suitable diagrams.
17 Draw -based design rules for double metal CMOS process for layers and transistors.
BASIC PHYSICAL DESIGN OF SIMPLE LOGIC GATES
1 Write the layout for the logic expression =
+
using CMOS design.
2 Draw the circuit and stick diagram of two input NAND gate using CMOS logic, use standard
colour or monochrome codes.
3 Draw the stick diagram for the nMOS implementation of the Boolean expression =
+

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Draw the circuit and stick diagram of two input NOR gate using CMOS logic, use standard
colour or monochrome codes.
5 Draw the schematic and layout for the expression Y=A+B+CD
6 Draw the stick diagram for =
+
using the nMOS design style. Explain the
procedure
Unit3: CMOS LOGIC STRUCTURES
CMOS Complementary Logic, Bi CMOS Logic, Pseudo-nMOS Logic, Dynamic CMOS Logic,
Clocked CMOS Logic, Pass Transistor Logic, CMOS Domino Logic Cascaded Voltage Switch

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Logic (CVSL).
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Realize a 2-input NAND gate for a clocked CMOS logic and also for CMOS domino logic.
Explain the working principle of dynamic CMOS logic of NAND gate.
Implement the pass transistor logic circuit for the expression Y = A + BC. Show the design
steps clearly.
Explain the Pseudo-NMOS logic, structure and their salient features with example.
Explain with the circuit the working principle of Bi-CMOS not gate and show the sub circuits
of the output voltage.
Implement the complementary CMOS and Clocked CMOS logic for the expression =
( + ) ( + ) Show the design step clearly.
With a neat circuit diagram and waveform, explain the principle of operation of a dynamic
logic and what are the advantages and disadvantages.
What is clocked CMOS logic gate? Where it is preferred?
Explain the following logic structures with their salient features of
a. BiCMOS logic; b. Pseudo-nMOS logic; c. Pass transistor logic; d. C2MOS logic
Discuss the merits and demerits of the following CMOS logic structures with a two input
NAND gate realization as an example: i) Complementary CMOS; ii) Pseudo nMOS logic; iii)
Dynamic CMOS logic.
Explain the operation of a CMOS transmission gate.
Explain domino CMOS logic with diagrams? How does it eliminate the issues related to
cascading in dynamic CMOS Logic?
What are the properties of nMOS and pMOS switches? How is transmission gate useful?
Explain the working of dynamic CMOS logic with necessary diagram and waveforms. What
are the problems encountered in this logic? Explain how CMOS domino logic eliminates the
above drawbacks with necessary diagrams.
What do you mean by pre-charge and evaluate modes in CMOS dynamic logic? Explain.
What are single rail and dual rail networks? Explain how cascade voltage switch logic(CVSL)
may be used to obtain dual-rail logic gates.

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17 Explain CMOS domain logic and derive the evaluation voltage equation.
18 Explain 2-input x-nor gate in pass transistor logic.
19 Explain the circuit of dynamic CMOS logic by taking an example of the function =
( + )( + )
20 Obtain the logical efforts and parasitic capacitance of 2-input NOR gate.
21 What is ganged CMOS logic? Explain with example. how it behave like pseudo nMOS logic,
static CMOS logic.
Unit4: BASIC CIRCUIT CONCEPTS
Sheet resistance. Area capacitances.Capacitance calculations. The delay unit. Inverter delays.
Driving capacitive loads. Propagation delays. Wiring capacitances.

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Calculate the area capacitance of a multi-layer structure shown in fig

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Given: Metal1 to substrate capacitance = 0.075(Relative capaccitance)


Polysilicon to substrate = 0.1
Narrate the steps involved in calculating the sheet resistance of: i) Transistor channels ii)
nMOS inverter iii) CMOS inverter
Derive expressions for rise time and fall time for 1:1 CMOS inverter. Also define delay time.
Derive the expression for total delay for N stage of NMOS and CMOS inverters by assuming
the width factor = .
In the circuit shown in figure, find V1, V2, V3, V4 and V5. Justify your answer.

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Explain with circuit diagram the super buffers with inverting type and non-inverting type of
nMOS.
Two nMOS inverters are cascaded to drive capacitive load = 16 as shown in figure.
Calculate pair delay to
in terms of for the inverter geometry indicated in figure.
What are the ratios of each inverter? If strays and wirings are allowed for, it would be
reasonable to increase the capacitance to ground across the output of each inverter by 4
What is the pair delay allowing for strays? Assume = 0.1
to evaluate this pair delay

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Describe the delay unit in terms of sheet resistance and area capacitance. For the CMOS
inverter pair shown, calculate the total delay

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9 Define sheet resistance, standard unit of capacitance and delay unit of time.
10 Explain cascaded inverters to drive large capacitive loads. Obtain an equation to find number
of stages.
11 Calculate the ON resistance for nMOS inverter with
= 10K,
= 8 and
= 1.
Also estimate the total power dissipated if VDD=5V.
12 What are the possible effects of propagation delay in cascaded pass transistor chain and long
polysilicon wires?
13 What is the problem encountered in driving a large capacitive load? How this problem can be
overcome using cascaded inverters? Obtain the express ion for total delay for N stages of
nMOS and CMOS inverters in terms of width factor f and delay . What is the problem
encountered in cascaded inverters? Explain how it is overcome.
14 Calculate the area capacitance values associated with the following structure, having different
layers as shown in figure (relative C' value for polysilicon-to-substrate = 0.1 pf x 10-4/m2 and
metal1-to-substrate = 0.075 pf x 10-4/m2).

15 Prove how the delay associated with CMOS inverter pair is independent of input transitions.
16 Calculate the capacitance in Cg for the given metal layer shown in figure, if feature size = 5m and

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relative value of metal to substrate = 0.075.

17 Calculate the output of voltage Vout in the circuit given below for different values of Va, Vb

18 Consider -based design rules and 5m technology. How many nMOS 8:1 inverter
=
Assume

can be driven by a minimum size conductor which is 3 wide and 1m thick?


,

=5 .

SCALING OF MOS CIRCUITS


Scaling models and factors. Limits on scaling. Limits due to current density and noise.
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Discuss the limits of scaling on : i) Supply voltage due to noise ii) Sub threshold current
iii) Interconnects.
2 Discuss the limitations of scaling.
3 Find the scaling factors for MOS circuits: i) For gate capacitance; ii) Channel resistance(Ron);
iii) Saturation Current (Idss); iv) Speed power product (PT).
4 Discuss the following in scaling of MOS circuits:
i)
Limit of miniaturization
ii)
Limits of interconnect and contact resistance
5 What are the scaling factors of
i)
Parasitic capacitance Cx
ii)
Power dissipation per unit area Pa
iii)
Current density J
iv)
Gate capacitance Cg
v)
Gate capacitance per unit area
vi)
Max. operating frequency f0
vii)
Gate area
viii) Gate delay
ix)
Saturation current
x)
Carrier density in the channel.
6 Explain in brief the wiring capacitances.
Unit5: CMOS SUBSYSTEM DESIGN
Architectural issues. Switch logic. Gate logic. Design examples combinational logic. Clocked
circuits. Other system considerations.
1 Discuss the architectural issues to be followed in the design of a VLSI subsystem.
2 Design 4: I MUX using transmission gates.
3 Design a 4:1 multiplexer using nmos logic and CMOS logic.
4 Design bus arbitration logic for n-line bus.

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Describe switch and CMOS logic implementation for two input Ex-OR gate.
Design a parity generator with following specifications and draw the stick diagram for one
basic cell.

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Explain the dynamic two bit shift register circuit using NMOS and CMOS logic.
Explain how to implement the switch logic of four way multiplexer using transmission gate.
Explain the dynamic four bit shift register circuit using NMOS and CMOS logic.
What are the two basic ways of building logic circuits? Explain each of them with an
example each. Mention their advantages and disadvantages.
11 When do you prefer to use MOS transistor drivers over bipolar drivers? Which are the three
classes of MOS transistor bus systems? Explain each of them with essential diagrams.
12 Obtain the logic implementation of 4-way multiplexer using nmos switches.
13 Explain structured design approach for a parity generator.
14 What is structured design process? Explain.
15 Explain the restoring logic, in detail.
16 Explain the pre charge bus approach, used in system design.
17 Mention the salient features of sub system design process.
18 What are the guidelines for good VLSI design and problems associated with VLSI design?
CLOCKING STRATEGIES
1 Discuss the timing constraints for both flip flops and latches.
2 Explain NMOS and CMOS non - inverting dynamic storage cell and draw the 3 - bit shift
register using the CMOS dynamic storage cell
3 Explain two-phase clocking generator using D flip-flops.
4 Discuss the timing constraints for system timing considerations.
5 For single phase clock define following parameters:
i)
Setup time(Ts)
ii)
Hold time(Tn)
iii)
Clock to Q delay(Tq)
6 Draw the basic form of a two-phase clock generator and explain.
7 Discuss the 4 phase clocking scheme to avoid the problem of cascading in dynamic CMOS
logic.
Unit6: CMOS SUBSYSTEM DESIGN PROCESSES
General considerations. Process illustration. ALU subsystem. Adders. Multipliers.

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Discuss Baugh-Worley method used for Two's complement multiplication.


Draw and explain the 8 - bit carry select adder dividing it into m = 2 blocks. Calculate the
Completion time 'T' by assuming the one adder delay-is 4ns and one mux delay is 2ns.
Draw the block diagram and clearly show the switch connections to perform the logic
operation of "OR" and "XOR" in a 3 - bit ALU using a standard adder element.
List and explain the general consideration to be considered in CMOS design process.
Explain the implementation of ALU functions with a standard adder. Explain with the help of

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logic expressions.
Define regularity in process illustration.
Explain the design steps for 4 bit adder.
Draw the basic arrangements of 4-bit serial parallel multiplier.
Discuss the timing constraints for system timing considerations.
List and explain the general consideration to be considered in digital system design.
Explain the design of 4-bit arithmetic processor with floor plan for 4-bit data path.
What are the basic requirements of a shifter? How a cross bar switch can be used as an
shifter? Explain with an example of 4 x 4 cross bar switch. What are the drawbacks of this
basic switch and how it is overcome?
Discuss the problems associated in VLSI design.
Explain 4-bit Braun multiplier with neat diagram
Write MOS switch implementation of 4x4 crossbar switch.
Realize a 4 x 4 barrel shifter using MOS switches and explain in brief its salient features.

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17 Discuss on a serial-parallel multiplier approach used in adder.
18 Explain booth multiplier with an example.
19 What are the adder enhancement techniques? Briefly explain.
20 Write and explain 6-bit carry select adder
21 Draw the Manchester carry-chain element with expression for inputs and outputs.
Unit7: MEMORY, REGISTERS AND CLOCK
Timing considerations. Memory elements. Memory cell arrays.

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Explain the working of 3T DRAM cell with circuit and stick diagrams.
Explain four transistor dynamic and six transistor static memory cells. Reason out the need
for sense amplifier in the cell array.
3 Explain the CMOS pseudo-static D flip-flop.
4 What is multiplexed D flip-flop? Explain the general method for testing with scan path
approach.
5 Discuss the important factors of system timing consideration.
6 Draw the circuit and stick diagram. Explain nMOS pseudo-static memory cell.
7 How to read or write and hold the bit in SRAM cell?
8 Explain the working of 1-transistor DRAM cell with schematic and stick diagram. Give the
difference between SRAM and DRAM.
9 Draw one-transistor dynamic memory cell circuit arrangement. What is the significance of
creating capacitor by using a polysilicon plate over the diffusion area?
10 Explain six transistor static CMOS memory cell arrangement.
Unit8: TESTABILITY
Performance parameters. Layout issues. I/O pads. Real estate. System delays. Ground rules for
design. Test and testability.

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Discuss the meaning of "REAL ESTATE" in VLSI design.


Narrate the meaning of controllability and observability in VLSI chip testing.
What are the three important steps in sensitized path based testing?
Find the test vectors to detect the stuck @ 0 and stuck @l faults of "and" gate at its input and
output node.

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Write short notes on :


a. I/O Pads
b. Test and testability
c. LSSD
d. BIST
What are the different types of I/O Pads?
List the ground rules for a system design.
Write short notes on :
a. Latch up phenomenon
b. BiCMOS circuit
c. Nature of failures in CMOS.
Discuss the requirements of I/O pads in a chip.
Write a note on scan design technique.
Explain the sensitized path based testing applied to combinational logic as an example
Explain the concept of system partitioning in VLSI chip testing.
Discuss the difficulties encountered in testing sequential logic with an example.
Write short notes on Boundary scan test (BST).

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