1.

4-TO-2 PRIORITY ENCODE

AIM: To implement 4-t0-2 priority encoder using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM: LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY pri_enc IS
port(a,b,c,d:in std_logic;s:out std_logic_vector(1 downto 0));
END ENTITY pri_enc;
architecture pr_en of pri_enc is
begin
process(a,b,c)
begin
if a='1' then
s<="00";
elsif b='1' then
s<="01";
elsif c='1' then
s<="10";
else s<="11";
end if;
end process;
end pr_en;

SIMULATION RESULT:

SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format
Optimization Goal
Keep Hierarchy
Target Technology
Macro Preserve
XOR Preserve
Clock Enable

: pri_enc.ngr
: pri_enc
: NGC
: Speed
: YES
: Automotive 9500XL
: YES
: YES
: YES

# IOs

:6

Design Statistics
Cell Usage :
# BELS
#
AND2
#
INV
#
OR2
# IO Buffers

:7
:2
:4
:1
:5

#
IBUF
#
OBUF
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.89 secs
Total memory usage is 157432 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

:3
:2

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

RESULT:
4-t0-2 encoder is designed and implemented.

2. 8 INTO 3 ENCODER
AIM: To implement 8 into 3 encoder using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM: LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ENCODER8_3 IS
PORT ( ENABLE: IN STD_LOGIC;
D_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
D_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );
END ENCODER8_3;
ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS
BEGIN
PROCESS(ENABLE,D_IN)
BEGIN
IF ( ENABLE = '1') THEN
D_OUT <= "000";
ELSE
CASE D_IN IS
WHEN "00000001" => D_OUT <= "000";
WHEN "00000010" => D_OUT <= "001";
WHEN "00000100" => D_OUT <= "010";
WHEN "00001000" => D_OUT <= "011";
WHEN "00010000" => D_OUT <= "100";
WHEN "00100000" => D_OUT <= "101";
WHEN "01000000" => D_OUT <= "110";
WHEN OTHERS => D_OUT <= "111";
--WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END ENCODER_ARCH;

SIMULATION RESULTS:

SYNTHESIS REPORT
Final Results
RTL Top Level Output File Name : ENCODER8_3.ngr
Top Level Output File Name
: ENCODER8_3
Output Format
: NGC
Optimization Goal
: Speed

Keep Hierarchy
: YES
Target Technology
: Automotive 9500XL
Macro Preserve
: YES
XOR Preserve
: YES
Clock Enable
: YES
wysiwyg
: NO
Design Statistics
# IOs
: 12
Cell Usage :
# BELS
: 59
#
AND2
: 21
#
INV
: 15
#
OR2
: 16
#
OR3
:7
# IO Buffers
: 12
#
IBUF
:9
#
OBUF
:3
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.72 secs
Total memory usage is 157432 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
RTL SCHEMATIC

TECHNOLOGY SCHEMATIC:

RESULT:
8 into 3 encoder is designed and implemented.

3. ASYNCHRONOUS COUNTER
AIM: To implement Asynchronous counter using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM: library IEEE;
use IEEE.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
entity syn_counter is
port (
CLK: in STD_LOGIC;
RESET,CE, load, DIR: in STD_LOGIC;
DIN: in std_logic_vector(3 downto 0);
COUNT: out std_logic_vector(3 downto 0));
end syn_counter;
architecture Behavioral of syn_counter is
signal count1: std_logic_vector(3 downto 0);
begin
process( reset, clk) begin
if(reset = '1') then count1 <= "0000";
else
if(clk'event and clk = '1') then
if(load = '1') then count1 <= din;
else
if(ce = '1') then
if( dir = '1') then
count1 <= count1 +1;
else
count1 <= count1 -1;
end if;
end if;
end if;
end if;
end if;
end process;
COUNT<=count1;
end Behavioral;

SIMULATION RESULTS

SYNTHESIS REPORT
Final Results
RTL Top Level Output File Name

: syn_counter.ngr

Top Level Output File Name

: syn_counter
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: YES
Target Technology
: Automotive 9500XL
Macro Preserve
: YES
XOR Preserve
: YES
Clock Enable
: YES
wysiwyg
: NO
Design Statistics
# IOs
: 13
Cell Usage :
# BELS
: 35
#
AND2
: 10
#
AND3
:1
#
AND4
:1
#
INV
:8
#
OR2
:8
#
OR3
:1
#
XOR2
:6
# FlipFlops/Latches
:4
#
FDCE
:4
# IO Buffers
: 13
#
IBUF
:9
#
OBUF
:4
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.75 secs
Total memory usage is 158456 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

RESULT:
Asynchronous counter is designed and implemented.

4. RANDOM COUNTER
AIM: To implement Random counter using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity random is
generic ( width : integer := 32 );
port ( clk : in std_logic;
random_num : out std_logic_vector (width-1 downto 0) );
end random;
architecture Behavioral of random is
begin
process(clk)
variable rand_temp : std_logic_vector(width-1 downto
0):="10000000000000000000000000000000";
variable temp : std_logic := '0';
begin
--if(clk'event and clk='1') then
if(rising_edge(clk)) then
temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1):= rand_temp(width-2 downto 0);
rand_temp(0) := temp;
end if;
random_num <= rand_temp;
end process;
end architecture;
SIMULATION RESULTS:

SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : random.ngr
Top Level Output File Name
: random
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: YES
Target Technology
: Automotive 9500XL
Macro Preserve
: YES
XOR Preserve
: YES
Clock Enable
: YES
wysiwyg
: NO

Design Statistics
# IOs

: 33

Cell Usage :
# BELS
:1
#
XOR2
:1
# FlipFlops/Latches
: 32
#
FD
: 32
# IO Buffers
: 33
#
IBUF
:1
#
OBUF
: 32
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 2.95 secs
Total memory usage is 127088 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
RTL SCHEMATICS:

TECHNOLOGY SCHEMATIC:

RESULT:
Random counter is designed and implemented.

5. Random Access Memory(RAM)

AIM: To implement Random Access Memory using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM1 is
port ( clk : in std_logic;
enr : in std_logic; --enable read,should be '0' when not in use.
enw : in std_logic; --enable write,should be '0' when not in use.
addr_in : in std_logic_vector( 15 downto 0);
addr_out : in std_logic_vector( 15 downto 0);
dataout : out std_logic_vector(3 downto 0); --output data
datain : in std_logic_vector (3 downto 0) );
end RAM1;
architecture ram of RAM1 is
type memory_type is array (0 to 15) of std_logic_vector(3 downto 0);
signal mem : memory_type ;
begin
process (clk)
begin
if clk'event and clk = '1' then
if (enw = '1') then
mem( conv_integer( addr_in)) <= datain ;
elsif(enr ='1') then
dataout <= mem( conv_integer( addr_out)) ;
end if ;
end if;
end process;
end ram;

SIMULATION RESULTS:

SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : RAM1.ngr
Top Level Output File Name
: RAM1
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: YES

Target Technology
: Automotive 9500XL
Macro Preserve
: YES
XOR Preserve
: YES
Clock Enable
: YES
wysiwyg
: NO
Design Statistics
# IOs
: 43
Cell Usage :
# BELS
: 562
#
AND2
: 172
#
AND3
: 11
#
AND4
: 12
#
AND8
: 21
#
GND
:1
#
INV
: 285
#
OR2
: 60
# FlipFlops/Latches
: 68
#
FDCE
: 68
# IO Buffers
: 31
#
IBUF
: 27
#
OBUF
:4
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.52 secs
Total memory usage is 128112 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

RESULT:
Random access memory is designed and implemented.

6. ARITHMETIC LOGIC UNIT(ALU)

AIM: To implement Arithmetic logic unit(ALU) using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit IS
port(a, b : in std_logic_vector(7 downto 0); -- a and b are busses
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
f : out std_logic_vector(7 downto 0));
END alu8bit;
architecture behavioral of alu8bit is
begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "001" =>
temp := a or b;
when "010" =>
temp := not a;
when "011" =>
temp := a xor b;
when "100" =>
temp := a + b;
when "101" =>
temp := a - b;
when "110" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
f <= temp;
end process;
end behavioral;

SIMULATION RESULTS:

SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : alu8bit.ngr
Top Level Output File Name
: alu8bit
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: YES
Target Technology
: Automotive 9500XL
Macro Preserve
: YES
XOR Preserve
: YES
Clock Enable
: YES
wysiwyg
: NO

Design Statistics
# IOs

: 28

Cell Usage :
# BELS
#
AND2
#
AND3
#
AND8
#
INV
#
OR2
#
OR3
#
OR4
#
XOR2
# IO Buffers
#
IBUF
#
OBUF

: 304
: 101
: 12
:1
: 99
: 58
:9
:1
: 23
: 28
: 19
:9

Total REAL time to Xst completion: 2.00 secs

Total CPU time to Xst completion: 2.88 secs
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

RESULT:
8-bit arithmetic logic unit is designed and implemented.

7. FINITE STATE MACHINE (FSM) ELEVATOR

AIM: To implement finite state machine (FSM) elevator using VHDL.
APPARATUS: Personal computer
Xilinx 10.1 software
PROGRAM: library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity fsm_elv is
port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
fcr:in std_logic_vector(1 downto 0);
elv_pos:out std_logic_vector(1 downto 0));
end fsm_elv;
Architecture sig_arc of fsm_elv is
signal elv_pos1:std_logic_vector(1 downto 0):="00";
begin
process(clk,reset,fcr)
begin
if clk'event and clk='1' then
if reset = '1' then
elv_pos1<="00";
else
if (fcr>elv_pos1) then
elv_pos1<=elv_pos1+1;
elsif (fcr<elv_pos1) then
elv_pos1<=elv_pos1-1;
else
elv_pos1<=elv_pos1;
end if;
end if;
end if;
end process;
elv_pos<=elv_pos1;
end sig_arc;

SIMULATION RESULTS:

SYNTHESIS REPORT:
Final Results
RTL Top Level Output File Name : fsm_elv.ngr
Top Level Output File Name
: fsm_elv
Output Format
: NGC
Optimization Goal
: Speed
Keep Hierarchy
: YES
Target Technology
: Automotive 9500XL
Macro Preserve
: YES
XOR Preserve
: YES

Clock Enable
wysiwyg

: YES
: NO

Design Statistics
# IOs

:6

Cell Usage :
# BELS
#
AND2
#
AND3
#
GND
#
INV
#
OR2
#
XOR2
# FlipFlops/Latches
#
FDCE
# IO Buffers
#
IBUF
#
OBUF

: 32
:7
:2
:1
: 14
:6
:2
:2
:2
:6
:4
:2

Total REAL time to Xst completion: 2.00 secs

Total CPU time to Xst completion: 2.59 secs
Total memory usage is 126064 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

RESULT:
Finite state machine(FSM) elevator is designed and implemented.