Green Card

z/Architecture
IBM
Reference Summary
SA22-7871-00
z/Architecture
IBM
Reference Summary
SA22-7871-00
First Edition (September 2001)

References in this publication to IBM products, programs, or services do not imply that IBM intends to make these available in all
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program product in this publication is not intended to state or
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IBM may use or distribute whatever information you supply in any
way it believes appropriate without incurring any obligation to you.
Copyright International Business Machines Corporation
2001. All rights reserved.
US Government Users Restricted Rights Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp.
Preface
This publication is intended primarily for use by
z/Architecture assembler-language application programmers.
It contains basic machine information summarized from the
IBM z/Architecture Principles of Operation, SA22-7832, about
the zSeries processors. It also contains frequently used
information from IBM ESA/390 Common I/O-Device Commands and Self Description, SA22-7204, IBM System/370
Extended Architecture Interpretive Execution, SA22-7095, and
IBM High Level Assembler for MVS & VM & VSE Language
Reference, SC26-4940. This publication will be updated from
time to time. However, the above publications and others
cited in this publication are the authoritative reference sources
and will be first to reflect changes.
The following instructions may be uninstalled or not available
on a particular model:
Facility
Expanded storage
Extended translation 2
Instruction
PGIN, PGOUT
CLCLU, MVCLU, PKA, PKU,
TP, TROO, TROT, TRTO,
TRTT, UNPKA, UNPKU
For information about Enterprise Systems Architecture/390

(ESA/390) architecture, refer to IBM Enterprise Systems
Architecture/390 Principles of Operation, SA22-7201, and IBM
Enterprise Systems Architecture/390 Reference Summary,
SA22-7209.
IBM, z/Architecture, zSeries, Enterprise Systems Architecture/390, and

ESA/390 are trademarks of the International Business Machines Corporation.
Copyright IBM Corp. 2001
iii
iv
z/Architecture Reference Summary
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Instruction Formats . . . . . . . . . . . . . . .
Machine Instructions by Mnemonic . . . . . . . . . . . .
Machine Instructions by Operation Code . . . . . . . . .
Condition Codes . . . . . . . . . . . . . . . . . . . . . .
Operand of Store Clock . . . . . . . . . . . . . . . . . .
Operand of Store Clock Extended . . . . . . . . . . . .
Assembler Instructions . . . . . . . . . . . . . . . . . .
Extended-Mnemonic Instructions for Branch on Condition
Extended-Mnemonic Instructions for Relative-Branch
. . . . . . . . . . . . . . . . . . . . . . .
Instructions
CNOP Alignment . . . . . . . . . . . . . . . . . . . . .
Summary of Constants . . . . . . . . . . . . . . . . . .
Fixed Storage Locations . . . . . . . . . . . . . . . . . .
External-Interruption Codes . . . . . . . . . . . . . . . .
Program-Interruption Codes . . . . . . . . . . . . . . . .
Translation-Exception Identification . . . . . . . . . . . .
Data-Exception Code (DXC) . . . . . . . . . . . . . . .
Control Registers . . . . . . . . . . . . . . . . . . . . .
Floating-Point-Control (FPC) Register . . . . . . . . . . .
Program-Status Word (PSW) . . . . . . . . . . . . . . .
z/Architecture PSW . . . . . . . . . . . . . . . . . . .
ESA/390 PSW . . . . . . . . . . . . . . . . . . . . .
Dynamic Address Translation . . . . . . . . . . . . . . .
Virtual-Address Format . . . . . . . . . . . . . . . . .
Address-Space-Control Element (ASCE) . . . . . . .
Table Values . . . . . . . . . . . . . . . . . . . . . .
Region-Table Entry (RTE) . . . . . . . . . . . . . . .
Segment-Table Entry (STE) . . . . . . . . . . . . . .
Page-Table Entry (PTE) . . . . . . . . . . . . . . . .
ASN Translation . . . . . . . . . . . . . . . . . . . . . .
Address-Space Number (ASN) . . . . . . . . . . . .
ASN-First-Table Entry . . . . . . . . . . . . . . . . .
ASN-Second-Table Entry (ASTE) . . . . . . . . . . .
PC-Number Translation . . . . . . . . . . . . . . . . . .
Program-Call Number . . . . . . . . . . . . . . . . .
Linkage-Table Entry (LTE) . . . . . . . . . . . . . . .
Entry-Table Entry (ETE) . . . . . . . . . . . . . . . .
Access-Register Translation . . . . . . . . . . . . . . . .
Access-List-Entry Token (ALET) . . . . . . . . . . . .
Dispatchable-Unit-Control Table (DUCT) . . . . . . .
Access-List Entry (ALE) . . . . . . . . . . . . . . . .
Linkage-Stack Entries . . . . . . . . . . . . . . . . . . .
Entry Descriptor . . . . . . . . . . . . . . . . . . . .
Header Entry (Entry Type 0001001) . . . . . . . . . .
Trailer Entry (Entry Type 0001010) . . . . . . . . . .
Branch State Entry (Entry Type 0001100) and
Program-Call State Entry (Entry Type 0001101)
. .
Trapping . . . . . . . . . . . . . . . . . . . . . . . . . .
Trap Control Block . . . . . . . . . . . . . . . . . . .
Trap Save Area . . . . . . . . . . . . . . . . . . . .
Trace-Entry Formats . . . . . . . . . . . . . . . . . . . .
Identification of Trace Entries . . . . . . . . . . . . .
Branch . . . . . . . . . . . . . . . . . . . . . . . . .
Branch in Subspace Group (if ASN Tracing on) . . . .
Mode Switch . . . . . . . . . . . . . . . . . . . . . .
Mode-Switching Branch . . . . . . . . . . . . . . . .
Program Call . . . . . . . . . . . . . . . . . . . . . .
Program Return . . . . . . . . . . . . . . . . . . . .
Copyright IBM Corp. 2001
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Program Transfer . . . . . . . . . . . . . . . . . .
Set Secondary ASN . . . . . . . . . . . . . . . .
Trace . . . . . . . . . . . . . . . . . . . . . . . .
Machine-Check Interruption Code . . . . . . . . . . .
External-Damage Code . . . . . . . . . . . . . . . .
Operation-Request Block (ORB) . . . . . . . . . . .
Channel-Command Word (CCW) . . . . . . . . . . .
Format-0 CCW . . . . . . . . . . . . . . . . . . .
Format-1 CCW . . . . . . . . . . . . . . . . . . .
Indirect-Data-Address Word (IDAW) . . . . . . . . .
Format-1 IDAW . . . . . . . . . . . . . . . . . . .
Format-2 IDAW . . . . . . . . . . . . . . . . . . .
Subchannel-Information Block (SCHIB) . . . . . . . .
Path-Management-Control Word (PMCW) . . . . .
Interruption-Response Block (IRB) . . . . . . . . . .
Subchannel-Status Word (SCSW) . . . . . . . . .
Extended-Status Word (ESW) . . . . . . . . . . .
Information Stored in ESW . . . . . . . . . . . . .
Extended-Control Word (ECW) . . . . . . . . . .
Measurement Block . . . . . . . . . . . . . . . . . .
Channel-Report Word (CRW) . . . . . . . . . . . . .
Error-Recovery Codes . . . . . . . . . . . . . . .
Reporting Source . . . . . . . . . . . . . . . . . .
I/O Command Codes . . . . . . . . . . . . . . . . .
Standard Command-Code Assignments (CCW Bits
0-7) . . . . . . . . . . . . . . . . . . . . . . . .
Standard Meanings of Bits of First Sense Byte . .
Code Assignments . . . . . . . . . . . . . . . . . .
Code Table . . . . . . . . . . . . . . . . . . . . .
Control Character Representations . . . . . . . .
Additional ISO-8 Control Character Representations
Formatting Character Representations . . . . . . .
Two-Character BSC Data Link Controls . . . . . .
Commonly Used Editing Pattern Characters . . . .
ANSI-Defined Printer Control Characters . . . . .
Hexadecimal and Decimal Conversion . . . . . . . .
Powers of 2 and 16 . . . . . . . . . . . . . . . .
vi
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40
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41
42
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42
43
43
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44
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45
46
47
48
48
48
48
49
49
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49
49
50
50
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57
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59
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NOTES
Machine Instruction Formats
First Halfword Second Halfword Third Halfword
E
Op Code
15
RR Op Code R$ R%
8 12 15
RRE
Op Code
///////// R$ R%
16
24 28 31
Op Code
R$ //// R, R%
16 2
24 28 31
RRF
Op Code
M, //// R$ R%
16 2
24 28 31
Op Code
R, M/ R$ R%
16 2
24 28 31
RX Op Code R$ X% B%
D%
8 12 16 2
31
RXE Op Code R$ X% B%
D%
///////// Op Code
8 12 16 2
32
4
47
RXF Op Code R, X% B%
D%
R$ //// Op Code
8 12 16 2
32
4
47
Op Code R$ R, B%
D%
8 12 16 2
31
RS
Op Code R$ M, B%
D%
8 12 16 2
31
Op Code R$ R, B%
D%
///////// Op Code
RSE
8 12 16 2
32
4
47
Machine Instruction Formats (Cont'd)
First Halfword Second Halfword Third Halfword
RSE
(Co-
nt.) Op Code R$ M, B%
D%
///////// Op Code
8 12 16 2
32
4
47
RSL Op Code L$ //// B%

D%
///////// Op Code
8 12 16 2
32
4
47
RSI Op Code R$ R,
I%
8 12 16
31
RI Op Code R$ OpCd
I%
8 12 16
31
Op Code R$ OpCd
I%
RIL
8 12 16
47
Op Code M$ OpCd
I%
8 12 16
47
SI Op Code I%
B$
D$
8
16 2
31
S
Op Code
B%
D%
16 2
31
Op Code
L
B$
D$
B%
D%
8
16 2
32 36
47
Op Code L$ L% B$
D$
B%
D%
8 12 16 2
32 36
47
SS
Op Code R$ R, B$
D$
B%
D%
8 12 16 2
32 36
47
Op Code R$ R, B%
D%
B/
D/
8 12 16 2
32 36
47
SSE
Op Code
B$
D$
B%
D%
16 2
32 36
47
Machine Instruction Formats (Cont'd)
$, %, ,, /:
B$, B%, B/:
D$, D%, D/:
I%:
L, L$, L%:
M$, M,, M/:
R$, R%, R,:
X%:
Denotes association with first, second, third, or fourth operand

Base register designation field
Displacement field
Immediate operand field
Length field
Mask field
Register designation field
Index register designation field
Machine Instructions by Mnemonic

Mnemonic
A
AD
ADB
ADBR
ADR
AE
AEB
AEBR
AER
AG
AGF
AGFR
AGHI
AGR
AH
AHI
AL
ALC
ALCG
ALCGR
ALCR
ALG
ALGF
ALGFR
ALGR
ALR
AP
AR
AU
AUR
AW
AWR
AXBR
AXR
BAKR
BAL
BALR
BAS
BASR
BASSM
BC
BCR
BCT
BCTG
BCTGR
BCTR
BRAS
BRASL
BRC
BRCL
BRCT
BRCTG
BRXH
BRXHG
BRXLE
BRXLG
BSA
BSG
BSM
BXH
BXHG
BXLE
Operands
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,I%
R$,R%
R$,D%(X%,B%)
R$,I%
Name
Add (32)
Add Normalized (LH)
Add (LB)
Add (LB)
Add Normalized (LH)
Add Normalized (SH)
Add (SB)
Add (SB)
Add Normalized (SH)
Add (64)
Add (64<32)
Add (64<32)
Add Halfword Immediate
Add (64)
Add Halfword
Add Halfword Immediate
(32)
R$,D%(X%,B%)
Add Logical (32)
R$,D%(X%,B%)
Add Logical with Carry (32)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,D%(X%,B%)
Add Logical (64)
R$,D%(X%,B%)
Add Logical (64<32)
R$,R%
Add Logical (64<32)
R$,R%
Add Logical (64)
R$,R%
Add Logical (32)
D$(L$,B$),D%(L%,B%) Add Decimal
R$,R%
Add (32)
R$,D%(X%,B%)
Add Unnormalized (SH)
R$,R%
Add Unnormalized (SH)
R$,D%(X%,B%)
Add Unnormalized (LH)
R$,R%
Add Unnormalized (LH)
R$,R%
Add (EB)
R$,R%
Add Normalized (EH)
R$,R%
Branch and Stack
R$,D%(X%,B%)
Branch and Link
R$,R%
Branch and Link
R$,D%(X%,B%)
Branch and Save
R$,R%
Branch and Save
R$,R%
Branch and Save and Set
Mode
M$,D%(X%,B%)
Branch on Condition
M$,R%
Branch on Condition
R$,D%(X%,B%)
Branch on Count (32)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,I%
Branch Relative and Save
R$,I%
Long
M$,I%
Branch Relative on Condition
M$,I%
Branch Relative on Condition Long
R$,I%
Branch Relative on Count
(32)
R$,I%
(64)
R$,R,,I%
Branch Relative on Index
High (32)
R$,R,,I%
High (64)
R$,R,,I%
Low or Equal (32)
R$,R,,I%
Low or Equal (64)
R$,R%
Branch and Set Authority
R$,R%
Branch in Subspace Group
R$,R%
Branch and Set Mode
R$,R,,D%(B%)
Branch on Index High (32)
R$,R,,D%(B%)
Branch on Index High (64)
R$,R,,D%(B%)
Branch on Index Low or
Equal (32)
Format
RX
RX
RXE
RRE
RR
RX
RXE
RRE
RR
RXE
RXE
RRE
RI
RRE
RX
RI
Op
Code
5A
6A
ED1A
B31A
2A
7A
ED0A
B30A
3A
E308
E318
B918
A7B
B908
4A
A7A
RX
RXE
RXE
RRE
RRE
RXE
RXE
RRE
RRE
RR
SS
RR
RX
RR
RX
RR
RRE
RR
RRE
RX
RR
RX
RR
RR
5E
E398
E388
B988
B998
E30A
E31A
B91A
B90A
1E
FA
1A
7E
3E
6E
2E
B34A
36
B240
45
05
4D
0D
0C
RX
RR
RX
RXE
RRE
RR
RI
RIL
47
07
46
E346
B946
06
A75
C05
RI
A74
RIL
C04
RI
A76
RI
A77
RSI
84
RIE
EC44
RSI
85
Notes
c
c
c
c
c
c
c
c
c
cN
cN
cN
cN
cN
c
c
c
c N3
cN
cN
c N3
cN
cN
cN
cN
c
c
c
c
c
c
c
c
c
q
N
N
N3
N3
RIE
EC45
RRE
RRE
RR
RS
RSE
RS
B25A
B258
0B
86
EB44
87
Machine Instructions by Mnemonic (Cont'd)
Mnemonic
BXLEG
C
CD
CDB
CDBR
CDFBR
CDFR
CDGBR
CDGR
CDR
CDS
CDSG
CEB
CE
CEBR
CEFBR
CEFR
CEGBR
CEGR
CER
CFC
CFDBR
CFDR
CFEBR
CFER
CFXBR
CFXR
CG
CGDBR
CGDR
CGEBR
CGER
CGF
CGFR
CGHI
CGR
CGXBR
CGXR
CH
CHI
CKSM
CL
CLC
CLCL
CLCLE
CLCLU
CLG
CLGF
CLGFR
CLGR
CLI
CLM
CLMH
CLR
CLST
CMPSC
CP
CPYA
CR
CS
CSCH
CSG
CSP
CUSE
CUTFU
CUUTF
CVB
CVBG
CVD
CVDG
CXBR
CXFBR
CXFR
CXGBR
CXGR
CXR
Operands
R$,R,,D%(B%)
Name
Branch on Index Low or
Equal (64)
R$,D%(X%,B%)
Compare (32)
R$,D%(X%,B%)
Compare (LH)
R$,D%(X%,B%)
Compare (LB)
R$,R%
Compare (LB)
R$,R%
Convert from Fixed (LB<32)
R$,R%
Convert from Fixed (LH<32)
R$,R%
R$,R%
R$,R%
Compare (LH)
R$,R,,D%(B%)
Compare Double and Swap
(32)
R$,R,,D%(B%)
Compare Double and Swap
(64)
R$,D%(X%,B%)
Compare (SB)
R$,D%(X%,B%)
Compare (SH)
R$,R%
Compare (SB)
R$,R%
Convert from Fixed (SB<32)
R$,R%
Convert from Fixed (SH<32)
R$,R%
Convert from Fixed (SB<64)
R$,R%
Convert from Fixed (SH<64)
R$,R%
Compare (SH)
D%(B%)
Compare and Form
Codeword
R$,M,,R%
Convert to Fixed (32<LB)
R$,M,,R%
Convert to Fixed (32<LH)
R$,M,,R%
Convert to Fixed (32<SB)
R$,M,,R%
Convert to Fixed (32<SH)
R$,M,,R%
Convert to Fixed (32<EB)
R$,M,,R%
Convert to Fixed (32<EH)
R$,D%(X%,B%)
Compare (64)
R$,M,,R%
Convert to Fixed (64<LB)
R$,M,,R%
Convert to Fixed (64<LH)
R$,M,,R%
Convert to Fixed (64<SB)
R$,M,,R%
Convert to Fixed (64<SH)
R$,D%(X%,B%)
Compare (64<32)
R$,R%
Compare (64<32)
R$,I%
Compare Halfword Immediate (64)
R$,R%
Compare (64)
R$,M,,R%
Convert to Fixed (64<EB)
R$,M,,R%
Convert to Fixed (64<EH)
R$,D%(X%,B%)
Compare Halfword
R$,I%
Compare Halfword Immediate (32)
R$,R%
Checksum
R$,D%(X%,B%)
Compare Logical (32)
D$(L,B$),D%(B%)
Compare Logical (character)
R$,R%
Compare Logical Long
R$,R,,D%(B%)
Extended
R$,R,,D%(B%)
Unicode
R$,D%(X%,B%)
R$,D%(X%,B%)
Compare Logical (64<32)
R$,R%
Compare Logical (64<32)
R$,R%
D$(B$)I%
Compare Logical (immediate)
R$,M,,D%(B%)
Compare Logical Characters
under Mask
R$,M,,D%(B%)
Compare Logical Characters
under Mask
R$,R%
R$,R%
Compare Logical String
R$,R%
Compression Call
D$(L$,B$),D%(L%,B%) Compare Decimal
R$,R%
Copy Access
R$,R%
Compare (32)
R$,R,,D%(B%)
Compare and Swap (32)
Clear Subchannel
R$,R,,D%(B%)
Compare and Swap (64)
R$,R%
Compare and Swap and
Purge
R$,R%
Compare until Substring
Equal
R$,R%
Convert UTF-8 to Unicode
R$,R%
Convert Unicode to UTF-8
R$,D%(X%,B%)
Convert to Binary (32)
R$,D%(X%,B%)
Convert to Binary (64)
R$,D%(X%,B%)
Convert to Decimal (32)
R$,D%(X%,B%)
Convert to Decimal (64)
R$,R%
Compare (EB)
R$,R%
Convert from Fixed (EB<32)
R$,R%
Convert from Fixed (EH<32)
R$,R%
Convert from Fixed (EB<64)
R$,R%
Convert from Fixed (EH<64)
R$,R%
Compare (EH)
Format
RSE
Op
Code
EB45
RX
RX
RXE
RRE
RRE
RRE
RRE
RRE
RR
RS
59
69
ED19
B319
B395
B3B5
B3A5
B3C5
29
BB
N
N
c
c
Notes
N
c
c
c
c
RSE
EB3E
cN
RXE
RX
RRE
RRE
RRE
RRE
RRE
RR
S
ED09
79
B309
B394
B3B4
B3A4
B3C4
39
B21A
c
c
c
N
N
c
ic
RRF
RRF
RRF
RRF
RRF
RRF
RXE
RRF
RRF
RRF
RRF
RXE
RRE
RI
B399
B3B9
B398
B3B8
B39A
B3BA
E320
B3A9
B3C9
B3A8
B3C8
E330
B930
A7F
c
c
c
c
c
c
cN
cN
cN
cN
cN
cN
cN
cN
RRE
RRF
RRF
RX
RI
B920
B3AA
B3CA
49
A7E
cN
cN
cN
c
c
RRE
RX
SS
RR
RS
B241
55
D5
0F
A9
c
c
c
ic
c
RSE
EB8F
c E2
RXE
RXE
RRE
RRE
SI
E321
E331
B931
B921
95
c
c
c
c
RS
BD
RSE
EB20
cN
RR
RRE
RRE
SS
RRE
RR
RS
S
RSE
RRE
15
B25D
B263
F9
B24D
19
BA
B230
EB30
B250
c
c
ic
c
c
c
pc
cN
pc
RRE
B257
ic
RRE
RRE
RX
RXE
RX
RXE
RRE
RRE
RRE
RRE
RRE
RRE
B2A7
B2A6
4F
E30E
4E
E32E
B349
B396
B3B6
B3A6
B3C6
B369
c
c
N
N
N
N
c
c
N
N
c
N
N
c
Mnemonic
D
DD
DDB
DDBR
DDR
DE
DEB
DEBR
DER
DIDBR
DIEBR
DL
DLG
DLGR
DLR
DP
DR
DSG
DSGF
DSGFR
DSGR
DXBR
DXR
EAR
ED
EDMK
EFPC
EPAR
EPSW
EREG
Operands
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R,,R%,M/
R$,R,,R%,M/
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
D$(L$,B$),D%(L%,B%)
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$,R%
R$,R%
D$(L,B$),D%(B%)
D$(L,B$),D%(B%)
R$
R$
R$,R%
R$,R%
EREGG
R$,R%
ESAR
ESEA
R$
R$,R%
ESTA
EX
FIDBR
FIDR
FIEBR
FIER
FIXBR
FIXR
HDR
HER
HSCH
IAC
R$,R%
R$,D%(X%,B%)
R$,M,,R%
R$,R%
R$,M,,R%
R$,R%
R$,M,,R%
R$,R%
R$,R%
R$,R%
IC
ICM
R$,D%(X%,B%)
R$,M,,D%(B%)
ICMH
R$,M,,D%(B%)
IIHH
IIHL
IILH
IILL
IPK
IPM
IPTE
ISKE
R$,I%
R$,I%
R$,I%
R$,I%
R$
R$,R%
R$,R%
IVSK
KDB
KDBR
KEB
KEBR
KXBR
L
LA
LAE
LAM
LARL
LASP
R$,R%
R$,D%(X%,B%)
R$,R%
R$,D%(X%,B%)
R$,R%
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R,,D%(B%)
R$,I%
D$,(B$),D%(B%)
LCDBR
LCDR
LCEBR
LCER
LCGFR
LCGR
LCR
LCTL
LCTLG
LCXBR
LCXR
LD
LDE
R$,R%
R$,R%
R$,R%
R$,R%
R$,R%
R$,R%
R$,R%
R$,R,,D%(B%)
R$,R,,D%(B%)
R$,R%
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$
Name
Divide (32<64)
Divide (LH)
Divide (LB)
Divide (LB)
Divide (LH)
Divide (SH)
Divide (SB)
Divide (SB)
Divide (SH)
Divide to Integer (LB)
Divide to Integer (SB)
Divide Logical (32<64)
Divide Decimal
Divide
Divide Single (64)
Divide Single (64<32)
Divide Single (64<32)
Divide Single (64)
Divide (EB)
Divide (EH)
Extract Access
Edit
Edit and Mark
Extract FPC
Extract Primary ASN
Extract PSW
Extract Stacked Registers
(32)
Extract Stacked Registers
(64)
Extract Secondary ASN
Extract and Set Extended
Authority
Extract Stacked State
Execute
Load FP Integer (LB)
Load FP Integer (LH)
Load FP Integer (SB)
Load FP Integer (SH)
Load FP Integer (EB)
Load FP Integer (EH)
Halve (LH)
Halve (SH)
Halt Subchannel
Insert Address Space
Control
Insert Character
Insert Characters under
Mask (low)
Insert Characters under
Mask (high)
Insert Immediate (high high)
Insert Immediate (high low)
Insert Immediate (low high)
Insert Immediate (low low)
Insert PSW Key
Insert Program Mask
Invalidate Page Table Entry
Insert Storage Key
Extended
Insert Virtual Storage Key
Compare and Signal (LB)
Compare and Signal (LB)
Compare and Signal (SB)
Compare and Signal (SB)
Compare and Signal (EB)
Load (32)
Load Address
Load Address Extended
Load Access Multiple
Load Address Relative Long
Load Address Space
Parameters
Load Complement (LB)
Load Complement (LH)
Load Complement (SB)
Load Complement (S)
Load Complement (64<32)
Load Complement (64)
Load Complement (32)
Load Control (32)
Load Control (64)
Load Complement (EB)
Load Complement (EH)
Load (L)
Load Lengthened (LH<SH)
Format
RX
RX
RXE
RRE
RR
RX
RXE
RRE
RR
RRF
RRF
RXE
RXE
RRE
RRE
SS
RR
RXE
RXE
RRE
RRE
RRE
RRE
RRE
SS
SS
RRE
RRE
RRE
RRE
Op
Code Notes
5D
6D
ED1D
B31D
2D
7D
ED0D
B30D
3D
B35B
c
B353
c
E397
N3
E387
N
B987
N
B997
N3
FD
1D
E30D
N
E31D
N
B91D
N
B90D
N
B34D
B22D
B24F
DE
c
DF
c
B38C
B226
q
B98D
N3
B249
RRE
B90E
RRE
RRE
B227
B99D
q
pN
RRE
RX
RRF
RRE
RRF
RRE
RRF
RRE
RR
RR
S
RRE
B24A
44
B35F
B37F
B357
B377
B347
B367
24
34
B231
B224
RX
RS
43
BF
RSE
EB80
cN
RI
RI
RI
RI
S
RRE
RRE
RRE
A50
A51
A52
A53
B20B
B222
B221
B229
N
N
N
N
q
RRE
RXE
RRE
RXE
RRE
RRE
RX
RX
RX
RS
RIL
SSE
B223
ED18
B318
ED08
B308
B348
58
41
51
9A
C00
E500
q
c
c
c
c
c
RRE
RR
RRE
RR
RRE
RRE
RR
RS
RSE
RRE
RRE
RX
RXE
B313
23
B303
33
B913
B903
13
B7
EB2F
B343
B363
68
ED24
pc
qc
c
p
p
N3
pc
c
c
c
c
cN
cN
c
p
pN
c
c
Mnemonic
LDEB
LDEBR
LDER
LDR
LDXBR
LDXR
LE
LEDBR
LEDR
LER
LEXBR
LEXR
LFPC
LG
LGF
LGFR
LGH
LGHI
LGR
LH
LHI
LLGC
LLGF
LLGFR
LLGH
LLGT
LLGTR
LLIHH
LLIHL
LLILH
LLILL
LM
LMD
LMG
LMH
LNDBR
LNDR
LNEBR
LNER
LNGFR
LNGR
LNR
LNXBR
LNXR
LPDBR
LPDR
LPEBR
LPER
LPGFR
LPGR
LPQ
LPR
LPSW
LPSWE
LPXBR
LPXR
LR
LRA
LRAG
LRDR
LRER
LRV
LRVG
LRVGR
LRVH
LRVR
LTDBR
LTDR
LTEBR
LTER
LTGFR
LTGR
LTR
LTXBR
LTXR
LURA
LURAG
LXD
LXDB
LXDBR
LXDR
LXE
Operands
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$,R%
R$,R%
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$,R%
R$,R%
D%(B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,D%(X%,B%)
R$,I%
R$,R%
R$,D%(X%,B%)
R$,I%
Name
Load Lengthened (LB<SB)
Load Lengthened (LB<SB)
Load Lengthened (LH<SH)
Load (L)
Load Rounded (LB<EB)
Load Rounded (LH<EH)
Load (S)
Load Rounded (SB<LB)
Load Rounded (SH<LH)
Load (S)
Load Rounded (SB<EB)
Load Rounded (SH<EH)
Load FPC
Load (64)
Load (64<32)
Load (64<32)
Load Halfword
Load Halfword Immediate
Load (64)
Load Halfword (32)
Load Halfword Immediate
(32)
R$,D%(X%,B%)
Load Logical Character
R$,D%(X%,B%)
Load Logical (64<32)
R$,R%
Load Logical (64<32)
R$,D%(X%,B%)
Load Logical Halfword
R$,D%(X%,B%)
Load Logical Thirty One Bits
R$,R%
Load Logical Thirty One Bits
R$,I%
Load Logical Immediate
(high high)
R$,I%
Load Logical Immediate
(high low)
R$,I%
Load Logical Immediate (low
high)
R$,I%
Load Logical Immediate (low
low)
R$,R,D%(B%)
Load Multiple (32)
R$,R,,D%(B%),D/(B/) Load Multiple Disjoint
R$,R,D%(B%)
Load Multiple (64)
R$,R,D%(B%)
Load Multiple High
R$,R%
Load Negative (LB)
R$,R%
Load Negative (LH)
R$,R%
Load Negative (SB)
R$,R%
Load Negative (SH)
R$,R%
Load Negative (64<32)
R$,R%
Load Negative (64)
R$,R%
Load Negative (32)
R$,R%
Load Negative (EB)
R$,R%
Load Negative (EH)
R$,R%
Load Positive (LB)
R$,R%
Load Positive (LH)
R$,R%
Load Positive (SB)
R$,R%
Load Positive (SH)
R$,R%
Load Positive (64<32)
R$,R%
Load Positive (64)
R$,D%(X%,B%)
Load Pair from Quadword
R$,R%
Load Positive (32)
D%(B%)
Load PSW
D%(B%)
Load PSW Extended
R$,R%
Load Positive (EB)
R$,R%
Load Positive (EH)
R$,R%
Load (32)
R$,D%(X%,B%)
Load Real Address (32)
R$,D%(X%,B%)
Load Real Address (64)
R$,R%
Load Rounded (LH<EH)
R$,R%
Load Rounded (SH<LH)
R$,D%(X%,B%)
Load Reversed (32)
R$,D%(X%,B%)
Load Reversed (64)
R$,R%
Load Reversed (64)
R$,D%(X%,B%)
Load Reversed (16)
R$,R%
Load Reversed (32)
R$,R%
Load and Test (LB)
R$,R%
Load and Test (LH)
R$,R%
Load and Test (SB)
R$,R%
Load and Test (SH)
R$,R%
Load and Test (64<32)
R$,R%
Load and Test (64)
R$,R%
Load and Test (32)
R$,R%
Load and Test (EB)
R$,R%
Load and Test (EH)
R$,R%
Load Using Real Address
(32)
R$,R%
Load Using Real Address
(64)
R$,D%(X%,B%)
Load Lengthened (EH<LH)
R$,D%(X%,B%)
Load Lengthened (EB<LB)
R$,R%
Load Lengthened (EB<LB)
R$,R%
Load Lengthened (EH<LH)
R$,D%(X%,B%)
Load Lengthened (EH<SH)
Format
RXE
RRE
RRE
RR
RRE
RR
RX
RRE
RR
RR
RRE
RRE
S
RXE
RXE
RRE
RXE
RI
RRE
RX
RI
Op
Code
ED04
B304
B324
28
B345
25
78
B344
35
38
B346
B366
B29D
E304
E314
B914
E315
A79
B904
48
A78
RXE
RXE
RRE
RXE
RXE
RRE
RI
E390
E316
B916
E391
E317
B917
A5C
N
N
N
N
N
N
N
RI
A5D
RI
A5E
RI
A5F
RS
SS
RSE
RSE
RRE
RR
RRE
RR
RRE
RRE
RR
RRE
RRE
RRE
RR
RRE
RR
RRE
RRE
RXE
RR
S
S
RRE
RRE
RR
RX
RXE
RR
RR
RXE
RXE
RRE
RXE
RRE
RRE
RR
RRE
RR
RRE
RRE
RR
RRE
RRE
RRE
98
EF
EB04
EB96
B311
21
B301
31
B911
B901
11
B341
B361
B310
20
B300
30
B910
B900
E38F
10
82
B2B2
B340
B360
18
B1
E303
25
35
E31E
E30F
B90F
E31F
B91F
B312
22
B302
32
B912
B902
12
B342
B362
B24B
RRE
B905
RXE
RXE
RRE
RRE
RXE
ED25
ED05
B305
B325
ED26
Notes
N
N
N
N
N
N
N
N
N
c
c
c
c
cN
cN
c
c
c
c
c
c
c
cN
cN
N
c
pn
pn N
c
c
pc
pc N
N3
N
N
N3
N3
c
c
c
c
cN
cN
c
c
c
p
pN
Mnemonic
LXEB
LXEBR
LXER
LXR
LZDR
LZER
LZXR
M
MADB
MADBR
MAEB
MAEBR
MC
MD
MDB
MDBR
MDE
MDEB
MDEBR
MDER
MDR
ME
MEE
MEEB
MEEBR
MEER
MER
MGHI
Operands
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$
R$
R$
R$,D%(X%,B%)
R$,R,,D%(X%,B%)
R$,R,,R%
R$,R,,D%(X%,B%)
R$,R,,R%
D$(B$),I%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$,I%
MH
MHI
R$,D%(X%,B%)
R$,I%
ML
MLG
MLGR
MLR
MP
MR
MS
MSCH
MSDB
MSDBR
MSEB
MSEBR
MSG
MSGF
MSGFR
MSGR
MSR
MSTA
MVC
MVCDK
MVCIN
MVCK
MVCL
MVCLE
MVCLU
MVCP
MVCS
MVCSK
MVI
MVN
MVO
MVPG
MVST
MVZ
MXBR
MXD
MXDB
MXDBR
MXDR
MXR
N
NC
NG
NGR
NI
NIHH
NIHL
NILH
NILL
NR
O
OC
OG
OGR
OI
OIHH
OIHL
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
D$(L$,B$),D%(L%,B%)
R$,R%
R$,D%(X%,B%)
D%(B%)
R$,R,,D%(X%,B%)
R$,R,,R%
R$,R,,D%(X%,B%)
R$,R,,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$
D$(L,B$),D%(B%)
D$(B$),D%(B%)
D$(L,B$),D%(B%)
D$(R$,B$),D%(B%),R,
R$,R%
R$,R,,D%(B%)
R$,R,,D%(B%)
D$(R$B$),D%(B%),R,
D$(R$B$),D%(B%),R,
D$(B$),D%(B%)
D$(B$),I%
D$(L,B$),D%(B%)
D$(L$,B$),D%(L%,B%)
R$,R%
R$,R%
D$(L,B$),D%(B%)
R$,R%
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
R$,R%
R$,R%
R$,D%(X%,B%)
D$(L,B$),D%(B%)
R$,D%(X%,B%)
R$,R%
D$(B$),I%
R$,I%
R$,I%
R$,I%
R$,I%
R$,R%
R$,D%(X%,B%)
D$(L,B$),D%(B%)
R$,D%(X%,B%)
R$,R%
D$(B$),I%
R$,I%
R$,I%
Name
Load Lengthened (EB<SB)
Load Lengthened (EB<SB)
Load Lengthened (EH<SH)
Load (E)
Load Zero (L)
Load Zero (S)
Load Zero (E)
Multiply (64<32)
Multiply and Add (LB)
Multiply and Add (LB)
Multiply and Add (SB)
Multiply and Add (SB)
Monitor Call
Multiply (LH)
Multiply (LB)
Multiply (LB)
Multiply (LH<SH)
Multiply (LB<SB)
Multiply (LB<SB)
Multiply (LH<SH)
Multiply (LH)
Multiply (LH<SH)
Multiply (SH)
Multiply (SB)
Multiply (SB)
Multiply (SH)
Multiply (LH<SH)
Multiply Halfword Immediate
(64)
Multiply Halfword (32)
Multiply Halfword Immediate
(32)
Multiply Logical (64<32)
Multiply Decimal
Multiply (64<32)
Multiply Single (32)
Modify Subchannel
Multiply and Subtract (LB)
Multiply and Subtract (LB)
Multiply and Subtract (SB)
Multiply and Subtract (SB)
Multiply Single (64<32)
Multiply Single (64<32)
Modify Stacked State
Move (character)
Move with Destination key
Move Inverse
Move with Key
Move Long
Move Long Extended
Move Long Unicode
Move to Primary
Move to Secondary
Move with Source Key
Move (immediate)
Move Numerics
Move with Offset
Move Page
Move String
Move Zones
Multiply (EB)
Multiply (EH<LH)
Multiply (EB<LB)
Multiply (EB<LB)
Multiply (EH<LH)
Multiply (EH)
And (32)
And (character)
And (64)
And (64)
And (immediate)
And Immediate (high high)
And Immediate (high low)
And Immediate (low high)
And Immediate (low low)
And (32)
Or (32)
Or (character)
Or (64)
Or (64)
Or (immediate)
Or Immediate (high high)
Or Immediate (high low)
Format
RXE
RRE
RRE
RRE
RRE
RRE
RRE
RX
RXF
RRF
RXF
RRF
SI
RX
RXE
RRE
RX
RXE
RRE
RR
RR
RX
RXE
RXE
RRE
RRE
RR
RI
Op
Code Notes
ED06
B306
B326
B365
B375
B374
B376
5C
ED1E
B31E
ED0E
B30E
AF
6C
ED1C
B31C
7C
ED0C
B30C
3C
2C
7C
ED37
ED17
B317
B337
3C
A7D
N
RX
RI
4C
A7C
RXE
RXE
RRE
RRE
SS
RR
RX
S
RXF
RRF
RXF
RRF
RXE
RXE
RRE
RRE
RRE
RRE
SS
SSE
SS
SS
RR
RS
RSE
SS
SS
SSE
SI
SS
SS
RRE
RRE
SS
RRE
RX
RXE
RRE
RR
RR
RX
SS
RX
RRE
SI
RI
RI
RI
RI
RR
RX
SS
RXE
RRE
SI
RI
RI
E396
E386
B986
B996
FC
1C
71
B232
ED1F
B31F
ED0F
B30F
E30C
E31C
B91C
B90C
B252
B247
D2
E50F
E8
D9
0E
A8
EB8E
DA
DB
E50E
92
D1
F1
B254
B255
D3
B34C
67
ED07
B307
27
26
54
D4
54
B980
94
A54
A55
A56
A57
14
56
D6
E381
B981
96
A58
A59
N3
N
N
N3
pc
N
N
N
N
q
qc
ic
c
c E2
qc
qc
q
qc
c
c
c
cN
cN
c
cN
cN
cN
cN
c
c
c
cN
cN
c
cN
cN
Mnemonic
OILH
OILL
OR
PACK
PALB
PC
PGIN
PGOUT
PKA
PKU
PLO
PR
PT
PTLB
RCHP
RLL
RLLG
RP
RRBE
RSCH
S
SAC
SACF
SAL
SAM24
SAM31
SAM64
SAR
SCHM
SCK
SCKC
SCKPF
SD
SDB
SDBR
SDR
SE
SEB
SEBR
SER
SFPC
SG
SGF
SGFR
SGR
SH
SIE
SIGP
SL
SLA
SLAG
SLB
SLBG
SLBGR
SLBR
SLDA
SLG
SLGF
SLGFR
SLGR
SLDL
SLL
SLLG
SLR
SP
SPKA
SPM
SPT
SPX
SQD
SQDB
SQDBR
SQDR
SQE
SQEB
SQEBR
SQER
SQXR
SQXBR
SR
Operands
R$,I%
R$,I%
R$R%
D$(L$,B$),D%(L%,B%)
Name
Or Immediate (low high)
Or Immediate (low low)
Or (32)
Pack
Purge ALB
D%(B%)
Program Call
R$R%
Page In
R$R%
Page In
D$(B$),D%(L%,B%)
Pack ASCII
D$(B$),D%(L%,B%)
Pack Unicode
R$,D%(B%),R,,D/(B/) Perform Locked Operation
Program Return
R$,R%
Program Transfer
Purge TLB
Reset Channel Path
R$,R,,D%(B%)
Rotate Left Single Logical
(32)
R$,R,,D%(B%)
Rotate Left Single Logical
(64)
D%(B%)
Resume Program
R$,R%
Reset Reference Bit
Extended
Resume Subchannel
R$,D%(X%,B%)
Subtract (32)
D%(B%)
Set Address Space Control
D%(B%)
Set Address Space Control
Fast
Set Address Limit
Set Addressing Mode (24)
R$,R%
Set Access
Set Channel Monitor
D%(B%)
Set Clock
D%(B%)
Set Clock Comparator
Set Clock Programmable
Field
R$,D%(X%,B%)
Subtract Normalized (LH)
R$,D%(X%,B%)
Subtract (LB)
R$,R%
Subtract (LB)
R$,R%
Subtract Normalized (LH)
R$,D%(X%,B%)
Subtract Normalized (SH)
R$,D%(X%,B%)
Subtract (SB)
R$,R%
Subtract (SB)
R$,R%
Subtract Normalized (SH)
R$
Set FPC
R$,D%(X%,B%)
Subtract (64)
R$,D%(X%,B%)
Subtract (64<32)
R$,R%
Subtract (64<32)
R$,R%
Subtract (64)
R$,D%(X%,B%)
Subtract Halfword
D%(B%)
Start Interpretive Execution
R$,R,,D%(B%)
Signal Processor
R$,D%(X%,B%)
Subtract Logical (32)
R$,D%(B%)
Shift Left Single (32)
R$,D%(B%)
Shift Left Single (64)
R$,D%(X%,B%)
Subtract Logical with Borrow
(32)
R$,D%(X%,B%)
(64)
R$,R%
(64)
R$,R%
(32)
R$,D%(B%)
Shift Left Double
R$,D%(X%,B%)
R$,D%(X%,B%)
Subtract Logical (64<32)
R$,R%
Subtract Logical (64<32)
R$,R%
R$,D%(B%)
Shift Left Double Logical
R$,D%(B%)
Shift Left Single Logical (32)
R$,D%(B%)
Shift Left Single Logical (64)
R$,R%
D$(L$,B$),D%(L%,B%) Subtract Decimal
D%(B%)
Set PSW Key from Address
R$
Set Program Mask
D%(B%)
Set CPU Timer
D%(B%)
Set Prefix
R$,D%(X%,B%)
Square Root (LH)
R$,D%(X%,B%)
Square Root (LB)
R$,R%
Square Root (LB)
R$,R%
Square Root (LH)
R$,D%(X%,B%)
Square Root (SH)
R$,D%(X%,B%)
Square Root (SB)
R$,R%
Square Root (SB)
R$,R%
Square Root (SH)
R$,R%
Square Root (EH)
R$,R%
Square Root (EB)
R$,R%
Subtract (32)
Format
RI
RI
RR
SS
RRE
S
RRE
RRE
SS
SS
SS
E
RRE
S
S
RSE
Op
Code
A5A
A5B
16
F2
B248
B218
B22E
B22F
E9
E1
EE
0101
B228
B20D
B23B
EB1D
Notes
cN
cN
c
p
q
pc ES
pc ES
E2
E2
c
qn
q
p
pc
N3
RSE
EB1C
S
RRE
B277
B22A
qn
pc
S
RX
S
S
B238
5B
B219
B279
pc
c
q
q
S
E
E
E
RRE
S
S
S
E
B237
010C
010D
010E
B24E
B23C
B204
B206
0107
p
N3
N3
N
RX
RXE
RRE
RR
RX
RXE
RRE
RR
RRE
RXE
RXE
RRE
RRE
RX
S
RS
RX
RS
RSE
RXE
6B
ED1B
B31B
2B
7B
ED0B
B30B
3B
B384
E309
E319
B919
B909
4B
B214
AE
5F
8B
EB0B
E399
c
c
c
c
c
c
c
c
N
N
N
N
c
ip
pc
c
c
cN
c N3
RXE
E389
cN
RRE
B989
cN
RRE
B999
c N3
RS
RXE
RXE
RRE
RRE
RS
RS
RSE
RR
SS
S
RR
S
S
RXE
RXE
RRE
RRE
RXE
RXE
RRE
RRE
RRE
RRE
RR
8F
E30B
E31B
B91B
B90B
8D
89
EB0D
1F
FB
B20A
04
B208
B210
ED35
ED15
B315
B244
ED34
ED14
B314
B245
B336
B316
1B
p
pc
p
p
c
c
c
c
c
c
c
c
c
N
N
N
N
N
c
c
q
n
p
p
Mnemonic
SRA
SRAG
SRDA
SRDL
SRL
Operands
R$,D%(B%)
R$,D%(B%)
R$,D%(B%)
R$,D%(B%)
R$,D%(B%)
SRLG
R$,D%(B%)
SRNM
SRP
SRST
SSAR
SSCH
SSKE
SSM
ST
STAM
STAP
STC
STCK
STCKC
STCKE
STCM
D%(B%)
D$(L$,B$),D%(B%),I,
R$,R%
R$
D%(B%)
R$,R%
D%(B%)
R$,D%(X%,B%)
R$,R,,D%(B%)
D%(B%)
R$,D%(X%,B%)
D%(B%)
D%(B%)
D%(B%)
R$,M,,D%(B%)
STCMH
R$,M,,D%(B%)
STCPS
STCRW
STCTG
STCTL
STD
STE
STFL
STFPC
STG
STH
STIDP
STM
STMG
STMH
STNSM
D%(B%)
D%(B%)
R$,R,,D%(B%)
R$,R,,D%(B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
D%(B%)
D%(B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
D%(B%)
R$,R,,D%(B%)
R$,R,,D%(B%)
R$,R,,D%(B%)
D$(B$),I%
STOSM
STPQ
STPT
STPX
STRAG
STRV
STRVG
STRVH
STSI
STSCH
STURA
D$(B$),I%
R$,D%(X%,B%)
D%(B%)
D%(B%)
D$(B$),D%(B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
D%(B%)
D%(B%)
R$,R%
STURG
R$,R%
SU
SUR
SVC
SW
SWR
SXBR
SXR
TAM
TAR
TB
TBDR
R$,D%(X%,B%)
R$,R%
I
R$,D%(X%,B%)
R$,R%
R$,D%
R$,D%
R$,R%
R$,R%
R$,M,,R%
TBEDR
R$,M,,R%
TCDB
TCEB
TCXB
THDER
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,D%(X%,B%)
R$,R%
THDR
R$,R%
TM
TMH
TMHH
TMHL
TML
TMLH
TMLL
TP
TPI
TPROT
TR
TRACE
D$(B$),I%
R$,I%
R$,I%
R$,I%
R$,I%
R$,I%
R$,I%
D$(L$,B$)
D%(B%)
D$(B$),D%(B%)
D$(L,B$),D%(B%)
R$,R,,D%(B%)
10
Name
Shift Right Single (32)
Shift Right Single (64)
Shift Right Double
Shift Right Double Logical
Shift Right Single Logical
(32)
Shift Right Single Logical
(64)
Set Rounding Mode
Shift and Round Decimal
Search String
Set Secondary ASN
Start Subchannel
Set Storage Key Extended
Set System Mask
Store (32)
Store Access Multiple
Store CPU Address
Store Character
Store Clock
Store Clock Comparator
Store Clock Extended
Store Characters under
Mask (low)
Store Characters under
Mask (high)
Store Channel Path Status
Store Channel Report Word
Store Control (64)
Store Control (32)
Store (L)
Store (S)
Store Facility List
Store FPC
Store (64)
Store Halfword
Store CPU ID
Store Multiple (32)
Store Multiple (64)
Store Multiple High
Store Then And System
Mask
Store Then Or System Mask
Store Pair to Quadword
Store CPU Timer
Store Prefix
Store Real Address
Store Reversed (32)
Store Reversed (64)
Store Reversed (16)
Store System Information
Store Subchannel
Store Using Real Address
(32)
Store Using Real Address
(64)
Subtract Unnormalized (SH)
Subtract Unnormalized (SH)
Supervisor Call
Subtract Unnormalized (LH)
Subtract Unnormalized (LH)
Subtract (EB)
Subtract Normalized (EH)
Test Addressing Mode
Test Access
Test Block
Convert HFP to BFP
(LB<LH)
Convert HFP to BFP
(SB<LH)
Test Data Class (LB)
Test Data Class (SB)
Test Data Class (EB)
Convert BFP to HFP
(LH<SB)
Convert BFP to HFP
(LH<LB)
Test under Mask
Test under Mask High
Test under Mask (high high)
Test under Mask (high low)
Test under Mask Low
Test under Mask (low high)
Test under Mask (low low)
Test Decimal
Test Pending Interruption
Test Protection
Translate
Trace (32)
Format
RS
RSE
RS
RS
RS
Op
Code
8A
EB0A
8E
8C
88
Notes
c
cN
c
RSE
EB0C
S
SS
RRE
RRE
S
RRE
S
RX
RS
S
RX
S
S
S
RS
B299
F0
B25E
B225
B233
B22B
80
50
9B
B212
42
B205
B207
B278
BE
c
c
pc
p
p
p
c
p
c
RSE
EB2C
S
S
RSE
RS
RX
RX
S
S
RXE
RX
S
RS
RSE
RSE
SI
B23A
B239
EB25
B6
60
70
B2B1
B29C
E324
40
B202
90
EB24
EB26
AC
p
pc
pN
p
SI
RXE
S
S
SSE
RXE
RXE
RXE
S
S
RRE
AD
E38E
B209
B211
E502
E33E
E32F
E33F
B27D
B234
B246
p
N
p
p
pN
N3
N
N3
pc
pc
p
RRE
B925
pN
RX
RR
RR
RX
RR
RRE
RR
E
RRE
RRE
RRF
7F
3F
0A
6F
2F
B34B
37
010B
B24C
B22C
B351
c
c
p N3
N
p
N
N
p
c
c
c
c
c N3
c
ipc
c
RRF
B350
RXE
RXE
RXE
RRE
ED11
ED10
ED12
B358
c
c
c
c
RRE
B359
SI
RI
RI
RI
RI
RI
RI
RSL
S
SSE
SS
RS
91
A70
A72
A73
A71
A70
A71
EBC0
B236
E501
DC
99
c
c
cN
cN
c
cN
cN
c E2
pc
pc
p
Mnemonic
TRACG
TRAP2
TRAP4
TRE
TROO
TROT
TRT
TRTO
TRTT
TS
TSCH
UNPK
UNPKA
UNPKU
UPT
X
XC
XG
XGR
XI
XR
XSCH
ZAP
---
For- Op
Name
mat
Code
Trace (64)
RSE EB0F
Trap
E
01FF
D%(B%)
Trap
S
B2FF
R$,R%
Translate Extended
RRE B2A5
R$,R%
Translate One to One
RRE B993
R$,R%
Translate One to Two
RRE B992
D$(L,B$),D%(B%)
Translate and Test
SS
DD
R$,R%
Translate Two to One
RRE B991
R$,R%
Translate Two to Two
RRE B990
D%(B%)
Test and Set
S
93
D%(B%)
Test Subchannel
S
B235
D$(L$,B$),D%(L%,B%) Unpack
SS
F3
D$(L$,B$),D%(B%)
Unpack ASCII
SS
EA
D$(L$,B$),D%(B%)
Unpack Unicode
SS
E2
Update Tree
E
0102
R$,D%(X%,B%)
Exclusive Or (32)
RX
57
D$(L,B$),D%(B%)
Exclusive Or (character)
SS
D7
R$,D%(X%,B%)
Exclusive Or (64)
RXE E382
R$,R%
Exclusive Or (64)
RRE B982
D$(B$),I%
Exclusive Or (immediate)
SI
97
R$,R%
Exclusive Or (32)
RR
17
Cancel Subchannel
S
B276
D$(L$,B$),D%(L%,B%) Zero and Add
SS
F8
ModelDiagnose
-83
dependent
Floating-Point Operand Lengths
Notes:
and Types:
E
Extended (binary or hex)
c
Condition code set
EB
Extended binary
i
Interruptible instruction
n
New condition code loaded
EH
Extended hex
L
Long (binary or hex)
p
Privileged instruction
LB
Long binary
q
Semiprivileged instruction
E2
Extended-translation facility 2
LH
Long hex
S
Short (binary or hex)
ES
Expanded-storage facility
SB
Short binary
N
Instruction new in z/Architecture
pared to ESA/390
SH
Short hex
N3
Instruction new in z/Architecture
pared to ESA/390 and added to
ESA/390
Operands
R$,R,,D%(B%)
Notes
pN
c
c E2
c E2
c
c E2
c E2
c
pc
c E2
c E2
ic
c
c
cN
cN
c
c
pc
c
pu
comcom-
Machine Instructions by Operation Code

Op
Code
0101
0102
0107
010B
010C
010D
010E
01FF
04
05
06
07
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
25
26
27
28
29
Mnemonic
PR
UPT
SCKPF
TAM
SAM24
SAM31
SAM64
TRAP2
SPM
BALR
BCTR
BCR
SVC
BSM
BASSM
BASR
MVCL
CLCL
LPR
LNR
LTR
LCR
NR
CLR
OR
XR
LR
CR
AR
SR
MR
DR
ALR
SLR
LPDR
LNDR
LTDR
LCDR
HDR
LDXR
LRDR
MXR
MXDR
LDR
CDR
Op
Code
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
35
36
37
38
39
3A
3B
3C
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
54
55
56
Mnemonic
ADR
SDR
MDR
DDR
AWR
SWR
LPER
LNER
LTER
LCER
HER
LEDR
LRER
AXR
SXR
LER
CER
AER
SER
MDER
MER
DER
AUR
SUR
STH
LA
STC
IC
EX
BAL
BCT
BC
LH
CH
AH
SH
MH
BAS
CVD
CVB
ST
LAE
N
CL
O
Op
Code
57
58
59
5A
5B
5C
5D
5E
5F
60
67
68
69
6A
6B
6C
6D
6E
6F
70
71
78
79
7A
7B
7C
7C
7D
7E
7F
80
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
Mnemonic
X
L
C
A
S
M
D
AL
SL
STD
MXD
LD
CD
AD
SD
MD
DD
AW
SW
STE
MS
LE
CE
AE
SE
MDE
ME
DE
AU
SU
SSM
LPSW
Diagnose
BRXH
BRXLE
BXH
BXLE
SRL
SLL
SRA
SLA
SRDL
SLDL
SRDA
SLDA
11
Machine Instructions by Operation Code (Cont'd)
Op
Code
90
91
92
93
94
95
96
97
98
99
9A
9B
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A5A
A5B
A5C
A5D
A5E
A5F
A70
A70
A71
A71
A72
A73
A74
A75
A76
A77
A78
A79
A7A
A7B
A7C
A7D
A7E
A7F
A8
A9
AC
AD
AE
AF
B1
B202
B204
B205
B206
B207
B208
B209
B20A
B20B
B20D
B210
B211
B212
B214
B218
B219
B21A
B221
B222
B223
B224
B225
B226
B227
B228
B229
B22A
B22B
B22C
B22D
B22E
B22F
B230
B231
B232
B233
B234
B235
B236
B237
B238
B239
B23A
B23B
B23C
B240
B241
B244
B245
B246
B247
B248
B249
B24A
B24B
B24C
12
Mnemonic
STM
TM
MVI
TS
NI
CLI
OI
XI
LM
TRACE
LAM
STAM
IIHH
IIHL
IILH
IILL
NIHH
NIHL
NILH
NILL
OIHH
OIHL
OILH
OILL
LLIHH
LLIHL
LLILH
LLILL
TMLH
TMH
TMLL
TML
TMHH
TMHL
BRC
BRAS
BRCT
BRCTG
LHI
LGHI
AHI
AGHI
MHI
MGHI
CHI
CGHI
MVCLE
CLCLE
STNSM
STOSM
SIGP
MC
LRA
STIDP
SCK
STCK
SCKC
STCKC
SPT
STPT
SPKA
IPK
PTLB
SPX
STPX
STAP
SIE
PC
SAC
CFC
IPTE
IPM
IVSK
IAC
SSAR
EPAR
ESAR
PT
ISKE
RRBE
SSKE
TB
DXR
PGIN
PGOUT
CSCH
HSCH
MSCH
SSCH
STSCH
TSCH
TPI
SAL
RSCH
STCRW
STCPS
RCHP
SCHM
BAKR
CKSM
SQDR
SQER
STURA
MSTA
PALB
EREG
ESTA
LURA
TAR
Op
Code
B24D
B24E
B24F
B250
B252
B254
B255
B257
B258
B25A
B25D
B25E
B263
B276
B277
B278
B279
B27D
B299
B29C
B29D
B2A5
B2A6
B2A7
B2B1
B2B2
B2FF
B300
B301
B302
B303
B304
B305
B306
B307
B308
B309
B30A
B30B
B30C
B30D
B30E
B30F
B310
B311
B312
B313
B314
B315
B316
B317
B318
B319
B31A
B31B
B31C
B31D
B31E
B31F
B324
B325
B326
B336
B337
B340
B341
B342
B343
B344
B345
B346
B347
B348
B349
B34A
B34B
B34C
B34D
B350
B351
B353
B357
B358
B359
B35B
B35F
B360
B361
B362
B363
B365
B366
B367
B369
B374
B375
B376
B377
B37F
B384
B38C
B394
B395
B396
B398
B399
B39A
B3A4
B3A5
Mnemonic
CPYA
SAR
EAR
CSP
MSR
MVPG
MVST
CUSE
BSG
BSA
CLST
SRST
CMPSC
XSCH
RP
STCKE
SACF
STSI
SRNM
STFPC
LFPC
TRE
CUUTF
CUTFU
STFL
LPSWE
TRAP4
LPEBR
LNEBR
LTEBR
LCEBR
LDEBR
LXDBR
LXEBR
MXDBR
KEBR
CEBR
AEBR
SEBR
MDEBR
DEBR
MAEBR
MSEBR
LPDBR
LNDBR
LTDBR
LCDBR
SQEBR
SQDBR
SQXBR
MEEBR
KDBR
CDBR
ADBR
SDBR
MDBR
DDBR
MADBR
MSDBR
LDER
LXDR
LXER
SQXR
MEER
LPXBR
LNXBR
LTXBR
LCXBR
LEDBR
LDXBR
LEXBR
FIXBR
KXBR
CXBR
AXBR
SXBR
MXBR
DXBR
TBEDR
TBDR
DIEBR
FIEBR
THDER
THDR
DIDBR
FIDBR
LPXR
LNXR
LTXR
LCXR
LXR
LEXR
FIXR
CXR
LZER
LZDR
LZXR
FIER
FIDR
SFPC
EFPC
CEFBR
CDFBR
CXFBR
CFEBR
CFDBR
CFXBR
CEGBR
CDGBR
Op
Code
B3A6
B3A8
B3A9
B3AA
B3B4
B3B5
B3B6
B3B8
B3B9
B3BA
B3C4
B3C5
B3C6
B3C8
B3C9
B3CA
B6
B7
B900
B901
B902
B903
B904
B905
B908
B909
B90A
B90B
B90C
B90D
B90E
B90F
B910
B911
B912
B913
B914
B916
B917
B918
B919
B91A
B91B
B91C
B91D
B91F
B920
B921
B925
B930
B931
B946
B980
B981
B982
B986
B987
B988
B989
B98D
B990
B991
B992
B993
B996
B997
B998
B999
B99D
BA
BB
BD
BE
BF
C00
C04
C05
D1
D2
D3
D4
D5
D6
D7
D9
DA
DB
DC
DD
DE
DF
E1
E2
E303
E304
E308
E309
E30A
E30B
E30C
E30D
E30E
E30F
E314
E315
E316
E317
E318
E319
Mnemonic
CXGBR
CGEBR
CGDBR
CGXBR
CEFR
CDFR
CXFR
CFER
CFDR
CFXR
CEGR
CDGR
CXGR
CGER
CGDR
CGXR
STCTL
LCTL
LPGR
LNGR
LTGR
LCGR
LGR
LURAG
AGR
SGR
ALGR
SLGR
MSGR
DSGR
EREGG
LRVGR
LPGFR
LNGFR
LTGFR
LCGFR
LLGFR
LCGR
LLGTR
AGFR
SGFR
ALGFR
SLGFR
MSGFR
DSGFR
LRVR
CGR
CLGR
STURG
CGFR
CLGFR
BCTGR
NGR
OGR
XGR
MLGR
DLGR
ALCGR
SLBGR
EPSW
TRTT
TRTO
TROT
TROO
MLR
DLR
ALCR
SLBR
ESEA
CS
CDS
CLM
STCM
ICM
LARL
BRCL
BRASL
MVN
MVC
MVZ
NC
CLC
OC
XC
MVCK
MVCP
MVCS
TR
TRT
ED
EDMK
PKU
UNPKU
LRAG
LG
AG
SG
ALG
SLG
MSG
DSG
CVBG
LRVG
LGF
LGH
LLGF
LLGT
AGF
SGF
Machine Instructions by Operation Code (Cont'd)
Op
Code
E31A
E31B
E31C
E31D
E31E
E31F
E320
E321
E324
E32E
E32F
E330
E331
E33E
E33F
E346
E380
E381
E382
E386
E387
E388
E389
E38E
E38F
E390
E391
E396
E397
E398
E399
E500
E501
E502
E50E
E50F
E8
E9
EA
EB04
EB0A
EB0B
EB0C
EB0D
EB0F
EB1C
EB1D
EB20
EB24
EB25
EB26
EB2C
EB2F
EB30
EB3E
EB44
EB45
EB80
EB8E
EB8F
EB96
EBC0
EC44
EC45
ED04
ED05
ED06
ED07
ED08
ED09
ED0A
ED0B
ED0C
ED0D
ED0E
ED0F
ED10
ED11
ED12
ED14
ED15
ED17
ED18
ED19
ED1A
ED1B
ED1C
ED1D
ED1E
ED1F
ED24
ED25
ED26
ED34
ED35
ED37
EE
EF
F0
F1
F2
F3
F8
F9
FA
FB
FC
FD
Mnemonic
ALGF
SLGF
MSGF
DSGF
LRV
LRVH
CG
CLG
STG
CVDG
STRVG
CGF
CLGF
STRV
STRVH
BCTG
NG
OG
XG
MLG
DLG
ALCG
SLBG
STPQ
LPQ
LLGC
LLGH
ML
DL
ALC
SLB
LASP
TPROT
STRAG
MVCSK
MVCDK
MVCIN
PKA
UNPKA
LMG
SRAG
SLAG
SRLG
SLLG
TRACG
RLLG
RLL
CLMH
STMG
STCTG
STMH
STCMH
LCTLG
CSG
CDSG
BXHG
BXLEG
ICMH
MVCLU
CLCLU
LMH
TP
BRXHG
BRXLG
LDEB
LXDB
LXEB
MXDB
KEB
CEB
AEB
SEB
MDEB
DEB
MAEB
MSEB
TCEB
TCDB
TCXB
SQEB
SQDB
MEEB
KDB
CDB
ADB
SDB
MDB
DDB
MADB
MSDB
LDE
LXD
LXE
SQE
SQD
MEE
PLO
LMD
SRP
MVO
PACK
UNPK
ZAP
CP
AP
SP
MP
DP
13
Condition Codes
Condition Code
Mask Bit Value
General
Instructions
Add
Add Halfword
Add Halfword
Immediate
Add Logical
0
8
1
4
2
2
3
1
Zero
Zero
Zero
< Zero
< Zero
< Zero
> Zero
> Zero
> Zero
Overflow
Overflow
Overflow
Zero,
no carry
Zero,
no carry
Zero
Sixteen bits
zero
Checksum
complete
Not zero,
no carry
Not zero,
no carry
Not zero
Sixteen bits
not zero
----
Zero,
carry
Zero,
carry
-------
Not zero,
carry
Not zero,
carry
-------
----
Compare
Equal
Compare and Form

Codeword
Equal
Compare and Swap

Compare Double
and Swap
Compare Halfword
Equal
Equal
First op
low
First op
low and
ctl = 0,
or first op
high and
ctl = 1
Not equal
Not equal
First op
high
First op
high and
ctl = 0,
or first op
low and
ctl = 1
-------
CPU-determined
completion
----
Compare Halfword
Immediate
Compare Logical
Equal
Compare Logical
Characters under
Mask
Compare Logical
Long
Compare Logical
Long Extended
Equal, or
Mask is
zero
Equal
First
low
First
low
First
low
First
low
First
high
First
high
First
high
First
high
Equal
Compare Logical
Long Unicode
Add Logical with

Carry
And
And Immediate
Checksum
Equal
-------
op
----
op
----
op
----
op
----
First op
low
First op
low
First op
high
First op
high
----
Equal
First op
low
First op
high
Compare Logical
String
Equal
First op
low
First op
high
Compare until Substring Equal
Equal
substring
Second op
end
Last
bytes
unequal
----
Equal
op
----
op
op
op
Convert Unicode to
UTF-8
Data
processed
Last
bytes
equal
First op
end, not
second op
end
First op
full
Convert UTF-8 to
Unicode
Data
processed
First op
full
----
Exclusive Or
Insert Characters
under Mask
Zero
All zero,
or mask
is zero
Not zero
Leftmost
bit = 1
Load and Test

Load Complement
Load Negative
Load Positive
Move Long
Zero
Zero
Zero
Zero
Operand
lengths
equal
Operand
lengths
equal
Operand
lengths
equal
Data
moved
< Zero
< Zero
< Zero
---First op
shorter
---Not zero,
but with
leftmost
bit = 0
> Zero
> Zero
---> Zero
First op
longer
First op
shorter
First op
longer
First op
shorter
First op
longer
First op
invalid,
both valid
in ES,
locked, or
ES error
Second op
moved
Second op
invalid
Compression Call
Move Long
Extended
Move Long Unicode
Move Page
Move String
14
----
----
----
CPU-determined
completion
CPU-determined
completion
CPU-determined
completion
CPU-determined
completion
CPU-determined
completion
CPU-determined
completion
CPU-determined
completion
-------
---Overflow
---Overflow
Overlap
CPU-determined
completion
CPU-determined
completion
----
CPU-determined
completion
Condition Codes (Cont'd)
Condition Code
Mask Bit Value
Or
Or Immediate
0
8
Zero
Sixteen bits
zero
Equal
1
4
Not zero
Sixteen bits
not zero
First op
not equal
Perform Locked
Operation (test
bit one)
Search String
Code
valid
2
2
3
1
-------
----------
----
First op
equal,
third op
not equal
----
----
Character
found
Character
not found
Set Program Mask

Shift Left Double
Shift Left Single
Shift Right Double
Shift Right Single
Store Clock
See Note
Zero
Zero
Zero
Zero
Set state
See Note
< Zero
< Zero
< Zero
< Zero
Not-set
state
See Note
> Zero
> Zero
> Zero
> Zero
Error
state
Store Clock
Set state
Not-set
state
Error
state
Subtract
Subtract Halfword
Subtract Logical
Zero
Zero
----
Subtract Logical
with Borrow
Test Addressing
Mode
Test and Set
Zero,
borrow
24-bit
mode
Leftmost
bit zero
All zeros,
or mask
is zero
All zeros
or mask
is zero
< Zero
< Zero
Not zero,
borrow
Not zero,
borrow
31-bit
mode
Leftmost
bit one
Mixed 0's
and 1's
> Zero
> Zero
Zero,
no borrow
Zero,
no borrow
----
CPU-determined
completion
See Note
Overflow
Overflow
------Stopped
state or
not operational
Stopped
state or
not operational
Overflow
Overflow
Not zero,
no borrow
Not zero,
no borrow
----
----
----
---
All ones
Mixed 0's
and 1's and
leftmost
bit one
Mixed 0's
and 1's and
leftmost
bit one
Not zero,
scan
complete
----
All ones
Perform Locked
Operation (test
bit zero)
Test under Mask

(TM)
Test under Mask
(TMHH, TMHL,
TMLH, TMLL)
Code
invalid
Test under Mask

High, Low
All zeros
or mask
is zero
Translate and Test
All zeros
Translate Extended
Data
processed
Translate One to
One, One to
Two, Two to
One, Two to Two
Unpack ASCII
Character
not found
Mixed 0's
and 1's and
leftmost
bit zero
Mixed 0's
and 1's and
leftmost
bit zero
Not zero,
scan
incomplete
First op
byte equal
test byte
Character
found
Sign plus
Sign minus
----
Unpack Unicode
Sign plus
Sign minus
----
Update Tree
Compare
equal at
current
node on
path
Path
complete,
no nodes
compared
equal
----
Zero
Equal
< Zero
First op
low
< Zero
< Zero
< Zero
> Zero
First op
high
> Zero
> Zero
> Zero
Overflow
----
< Zero
Sign
invalid
> Zero
Digit
invalid
Zero and Add
Zero
Digits
and sign
valid
Zero
< Zero
> Zero
Overflow
Sign and
digit
invalid
Overflow
Floating-Point
Instructions
Add
Add Normalized
Add Unnormalized
Compare (BFP)
Zero
Zero
Zero
Equal
< Zero
< Zero
< Zero
First op
low
> Zero
> Zero
> Zero
First op
high
Decimal
Instructions
Add Decimal
Compare Decimal
Edit
Edit and Mark
Shift and Round
Decimal
Subtract Decimal
Test Decimal
Zero
Zero
Zero
----
All ones
---CPU-determined
completion
CPU determinded
completion
Sign
invalid
Sign
invalid
Path not
complete
and compared
register
negative
------Overflow
NaN
------Unordered
15
Condition Code
Mask Bit Value
Compare (HFP)
0
8
Equal
Compare and
Signal
Convert BFP to
HFP
Convert HFP to
BFP
Convert to Fixed
Equal
Zero
1
4
First op
low
First op
low
< Zero
2
2
First op
high
First op
high
> Zero
Zero
< Zero
> Zero
Zero
< Zero
> Zero
Divide to Integer
Remainder
complete,
quotient
normal
Remainder
incomplete,
quotient
normal
Load and Test

(BFP)
Load and Test
(HFP)
Load Complement
(BFP)
Load Complement
(HFP)
Load Negative
(BFP)
Load Negative
(HFP)
Load Positive
(BFP)
Load Positive
(HFP)
Subtract
Subtract Normalized
Subtract Unnormalized
Test Data Class
Zero
Remainder
complete,
quotient
overflow
or NaN
< Zero
Zero
< Zero
> Zero
----
Zero
< Zero
> Zero
NaN
Zero
< Zero
> Zero
----
Zero
< Zero
----
NaN
Zero
< Zero
----
----
Zero
----
> Zero
NaN
Zero
----
> Zero
----
Zero
Zero
< Zero
< Zero
> Zero
> Zero
NaN
----
Zero
< Zero
> Zero
----
Zero (no
match)
One
(match)
----
----
Equal
Not equal
----
----
See note
Branch
state
entry
See note
----
See note
----
Primaryspace
mode
Parameters
loaded
See note
Program
call
state
entry
Secondaryspace
mode
Primary
not
available
Homespace
mode
Spaceswitch
event
Load PSW
Load PSW
Extended
Load Real Address
See note
See note
See note
See note
Accessregister
mode
Secondary
not authorized
or not
available
See note
See note
Translation
available
Move to Primary
Length
256
Length
256
Length
256
Operation
completed
Segmenttable
entry
invalid
----
Pagetable
entry
invalid
----
----
----
----
----
ES data
error
----
Control
Instructions
Compare and Swap
and Purge
Diagnose
Extract Stacked
State
Insert Address
Space Control
Load Address
Space Parameters
Move to Secondary
Move with Key
Page In
> Zero
Page Out
Operation
completed
ES data
error
----
Program Return
Reset Reference
Bit Extended
Resume Program
Set Clock
See note
Ref = 0,
Chg = 0
See note
Set
See note
Ref = 0,
Chg = 1
See note
Secure
See note
Ref = 1,
Chg = 0
See note
----
Signal Processor
Accepted
Info
provided
ALET = 0
Status
stored
----
Busy
Store System Information

Test Access
ALET
uses
DUALD
ALET
uses
PSALD
Test Block
Usable
Unusable
----
16
----
3
1
---Unordered
Special
case
Special
case
Special
case
Remainder
incomplete,
quotient
overflow
or NaN
NaN
See note
See note
See note
Length
> 256
Length
> 256
Length
> 256
ES block
not available
ES block
not available
See note
Ref = 1,
Chg = 1
See note
Not operational
Not operational
Info not
available
ALET = 1
or causes
ART
exception
----
Condition Code
Mask Bit Value
Test Protection
Input/Output
Instructions
Cancel Subchannel
Clear Subchannel
Halt Subchannel
Modify Subchannel
Reset Channel Path
Resume Subchannel
Start Subchannel
Store Channel
Report Word
Store Subchannel
Test Pending Interruption
Test Subchannel
0
8
Fetch and
store
allowed
1
4
Fetch
allowed;
no store
allowed
2
2
No fetch
or store
allowed
3
1
Translation
not available
Function
started
Function
started
Function
started
----
----
----
----
Nonintermediate
status
pending
Status
pending
----
Busy
Not operational
Not operational
Not operational
Status
pending
Status
pending
Zeros
stored
----
Not
applicable
Busy
Interruption
code
stored
Status
was not
pending
----
Function
executed
Function
started
Function
started
Function
started
CRW
stored
SCHIB
stored
Interruption
not pending
Status
was
pending
Busy
Busy
-------
----
Not operational
Not operational
Not operational
Not operational
---Not operational
----
Not operational
Notes:
For Diagnose, the resulting condition code is model-dependent.
For Load Real Address, condition code 3 is set if address-space-control element not
available, region-table entry outside table or invalid, segment-table entry outside table,
or, for LRA in 24- or 31-bit mode when bits 0-32 of entry address not all zeros, segmentor page-table entry invalid.
For Load PSW, Load PSW Extended, and Resume Program, the condition code is
loaded from the condition-code field of the second operand.
For Set Program Mask, the condition code is loaded from bit positions 2 and 3 of the
first operand.
Operand of Store Clock
Bits -63 of
Time-of-Day (TOD) Clock
63
Note: Bit 51 of the TOD clock corresponds to one microsecond.
Operand of Store Clock Extended
Programmable
Zeros
Time-of-Day (TOD) Clock
Field
8
112
127
Note: Bit 51 of the TOD clock (bit 59 of the operand) corresponds to one
microsecond.
Assembler Instructions
Function
Option
control
Mnemonic
*PROCESS
ACONTROL
Meaning
Specify assembler options
Dynamically modify options
17
Assembler Instructions (Cont'd)
Function
Data
definition
DSECT
DXD
ENTRY
EXTRN
LOCTR
RMODE
RSECT
START
WXTRN
XATTR
Meaning
Define channel command word
Define format-0 channel command word
Define format-1 channel command word
Define constant
Define storage
Rename external symbol
Specify addressing mode
Define class name and attributes
Identify common control section
Identify control section
Cumulative length of external dummy
section
Identify dummy section
Define external dummy section
Identify entry-point symbol
Identify external symbol
Specify multiple location counters
Specify residence mode
Identify read-only control section
Start assembly
Identify weak external symbol
Declare external symbol attributes
Base register
assignment
DROP
USING
Drop base address register

Use base address and register
Control of
listings
AEJECT
ASPACE
CEJECT
EJECT
PRINT
SPACE
TITLE
Start new page in macro definition

Space lines in macro definition
Conditional start new page
Start new page
Print optional data
Space listing
Identify assembly output
Program
control
ADATA
CNOP
COPY
END
EQU
EXITCTL
ICTL
ISEQ
LTORG
OPSYN
ORG
POP
Provide data for SYSADATA file

Conditional no operation
Copy predefined source coding
End assembly
Equate symbol
Program control data for I/O exits
Input format control
Input sequence checking
Begin literal pool
Equate operation code
Set location counter
Restore ACONTROL, PRINT, or USING
status
Punch a card
Save current ACONTROL, PRINT, or
USING status
Reproduce following card
Program
sectioning
and linking
Mnemonic
CCW
CCW0
CCW1
DC
DS
ALIAS
AMODE
CATTR
COM
CSECT
CXD
PUNCH
PUSH
REPRO
Conditional
assembly
ACTR
AGO
AIF
AINSERT
ANOP
AREAD
GBLA
GBLB
GBLC
LCLA
LCLB
LCLC
MHELP
MNOTE
SETA
SETAF
SETB
SETC
SETCF
Macro
definition
MACRO
MEND
MEXIT
Conditional assembly branch counter

Unconditional branch
Conditional branch
Create input record
Assembly no operation
Assign input record to SETC symbol
Define global SETA symbol
Define global SETB symbol
Define global SETC symbol
Define local SETA symbol
Define local SETB symbol
Define local SETC symbol
Trace macro flow
Generate error message
Set arithmetic variable symbol
Set arithmetic variable symbol from
external function
Set binary variable symbol
Set character variable symbol
Set character variable symbol from
external function
Macro definition header
Macro definition trailer
Macro definition exit
Source: SC26-4940.
18
Extended-Mnemonic Instructions for Branch

on Condition
Extended Mnemonic*
(RX or RR)
Meaning
B or BR
Unconditional Branch
NOP or NOPR
No Operation
Machine Instr.*
(RX or RR)
BC or BCR 15,
BC or BCR 0,
After
Compare
Instructions
(A:B)
BH or BHR
BL or BLR
BE or BER
BNH or BNHR
BNL or BNLR
BNE or BNER
Branch
Branch
Branch
Branch
Branch
Branch
on
on
on
on
on
on
A
A
A
A
A
A
BC
BC
BC
BC
BC
BC
or
or
or
or
or
or
BCR
BCR
BCR
BCR
BCR
BCR
2,
4,
8,
13,
11,
7,
After
Arithmetic
Instructions
BP or BPR
BM or BMR
BZ or BZR
BO or BOR
BNP or BNPR
BNM or BNMR
BNZ or BNZR
BNO or BNOR
Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch
on
on
on
on
on
on
on
on
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
BC
BC
BC
BC
BC
BC
BC
BC
or
or
or
or
or
or
or
or
BCR
BCR
BCR
BCR
BCR
BCR
BCR
BCR
2,
4,
8,
1,
13,
11,
7,
14,
After Test
under Mask
instruction
BO or BOR
BM or BMR
BZ or BZR
BNO or BNOR
BNM or BNMR
BNZ or BNZR
Branch
Branch
Branch
Branch
Branch
Branch
if
if
if
if
if
if
BC
BC
BC
BC
BC
BC
or
or
or
or
or
or
BCR
BCR
BCR
BCR
BCR
BCR
1,
4,
8,
14,
11,
7,
Use
General
High
Low
Equal B
Not High
Not Low
Not Equal B
Ones
Mixed
Zeros
Not Ones
Not Mixed
Not Zeros
Source: SC26-4940.
*Second operand, not shown, is D% (X%, B%) for RX format and R% for RR format.
Extended-Mnemonic Instructions for

Relative-Branch Instructions
Extended
Mnemonic
BRU or J
BRUL or JLU
JNOP*
Meaning
Unconditional Branch Relative
Unconditional Branch Relative
No Operation
Machine
Instr.
BRC 15,I%
BRCL 15,I%
BRC 0,I%
After
Compare
Instructions
(A:B)
BRH or JH*
BRL or JL*
BRE or JE*
BRNH or JNH*
BRNL or JNL*
BRNE or JNE*
Branch
Branch
Branch
Branch
Branch
Branch
Relative
Relative
Relative
Relative
Relative
Relative
on
on
on
on
on
on
A
A
A
A
A
A
BRC
BRC
BRC
BRC
BRC
BRC
2,I%
4,I%
8,I%
13,I%
11,I%
7,I%
After
Arithmetic
Instructions
BRP or JP*
BRM or JM*
BRZ or JZ*
BRO or JO*
BRNP or JNP*
BRNM or JNM*
BRNZ or JNZ*
BRNO or JNO*
Branch
Branch
Branch
Branch
Branch
Branch
Branch
Branch
Relative
Relative
Relative
Relative
Relative
Relative
Relative
Relative
on
on
on
on
on
on
on
on
Plus
Minus
Zero
Overflow
Not Plus
Not Minus
Not Zero
No Overflow
BRC
BRC
BRC
BRC
BRC
BRC
BRC
BRC
2,I%
4,I%
8,I%
1,I%
13,I%
11,I%
7,I%
14,I%
After Test
under Mask
instruction
BRO or JO*
BRM or JM*
BRZ or JZ*
BRNO or JNO*
BRNM or JNM*
BRNZ or JNZ*
Branch
Branch
Branch
Branch
Branch
Branch
Relative
Relative
Relative
Relative
Relative
Relative
if
if
if
if
if
if
BRC
BRC
BRC
BRC
BRC
BRC
1,I%
4,I%
8,I%
14,I%
11,I%
7,I%
Non-Branch
Relative on
Condition
JAS
JASL
JCT
JCTG
JXH
JXHG
JXLE
JXLEG

Branch Relative and Save Long
Branch Relative on Index High
Branch Relative on Index High
Br. Rel. on Index Low or Equal
Br. Rel. on Index Low or Equal
Use
General
Branch Rel.
on Condition
High
Low
Equal B
Not High
Not Low
Not Equal B
Ones
Mixed
Zeros
Not Ones
Not Mixed
Not Zeros
BRAS R$,I%
BRASL R$,I%
BRCT R$,I%
BRCTG R$,I%
BRXH R$,R,,I%
BRXHG R$,R,,I%
BRXLE R$,R,,I%
BRXLG R$,R,,I%
Source: SC26-4940.
*To obtain BRCL instead of BRC, add L at the end of the B mnemonic or insert L after
the J of the J mnemonic. For example, change BRNZ or JNZ to BRNZL or JLNZ.
19
CNOP Alignment
Doubleword
Word
Word
Halfword Halfword Halfword Halfword
Byte Byte Byte Byte Byte Byte Byte Byte
E
E
E
E
,4
2,4
,4
2,4
,8
2,8
4,8
6,8
Source: SC26-4940.
Summary of Constants
Type
A
AD
B
C
CU
D
DB
DH
E
EB
EH
F
FD
G
H
J
L
LB
LH
P
Q
R
S
V
X
Y
Z
Implied
Length,
Bytes
4
8
8
8
8
4
4
4
4
8
Even
2
4
Alignment
Word
Doubleword
Byte
Byte
Byte
Doubleword
Doubleword
Doubleword
Word
Word
Word
Word
Doubleword
Byte
Halfword
Word
16
16
16
4
4
2
4
2
-
Doubleword
Doubleword
Doubleword
Byte
Word
Word
Halfword
Word
Byte
Halfword
Byte
Format
Value of address
Value of address
Binary digits
Characters
Characters, translated to Unicode
Long hex floating point
Long binary floating point
Long hex floating point
Short hex floating point
Short binary floating point
Short hex floating point
Fixed-point binary
Fixed-point binary
Graphic (double-byte) characters
Fixed-point binary
Symbol naming a DXD, DSECT, or
class
Extended hex floating point
Extended binary floating point
Extended hex floating point
Packed decimal
Symbol naming a DXD or DSECT
PSECT address value
Address in base-displacement form
Externally defined address value
Hexadecimal digits
Value of address
Zoned decimal
Truncation/
Padding
Left
Left
Left
Right
Right
Right
Right
Right
Right
Right
Right
Left
Left
Right
Left
Left
Right
Right
Right
Left
Left
Left
Left
Left
Left
Source: SC26-4940.
Fixed Storage Locations

Area
(Dec)
128-131
132-133
Addr Hex
Type Addr
R
80
R
84
134-135
86
136-139
88
140-143
8C
144-147
90
148-149
94
150-151
96
152-159
160
R
R
98
A0
161
A1
20
Function
External-interruption parameter
CPU address associated with external interruption, or zeros
External-interruption code (see table on
page 21)
SVC-interruption identification (0-12 zeros,
13-14 ILC, 15 zero, 16-31 code)
Program-interruption identification (0-12
zeros, 13-14 ILC, 15 zero, 16-31 code)
Data-exception code (0-23 zeros, 24-31
code (see table on page 23))
Monitor-class number (0-7 zeros, 8-15
number)
PER code (0 successful branching, 1
instruction fetching, 2 storage alteration, 2
and 4 stura, 3 and 5-8 zeros, 8-13 ATMID,
14-15 AI)
PER address
Exception access identification (0-3 zeros,
4-7 access-register number)
PER access identification (0-3 zeros, 4-7
access-register number)
Fixed Storage Locations (Cont'd)
Area
(Dec)
162
Addr Hex
Type Addr
R
A2
163
A/R
A3
168-175
A8
176-183
184-187
R
R
B0
B8
188-191
192-195
R
R
BC
C0
200-203
C8
232-239
E8
244-247
F4
248-255
288-303
304-319
320-335
336-351
352-367
368-383
416-431
432-447
448-463
464-479
480-495
496-511
4544-4607
4608-4735
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A/R
F8
120
130
140
150
160
170
1A0
1B0
1C0
1D0
1E0
1F0
11C0
1200
4736-4863
A/R
1280
4864-4879
A/R
1300
4888-4891
4892-4895
A
A/R
1318
131C
4900-4903
A/R
1324
4904-4911
A/R
1328
4913-4919
A/R
1331
4928-4991
A/R
1340
4992-5119
A/R
1380
Function
Operand access identification (if pagetranslation exception recognized by Move
Page: 0-3 R$, 4-7 R%)
Store-status/machine-check architecturalmode identification (0-6 zeros, 7 one)
Translation-exception identification (see
table on page 23)
Monitor code
Subsystem-identification word (0-14 zeros,
15 one, 16-31 subchannel number)
I/O-interruption parameter
I/O-interruption-identification word (0-1
zeros, 2-4 I/O-interruption subclass, 5-31
zeros)
STFL facility list (0 certain z/Architecture
instructions available, 1 z/Architecture
installed, 2 z/Architecture active, 16
extended-translation facility 2 installed)
Machine-check-interruption code (see
diagram on page 41)
External-damage code (see diagram on
page 41)
Failing-storage address
Restart old PSW
External old PSW
Supervisor-call old PSW
Program old PSW
Machine-check old PSW
Input/output old PSW
Restart new PSW
External new PSW
Supervisor-call new PSW
Program new PSW
Machine-check new PSW
Input/output new PSW
Available for programming
Store-status/machine-check floating-pointregister save area
Store-status/machine-check general-register
save area
Store-status PSW save area or machinecheck fixed-logout area*
Store-status prefix save area
Store-status/machine-check floating-pointcontrol-register save area
Store-status/machine-check
TOD-programmable-register save area
Store-status/machine-check CPU-timer
save area
Store-status/machine-check clockcomparator bits 0-55 save area (zeros at
4912)
Store-status/machine-check access-register
save area
Store-status/machine-check control-register
save area
A=Absolute address. R=Real address.

A/R=A if store status, R if machine check.
* Contents may vary among models; see System Library manuals.
External-Interruption Codes
At real-storage locations 134-135 (86-87 hex)
21
Code
(Hex)
0040
1004
1005
1200
1201
1202
1406
2401
Condition
Interrupt key
Clock comparator
CPU timer
Malfunction alert
Emergency signal
External call
ETR
Service signal
Program-Interruption Codes
At real-storage locations 142-143 (8E-8F hex)
Code
(Hex)
0001
0002
0003
0004
0005
0006
0007
0008
0009
000A
000B
000C
000D
000E
000F
0010
0011
0012
0013
0015
0016
001C
001D
001F
0020
0021
0022
0023
0024
0025
0028
0029
002A
002B
002C
002D
0030
0031
0032
0033
0034
0038
0039
003A
003B
0040
0080
0119
22
Condition
Operation exception
Privileged-operation exception
Execute exception
Protection exception
Addressing exception
Specification exception
Data exception
Fixed-point-overflow exception
Fixed-point-divide exception
Decimal-overflow exception
Decimal-divide exception
HFP-exponent-overflow exception
HFP-exponent-underflow exception
HFP-significance exception
HFP-floating-point-divide exception
Segment-translation exception
Page-translation exception
Translation-specification exception
Special-operation exception
Operand exception
Trace-table exception
Space-switch event
HFP-square-root exception
PC-translation-specification exception
AFX-translation exception
ASX-translation exception
LX-translation exception
EX-translation exception
Primary-authority exception
Secondary-authority exception
ALET-specification exception
ALEN-translation exception
ALE-sequence exception
ASTE-validity exception
ASTE-sequence exception
Extended-authority exception
Stack-full exception
Stack-empty exception
Stack-specification exception
Stack-type exception
Stack-operation exception
ASCE-type exception
Region-first-translation exception
Region-second-translation exception
Region-third-translation exception
Monitor event
PER event (code may be combined with another code)
Crypto-operation exception
Translation-Exception Identification
At real-storage locations 168-175 (A8-AF hex)
Interruption
Code
(Hex)
0004
Exception or
Event
Protection
0010,
0038,
0039,
003A,
003B
0011
Segment translation; ASCE

type; region-first,
second, third
translation
Page translation
001C
Space switch
0020
0021
0022
0023
0024
0025
AFX translation
ASX translation
LX translation
EX translation
Primary authority
Secondary
authority
Format of Information Stored*

If 61 zero: rest unpredictable
If 61 one: suppression, 0-51 address; if
DAT was on, 60 one if access-listcontrolled protection, 62-63 ASCE identification, rest unpredictable, location 160
valid; if DAT was off, rest unpredictable
0-51 address, 52-61 unpredictable, 62-63
ASCE identification
0-51 address, 52-60 unpredictable, if 61

zero, not Move Page; if 61 one, Move
Page (see location 162); 62-63 ASCE
identification
From primary-space mode: 32 old
primary-space-switch-event control, 33-47
zeros, 48-63 old PASN
From home-space mode: 32 home-spaceswitch-event control, 33-63 zeros
32-47 zeros, 48-63 address-space number
32-43 zeros, 44-63 program-call number
32-43 zeros, 44-63 program-call number
* Bits 0-31 (bytes 68-71) unchanged if not described.
Data-Exception Code (DXC)

At real-storage location 147 (93 hex) and in byte 2 of floatingpoint-control register
Code
(Hex)
00
01
02
08
0C
10
18
1C
20
28
2C
40
80
Data Exception
Decimal operand
AFP register
BFP instruction
IEEE inexact and truncated
IEEE inexact and incremented
IEEE underflow, exact
IEEE underflow, inexact and truncated
IEEE underflow, inexact and incremented
IEEE overflow, exact
IEEE overflow, inexact and truncated
IEEE overflow, inexact and incremented
IEEE division by zero
IEEE invalid operation
23
Control Registers
CR
0
Bits
33
34
35
36
37
38
39
45
48
49
50
52
53
54
56
57
58
59
61
0-63
0-51
54
55
56
57
58
60-61
62-63
33-57
5
6
32-47
48-63
32-47
48-63
33-57
32-39
0-63
0-51
54
55
56
58
60-61
62-63
8
32-47
48-63
24
Name of Field
SSM-suppression control
TOD-clock-sync control
Low-address-protection
control
Extraction-authority control
Secondary-space control
Fetch-protection-override
control
Storage-protectionoverride control
AFP-register control
Malfunction-alert subclass
mask
Emergency-signal subclass
mask
External-call subclass
mask
Clock-comparator subclass
mask
CPU-timer subclass mask
Service-signal subclass
mask
Unused (See note)
Interrupt-key subclass
mask
Unused (See note)
ETR subclass mask
Crypto control
Primary address-spacecontrol element
Primary region-table or
segment-table origin or
real-space token origin
Primary subspace-group
control
Primary private-space
control
Primary storagealteration-event control
Primary space-switchevent control
Primary real-space
control
Primary designationtype control
Primary table length
Dispatchable-unit-controltable origin
PSW-key mask
Secondary ASN
Authorization index
Primary ASN
Primary-ASTE origin
I/O-interruption subclass
mask
Secondary address-spacecontrol element
Secondary region-table or
Secondary subspace-group
control
Secondary private-space
control
Secondary storagealteration-event control
Secondary real-space
control
Secondary designationtype control
Secondary table length
Extended authorization
index
Monitor masks
Associated with
SSM instruction
TOD clock
Low-address protection
Init*
0
0
0
Instruction authorization
Key-controlled protection
0
0
0
Key-controlled protection
Floating point
External interruptions
0
0
0
0
1
1
Cryptography
Dynamic address
translation
Dynamic address
translation
1
0
0
0
0
Subspace groups
Dynamic address
translation
Program-event recording
Program interruptions
Dynamic address
translation
Dynamic address
translation
Dynamic address
translation
Access-register
translation
Address spaces
Address spaces
Access-register translation
I/O interruptions
0
0
0
0
0
0
0
0
0
0
0
Dynamic address
translation
Dynamic address
translation
Subspace groups
Dynamic address
translation
Dynamic address
translation
Dynamic address
translation
Dynamic address
translation
Access-register
translation
MC instruction
0
0
0
0
Control Registers (Cont'd)
CR
9
Bits
32
33
34
36
40
42
10
11
12
13
0-63
0-63
0
1
2-61
62
63
0-63
0-51
54
55
56
57
58
60-61
62-63
14
32
33
35
36
37
38
39
42
15
44
45-63
0-60
Name of Field
Successful-branchingevent mask
Instruction-fetchingevent mask
Storage-alterationevent mask
Store-using-real-addressevent mask
Branch-address control
Storage-alteration-space
control
PER starting address
PER ending address
Branch-trace control
Mode-trace control
Trace-entry address
ASN-trace control
Explicit-trace control
Home address-spacecontrol element
Home region-table or
Home subspace-group
control
Home private-space
control
Home storagealteration-event control
Home space-switchevent control
Home real-space
control
Home designationtype control
Home table length
Unused (See note)
Unused (See note)
Channel-report-pending
subclass mask
Recovery subclass mask
Degradation subclass mask
External-damage subclass
mask
Warning subclass mask
TOD-clock-controloverride control
ASN-translation control
ASN-first-table origin
Linkage-stack-entry
address
Associated with
Init*
0
0
0
Tracing
Tracing
Tracing
Tracing
Tracing
Dynamic address
translation
Dynamic address
translation
0
0
0
0
0
0
0
0
Subspace groups
Dynamic address
translation
Program interruptions
Dynamic address
translation
Dynamic address
translation
Dynamic address
translation
I/O machine-check
handling
Machine-check handling
0
0
0
0
1
1
0
0
0
1
TOD clock
0
0
ASN translation
Linkage-stack operations
0
0
0
* Value after initial CPU reset.

Note: This bit is not used but is initialized to one for consistency with the
System/370 definition.
Floating-Point-Control (FPC) Register

MasksFlags
i z o u x
i z o u x
DXC
RM
8
16
24
31
Bit
0
1
2
3
4
8
9
10
11
12
16-23
30-31
Meaning
(IMi) IEEE-invalid-operation mask
(IMz) IEEE-division-by-zero mask
(IMo) IEEE-overflow mask
(IMu) IEEE-underflow mask
(IMx) IEEE-inexact mask
(SFi) IEEE-invalid-operation flag
(SFz) IEEE-division-by-zero flag
(SFo) IEEE-overflow flag
(SFu) IEEE-underflow flag
(SFx) IEEE-inexact flag
(DXC) Data-exception code (see table on page 23)
(RM) Rounding mode
00 Round to nearest
01 Round toward 0
10 Round toward +
11 Round toward
25
Program-Status Word (PSW)

z/Architecture PSW
PSW Program
E
R TIEKey MWPASCC Mask
A
5
8 12
16 18 2
24
31
32
63
Bits -31 of Instruction Address
64
95
Bits 32-63 of Instruction Address
96
127
Bit
1
5
6
7
12
13
14
15
16-17
18-19
20
21
22
23
31/32
Meaning
(R) Program-event-recording mask
(T = 1) DAT mode
(I) Input/output mask
(E) External mask
Zero indicates z/Architecture
(M) Machine-check mask
(W = 1) Wait state
(P = 1) Problem state
(AS) Address-space control
xx Real mode (T = 0)
00 Primary-space mode (T = 1)
01 Access-register mode (T = 1)
10 Secondary-space mode (T = 1)
11 Home-space mode (T = 1)
(CC) Condition code
Fixed-point-overflow mask
Decimal-overflow mask
HFP-exponent-underflow mask
HFP-significance mask
Extended/basic addressing mode
00 24-bit mode
01 31-bit mode
10 Invalid
11 64-bit mode
ESA/390 PSW
PSW Program
R TIEKey 1MWPASCC Mask
5
8 12
16 18 2
24
31
A
Instruction Address
32
63
Bit
12
32
26
Meaning
One indicates ESA/390
(A = 1) 31-bit addressing mode
Dynamic Address Translation

Virtual-Address Format
L11ML11ML11ML11ML8ML12M
RFX RSX RTX SX

PX
BX
11
22
33
44
52
63
LRX 33M
Bit
RX
RFX
RSX
RTX
SX
PX
BX
Meaning
Region index (region = 2G bytes)
Region first index
Region second index
Region third index
Segment index (segment = 1M bytes)
Page index (page = 4K bytes)
Byte index
Address-Space-Control Element (ASCE)

Region-Table or Segment-Table Designation (RTD
or STD)
Region-Table or Segment-Table Origin GPSXR DTTL
52 54
58 6
63
Bit
54
55
56
57
58
60-61
62-63
Meaning
(G) Subspace-group control
(P) Private-space control
(S) Storage-alteration-event control
(X) Space-switch-event control
(R) Real-space control (R = 0)
(DT) Designation-type control
11 Region-first-table
10 Region-second-table
01 Region-third-table
00 Segment-table
(TL) Table length ( 4K bytes)
Real-Space Designation (RSD)
Real-Space Token Origin

GPSXR
52 54
58
63
Bit
Meaning
58
(R) Real-space control (R = 1)
Note: Other bits are as in RTD or STD.
Table Values
Inc-
Incr.
Max Max Table Maps
re- Incr.Ent- Max Ent-
Table
mentsSize ries Size ries Regions Bytes
Region First 1-4 4KB 512 16KB 2K 8G 16E=162QR

Region Second 1-4 4KB 512 16KB 2K 4M 8P= 82SR
Region Third 1-4 4KB 512 16KB 2K 2K 4T= 42TR
Segment
1-4 4KB 512 16KB 2K 1
2G= 22UR
Page
1 2KB 256 2KB 256 - 1M= 2VR
27
Dynamic Address Translation (Cont'd)
Region-Table Entry (RTE)

Region-First-Table Entry (RFTE)
Region-Second-Table Origin
TFI TTTL
52 56 58 6
63
Region-Second-Table Entry (RSTE)
Region-Third-Table Origin
TFI TTTL
52 56 58 6
63
Region-Third-Table Entry (RTTE)
Segment-Table Origin
TFI TTTL
52 56 58 6
63
Bit
56-57
58
60-61
62-63
Meaning
(TF) Table offset (for next-lower-level table)
(I) Invalid bit (for set of regions in RFTE or RSTE, or for region in
RTTE)
(TT) Table-type bits (for this table)
11 Region first table
10 Region second table
01 Region third table
(TL) Table length (for next-lower-level table) ( 4K bytes)
Segment-Table Entry (STE)
Page-Table Origin
P ICTT
53 55 58 6
63
Bit
54
58
59
60-61
Meaning
(P) Page-protection bit
(I) Segment-invalid bit
(C) Common-segment bit
(TT) Table-type bits (for this table)
00 Segment table
Page-Table Entry (PTE)
Page-Frame Real Address

IP ////////
52
56
63
Bit
53
53
Meaning
(I) Page-invalid bit
(P) Page-protection bit
ASN Translation
Address-Space Number (ASN)
ASN-First ASN-Second-
Table Index
Table Index
1
15
28
ASN Translation (Cont'd)
ASN-First-Table Entry
I
ASN-Second-Table Origin
1
26
31
Bit
0
Meaning
(I) AFX-invalid bit
ASN-Second-Table Entry (ASTE)

Byte
(Hex)
I
Authority-Table Origin
B
1
3 31
4 Authorization Index
Authority-Table Length
16
28 31
Address-Space-Control Element (ASCE=RTD/STD/RSD) Part 1
8Region or Segment-Table Origin or Real-Space Token Origin
31
RTD or STD Part 2 (R= )
CRegion or Seg.-Table Origin (Cont.) GPSXR DTTL
2 22
26 28 31
RSD Part 2 (R=1)
C Real-Space Token Origin (Cont.) GPSXR
2 22
26
31
1
Primary-Space Access-List Origin
ALL
1
25
31
14
ASN-Second-Table-Entry Sequence Number
31
Linkage-Table Designation (LTD)
18V
Linkage-Table Origin
LTL
1
25
31
1C/////////////////////////////////////////////////////////
31
/
/
3C
31
Byte.Bit
0.0
0.31
10.25-31
18.0
18.25-31
Meaning
(I) ASX-invalid bit
(B) Base-space bit
(ALL) Access-list length ( 128 bytes)
(V) Subsystem-linkage control
(LTL) Linkage-table length ( 128 bytes)
29
PC-Number Translation
Program-Call Number
Linkage Index
Entry Index
12
24
31
Linkage-Table Entry (LTE)
I
Entry-Table Origin
ETL
1
26
31
Bit
0
26-31
Meaning
(I) LX-invalid bit
(ETL) Entry-table length ( 128 bytes)
Entry-Table Entry (ETE)

Byte
(Hex)
If Bit 1 .1 (G) Is Zero
31
4A
Bits 33-62 of Entry Instruction Address
P
1
31
If Bit 1 .1 (G) Is One
Bits -31 of Entry Instruction Address
31
4
Bits 32-62 of Entry Instruction Address
P
31
8 Authorization Key Mask

Address-Space Number
16
31
C
Entry Key Mask
16
31
1 TGKMECS EK
Entry Ext. Auth. Index
1 3
8
12
16
31
14
ASN-Second-Table-Entry Address
1
26
31
18
Bits -31 of Entry Parameter
31
1C
Bits 32-63 of Entry Parameter
31
30
PC-Number Translation (Cont'd)
Entry-Table Entry (ETE) (Cont'd)

Byte.Bit
4.0
4.31
10.0
10.1
10.3
10.4
10.5
10.6
10.7
10.8-11
Meaning
(A) Entry addressing mode
(P) Entry problem state
(T) PC-type bit (zero: basic; one: stacking)
(G) Entry extended addressing mode
(K) PSW-key control (zero: unchanged; one: replace if stacking
(M) PSW-key-mask control (zero: Or; one: replace if stacking)
(E) EAX control (zero: unchanged; one: replace if stacking)
(C) Address-space-control control
(S) Secondary-ASN control
(EK) Entry key
Access-Register Translation
Access-List-Entry Token (ALET)
P
ALESN
Access-List-Entry Number
7 8
16
31
Bit
7
8-15
Meaning
(P) Primary-list bit (zero: use DUCT; one: use primary ASTE)
(ALESN) Access-list-entry sequence number
Dispatchable-Unit-Control Table (DUCT)

Byte
(Hex)

Base-ASTE Origin
1
31
4S
A
Subspace-ASTE Origin
1
31
31
C
Subspace-ASTE Sequence Number
31
1
Dispatchable-Unit Access-List Origin
ALL
1
25
31
14
PSW R
PSW-Key Mask
Key A P
16
24 28
31
18
31
1C/////////////////////////////////////////////////////////
31
31
Access-Register Translation (Cont'd)
Dispatchable-Unit-Control Table (DUCT) (Cont'd)

In 24-Bit or 31-Bit Addressing Mode
31
24A
Bits 33-63 of Return Address
1
31
In 64-Bit Addressing Mode
2
Bits -31 of Return Address
31
24
Bits 32-63 of Return Address
31
28
31
2C
Trap-Control-Block Address
E
1
28 31
/
/
3C
31
Byte.Bit
4.0
10.25-31
14.28
14.31
2C.31
///
Meaning
(SA) Subspace-active bit
(ALL) Access-list length ( 128 bytes)
(RA) Reduced-authority bit
(P) Problem-state bit
(E) TRAP-enabled bit
Access-List Entry (ALE)
Access-List-Entry
I
OP
ALESN
Authorization Index
1
6 8
16
31
32
63

ASN-Second-Table-Entry Origin
64
9
95
ASN-Second-Table-Entry Sequence Number
96
127
Bit
0
6
7
8-15
32
Meaning
(I) ALEN-invalid bit
(FO) Fetch-only bit
(P) Private bit
(ALESN) Access-list-entry sequence number
Linkage-Stack Entries
Entry Descriptor
UEntry Type Section ID

Remaining Free Space
1
8
16
31
Next-Entry Size
32
48
63
Bit
0
1-7
Meaning
(U) Unstack-suppression bit
Entry type:
Header entry = 0001001 binary
Trailer entry = 0001010 binary
Branch state entry = 0001100 binary
Program-call state entry = 0001101 binary
Available for program use = 1xxxxxx binary
Header Entry (Entry Type 0001001)
Bits -31 of Backward Stack-Entry Address
31
Bits 32-6 of Backward Stack-Entry Address

B
32
61 63
Entry Descriptor (First Half)
64
95
Entry Descriptor (Second Half)
96
127
Bit
63
Meaning
(B) Backward stack-entry validity bit
Trailer Entry (Entry Type 0001010)
Bits -31 of Forward-Section-Header Address
31
Bits 32-6 of Forward-Section-Header Address

F
32
61 63
Entry Descriptor (First Half)
64
95
Entry Descriptor (Second Half)
96
127
Bit
63
Meaning
(F) Forward-section validity bit
33
Linkage-Stack Entries (Cont'd)
Branch State Entry (Entry Type 0001100) and

Program-Call State Entry (Entry Type 0001101)
Byte
(Hex)
/
Contents of General Registers -15
/
78
63
8 PSW-Key Mask Secondary ASNExt Auth Index Primary ASN
16
32
48
63
88
Bits -63 of Program-Status Word
63
In a Branch State Entry Made in 24-Bit or 31-Bit Mode
9
ABits 33-63 of Branch Adr.
32
63
In a Branch State Entry Made in 64-Bit Mode
9
Bits -62 of Branch Address
1
63
In a Program-Call State Entry Made on a Call to 24-Bit or
31-Bit Mode
9
Called-Space ID

Program-Call Number
32
63
In a Program-Call State Entry Made on a Call to 64-Bit Mode
9
Called-Space ID
1
Program-Call Number
32
63
98
Modifiable Area
63
A
All Zeros
63
A8
Bits 64-127 of Program-Status Word
63
/
Unpredictable
D8
63
/
Contents of Access Registers -15
/
118
63
34
Linkage-Stack Entries (Cont'd)
Branch State Entry (Entry Type

11 ) and
Program-Call State Entry (Entry Type
11 1) (Cont'd)
12
Entry Descriptor
63
Byte.Bit
90.32
Meaning
(A) Addressing mode (in branch state entry)
Trapping
Trap Control Block
Byte
(Hex)
PR
13
31
31
C
Trap-Save-Area Address

1
28 31
31
14
Trap-Program Address
1
31
18/////////////////////////////////////////////////////////
1C/////////////////////////////////////////////////////////
31
/
/
3C
31
Byte.Bit
0.13
0.14
///
Meaning
(P) PSW control (zero: PSW.31 must be zero, ESA/390 PSW
stored; one: z/Architecture PSW stored)
(R) General-register control (zero: bits 32-63 stored; one: bits
0-63 stored)
35
Trapping (Cont'd)
Trap Save Area

Byte
(Hex)
Trap Flags
EW
Zeros
IL
Zeros
1 2
13 15
31
4
Zeros
8
Bits 33-63 of Second-Operand Address of TRAP4
C
Access Register 15
31
PSW Values
If z/Architecture PSW Stored
1
Prog
E
U UUUU UUU UWPASCCMask
A
14B
A
Zeros
18
Bits -31 of Instruction Address
1C
1 2 5
12 14 16 18 2
24
31
If ESA/39 PSW Stored
1
Prog
U UUUU UUU 1UWPASCCMask
14A
18
Zeros
1C
Zeros
1 2 5
12 14 16 18 2
24
31
/
General Registers -15
/
9C
A /////////////////////////////////////////////////////////
A4/////////////////////////////////////////////////////////
A8
/
Unchanged
/
FC
31
Byte.Bit
0.0
0.1
0.13-14
10-1F
U
///
36
Meaning
(E) TRAP was target of EXECUTE
(W) TRAP is TRAP4 (not TRAP2)
(IL) Instruction-length code
PSW values (see PSW on page 26)
Unpredictable
Trace-Entry Formats
Identification of Trace Entries
Trace Entry
Trace-Entry Bits
For-
-7 8-1112-15
Type
mat
Branch
1
1
Set Secondary ASN

1
1
1
Program Call
1
1 1
Program Call
2
11 1
Program Transfer
1
11 1
1
Program Transfer
2
11 1
Program Return
1
11 1
1 Program Return
2
11 1
1
Program Return
4
11 1
1 1 Program Return
5
11 1
11 Program Transfer
3
11 11
11 Program Return
3
11 11
1 11 Program Return
6
11 11
11 Program Return
7
11 11
111 Program Return
8
11 1
1111 Program Return
9
1
1
Branch in Subspace Group 1

1
1
Branch in Subspace Group 2

1 1 1 1
Mode Switch
2
1 1 1 11
Mode Switch
1
1 1 11 1
Mode-Switching Branch 1
1 1 11 11
1 1 1 11
Mode Switch
3
1 1 1 11
Branch
3
1 1 1 1111
111
Trace
1
111
1
Trace
2
1
Branch
2
Branch
F1 (Branch, RP, or TRAP2/4 to 24-Bit Mode)
Bits 4 -63 of Branch Adr.
F2 (Branch, RP, or TRAP2/4 to 31/64-Bit Mode)
1 Bits 33-63 of Branch Address
F3 (Branch, RP, or TRAP2/4 to 64-Bit Mode)
1 1 1 11
All Zeros
Bits 32-63 of Branch Address
Note: Branch is BAKR, BALR, BASR, BASSM, BSA, or BSG.

8
64
12
32
95
63
37
Trace-Entry Formats (Cont'd)
Branch in Subspace Group (if ASN Tracing on)

F1 (in 24/31-Bit Mode)
1
1P Bits 9-31 of ALET A Bits 33-63 of Branch Address
F2 (in 64-Bit Mode)
1
1 P Bits 9-31 of ALET Bits -31 of Branch Address
Mode Switch
F1 (BASSM, BSM, PC, PR, RP, or SAM64 from 24/31-Bit to 64-Bit Mode)
1 1 1 11
All Zeros
A Updated Instruction Address
F2 (BASSM, BSM, PC, PR, RP, SAM24/31 from 64-Bit to 24/31-Bit Mode)
1 1 1 1
All Zeros
Bits 32-63 of Updated Inst. Adr.
F3 (BASSM, BSM, PC, PR, RP, SAM24/31 from 64-Bit to 24/31-Bit Mode)
1 1 1 11
All Zeros
Bits -31 of Updated Inst. Adr.
Mode-Switching Branch
F1 (BASSM or RP from 64-Bit to 24/31-Bit Mode)
1 1 11 1
All Zeros
A
Branch Address
F2 (BASSM or RP from 24/31-Bit to 64-Bit Mode)
1 1 11 11
All Zeros
F3 (BASSM or RP from 24/31-Bit to 64-Bit Mode)
1 1 1 1111
All Zeros
Program Call
PSW

1
1Key
PC Number
ABits 33-62 of Return AddressP
F2 (in 64-Bit Mode)
PSW
1 1 Key
PC Number
Bits 32-62 of Return Address P
8 12
32
63
64
95
38
Program Return
F1 (in 24/31-Bit to 24/31-Bit Mode)
PSW

11 1 Key
New PASN
ABits 33-63 of Updated Inst. Adr.
F2 (in 64-Bit to 24/31-Bit Mode)
PSW

11 1 Key 1 New PASN
F3 (in 64-Bit to 24/31-Bit Mode)
PSW

11 11Key 11 New PASN
Updated Instruction Address
F4 (in 24/31-Bit to 64-Bit Mode)
PSW

11 1 Key 1 New PASN
ABits 33-63 of Updated Inst. Adr.
F5 (in 64-Bit to 64-Bit Mode)
PSW

11 1 Key 1 1 New PASN
PSW

11 11Key 1 11 New PASN
Updated Instruction Address
F7 (in 24/31-Bit to 64-Bit Mode)
PSW

Bits 32-62 of Return Address PA Updated Instruction Address
PSW

Bits 32-62 of Return Address PBits 32-63 of Updated Inst. Adr.
8 12
32
63
64
96
127
39
Program Return (Cont'd)

PSW
11 1 Key 1111 New PASN

Bits 32-62 of Return Address PBits -31 of Updated Inst. Adr.
Program Transfer
PSW
11 1Key
New PASN
Bits 32-63 of R% Before
F2 (in 64-Bit Mode)
PSW
11 1Key 1 New PASN
F3 (in 64-Bit Mode)
PSW
11 1 Key 11 New PASN
Bits -31 of R% Before
Set Secondary ASN

F1
New SASN
Trace
F1 (TRACE)
111 N
TOD-Clock Bits 16-63
TRACE Operand
(R$) - (R,)
/
F2 (TRACG)
111 N 1
TOD-Clock Bits -47
TOD-Clock Bits 48-79
TRACE Operand
(R$) - (R,)
/
8 12
32
63
64
96
127
128
159
Bit
4-7
40
Meaning
(N) One less than the number of registers in the trace entry.
Machine-Check Interruption Code

At real-storage locations 232-239 (E8-EF hex)
S P S C E V D C S C V S S K D W M P IF E F G C S
D D R D D F GW P P K S B E C E S P S M AA C P R R T
4
8
13
16
24 26
31
I A D
XA C C
E R A
FP T C
32
35
4
43
46 48
63
Bit
0
1
2
4
5
6
7
8
9
10
11
13
14
16
17
18
19
20
21
22
23
24
26
27
28
29
31
32
33
34
43
44
46
47
Meaning
(SD) System damage
(PD) Instruction-processing damage
(SR) System recovery
(CD) Timing-facility damage
(ED) External damage
(VF) Vector-facility failure
(DG) Degradation
(W) Warning
(CP) Channel report pending
(SP) Service-processor damage
(CK) Channel-subsystem damage
(VS) Vector-facility source
(B) Backed up
(SE) Storage error uncorrected
(SC) Storage error corrected
(KE) Storage-key error uncorrected
(DS) Storage degradation
(WP) PSW-MWP validity
(MS) PSW mask and key validity
(PM) PSW program-mask and condition-code validity
(IA) PSW-instruction-address validity
(FA) Failing-storage-address validity
(EC) External-damage-code validity
(FP) Floating-point-register validity
(GR) General-register validity
(CR) Control-register validity
(ST) Storage logical validity
(IE) Indirect storage error
(AR) Access-register validity
(DA) Delayed-access exception
(XF) Extended-floating-point-register validity
(AP) Ancillary report
(CT) CPU-timer validity
(CC) Clock-comparator validity
External-Damage Code
At real-storage address 244-247 (F4-F7 hex)
X X
N F
8 1
16
24
31
Bit
8
9
Meaning
(XN) Expanded storage not operational
(XF) Expanded-storage control failure
41
Operation-Request Block (ORB)

Word
Interruption Parameter
1Key SCMYFPIAU HT
LPM
L
X
2
Channel-Program Address
3CSS Priority Reserved

CU Priority Reserved
4
Reserved
5
Reserved
6
Reserved
7
Reserved
8
16
24
31
Word.Bit
1.0-3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
1.14
1.15
1.16-23
1.24
1.31
3.0-7
3.16-23
Meaning
(Key) Subchannel key
(S) Suspend control
(C) Streaming-mode control
(M) Modification control
(Y) Synchronization control
(F) CCW-format control
(P) Prefetch control
(I) Initial-status-interruption control
(A) Address-limit-checking control
(U) Suppress-suspended-interruption control
(H) Format-2-IDAW control
(T) 2K-IDAW control
(LPM) Logical-path mask
(L) Incorrect-length-suppression mode
(X) ORB-extension control
Control-unit priority
Channel-subsystem priority
Channel-Command Word (CCW)

Format-0 CCW
Command Code
Data Address
8
31
Flags
Byte Count
32
4
48
63
Bit
32
33
34
35
36
37
38
42
Meaning
(CD) Causes use of data-address portion of next CCW
(CC) Causes use of command code and data address of next
CCW
(SLI) Causes suppression of possible incorrect-length indication
(Skip) Suppresses transfer of information to main storage
(PCI) Causes an intermediate-interruption condition to occur
(IDA) Causes bits 8-31 of CCW to specify location of first IDAW
(Suspend) Causes suspension before execution of this CCW
Channel-Command Word (CCW) (Cont'd)
Format-1 CCW
Command Code Flags

Byte Count
8
16
31

Data Address
32
63
Bit
8
9
10
11
12
13
14
Meaning
(CD) Causes use of data-address portion of next CCW
(CC) Causes use of command code and data address of next
CCW
(SLI) Causes suppression of possible incorrect-length indication
(Skip) Suppresses transfer of information to main storage
(PCI) Causes an intermediate-interruption condition to occur
(IDA) Causes bits 8-31 of CCW to specify location of first IDAW
(Suspend) Causes suspension before execution of this CCW
Indirect-Data-Address Word (IDAW)

Format-1 IDAW

Data Address
1
31
Format-2 IDAW
Bits -31 of Data Address
31
Bits 32-63 of Data Address
32
63
43
Subchannel-Information Block (SCHIB)

Word
3
Path-Management-Control Word
8
Subchannel-Status Word`
11
Model-Dependent Area
12
*See Subchannel-Status Word (SCSW) on page 45.
Path-Management-Control Word (PMCW)
Interruption Parameter
1 ISC
ELMMMDTV
Device Number
2
LPM
PNOM
LPUM
PIM
3
MBI
POM
PAM
4
CHPID CHPID-1
CHPID-2 CHPID-3
5
CHPID-4 CHPID-5
CHPID-6 CHPID-7
8
16
24
31
Word.Bit
1.2-4
1.8
1.9-10
1.11-12
1.13
1.14
1.15
2.0-7
2.8-15
2.16-23
2.24-31
3.0-15
3.16-23
3.24-31
4.0-7
6.31
44
Meaning
(ISC) Interruption-subclass code
(E) Subchannel enabled
(LM) limit mode
00 No Checking
01 Data address must be limit
10 Data address must be < limit
11 Reserved
(MM) Measurement-mode enable
00 Neither mode enabled
01 Device-connect-time-measurement enabled
10 Measurement-block-update enabled
11 Both modes enabled
(D) Multipath mode
(T) Timing facility available
(V) Device number valid
(LPM) Logical-path mask
(PNOM) Path-not-operational mask
(LPUM) Last-path-used mask
(PIM) Path-installed mask
(MBI) Measurement-block index
(POM) Path-operational mask
(PAM) Path-available mask
(CHPID-0) Channel-path ID for logical path 0 (typical)
(S) Concurrent sense
Interruption-Response Block (IRB)

Word
1
Subchannel-Status Word
5
Extended-Status Word
/
Extended-Control Word
15
Subchannel-Status Word (SCSW)

Subchannel Control
Key SLCCFPIAUZENOFC
AC
SC
4 5 6 8
13
17 2
27
31
1
CCW Address
2Device StatusSubchan Status

Byte Count
8
16
31
Word.
Bit
0.0-3
0.4
0.5
0.6-7
0.8
0.9
0.10
0.11
0.12
0.13
0.14
0.15
0.17-19
0.20-26
0.27-31
2.0-15
Meaning
(Key) Subchannel key
(S) Suspend control
(L) Extended-status-word format (logout stored)
CC) Deferred condition code
00 Normal I/O interruption
01 Status in SCSW
10 Reserved
11 Path not operational
(F) CCW-format control
(P) Prefetch control
(I) Initial-status-interruption control
(A) Address-limit-checking control
(U) Suppress-suspended-interruption control
(Z) Zero condition code
(E) Extended control (information stored in ECW of IRB)
(N) Path not operational (PNOM nonzero)
(FC) Function control
17 (40) start, 18 (20) halt, 19 (10) clear
(AC) Activity control
20 (08) resume pending
24 (80) subchannel active
21 (04) start pending
25 (40) device active
22 (02) halt pending
26 (20) suspended
23 (01) clear pending
(SC) Status control
27 (10) alert
30 (02) secondary
28 (08) intermediate
31 (01) status pending
29 (04) primary
Device status (0-7), subchannel status (8-15)
0 (80) Attention
8 (80) Prog.-cont. int.
1 (40) Status modifier
9 (40) Incorrect length
2 (20) Control-unit end
10 (20) Program check
3 (10) Busy
11 (10) Protection check
4 (08) Channel end
12 (08) Channel-data check
5 (04) Device end
13 (04) Channel-control check
6 (02) Unit check
14 (02) Interface-control check
7 (01) Unit exception
15 (01) Chaining check
45
Interruption-Response Block (IRB) (Cont'd)
Extended-Status Word (ESW)

See chart on page 47 to determine the appropriate ESW
format.
Format-0 ESW
Word
Subchannel Logout
1
Extended-Report Word
Failing-Storage Address
4
Secondary-CCW Address
Format-0 ESW Word 0 (Subchannel Logout)
ESF
LPUM
FVF SATCDEASC
1
8
16
22 24 26 28 31
Bit
1-7
8-15
17-21
22-23
24-25
26
27
28
29-31
Meaning
(ESF) Extended-status flags (1 key check, 2 measurement-block
program check, 3 measurement-block data check, 4 measurement
-block protection check, 5 CCW check, 6 IDAW check, 7:0)
(FVF) Field-validity flags (17 LPUM, 18 TC, 19 SC, 20 device
status, 21 CCW address)
(SA) Storage-access code (00 access type unknown, 01 read, 10
write, 11 read backward)
(TC) Termination code (00 halt signal issued, 01 stop, stack, or
normal termination, 10 clear signal issued)
(D) Device status check
(E) Secondary error
(A) I/O-error alert
(SC) Sequence code
Format-0 ESW Word 1 (Extended-Report Word)
APTFSCR SCNT
3
8 1
16
31
Bit
3
4
5
6
7
8
9
10-15
Meaning
(A) Authorization check
(P) Path-verification-required
(T) Channel-path timeout
(F) Failing-storage-address validity
(S) Concurrent sense
(C) Secondary-CCW-address validity
(R) Failing-storage-address format (zero: 1-31 of word 2; one:
words 2 and 3)
(SCNT) Concurrent-sense count
Format-1 ESW Word 0*
LPUM
8
16
31
Bit
8-15
Meaning
*Word 1 is the same as word 1 of a format-0 ESW. Words 2, 3, and 4

are zeros.
46
LPUM
DCTI
8
16
31
Bit
8-15
16-31
Meaning
(DCTI) Device-connect-time interval
LPUM
Unpredictable
8
16
31
Bit
8-15
Meaning
Information Stored in ESW

Subchannel Conditions under which ESW
Is Stored by Test Subchannel Instruction
SubchannelPath-ManagementStatus Word
Control Word
DeviceConnectTime
StatusMeasurControl
SusmentField
pen- TimingModeL
ded
Facility
Enable
AIPSX
Bit
Bit
Bit
Bit
----0
*
*
*
DeviceConnectTime
MeasurmentMode
Active
No/Yes
**001
**1*1
10011
1
1
1
*
*
*
*
*
*
*
*
*
No/Yes
No/Yes
No/Yes
0
0
0
RRRR
RRRR
RRRR
00001
00011
100*1
0
0
0
*
*
*
*
*
*
*
*
*
No/Yes
No/Yes
No/Yes
U
3
3
****
ZM**
ZM**
**1*1
**1*1
**1*1
**1*1
0
0
0
0
*
*
*
*
0
1
1
1
*
0
1
1
No/Yes
No/Yes
No
Yes
1
1
1
2
ZMZZ
ZMZZ
ZMZZ
ZMDD
01001
01001
01001
01001
01001
0
0
0
0
0
0
1
1
1
1
*
0
1
1
1
*
*
0
1
1
No/Yes
No/Yes
No/Yes
No
Yes
U
1
1
1
2
****
ZMZZ
ZMZZ
ZMZZ
ZMDD
00011
11001
*1011
1
0
*
Bit
*
A
D
I
L
M
P
R
S
U
X
Z
ExtendedStatus
Word (ESW)
Format
U
Contents
Word 0
Byte
0123
****
These combinations do not occur.
Meaning
Not meaningful.
Bits may be zeros or ones.
Alert status.
Accumulated device-connect-time-interval (DCTI) value stored in
bytes 2 and 3.
Intermediate status.
Extended-status-word format.
Last-path-used mask (LPUM) stored in byte 1.
Primary status.
Subchannel-logout information stored in bytes 0-3.
Secondary status.
No format defined.
Status pending.
Bits are stored as zeros.
*Word 1 is the same as word 1 of a format-0 ESW. Words 2, 3, and 4

are zeros.
47
Extended-Control Word (ECW)

SCSW
Bits
5 14
0 0
0 1
ERW
Bit
7
0
1
1 0
1 1
1 1
0
0
1
ERW
Bits
10-15
Zeros
No. of con-sen*
bytes
Zeros
Zeros
No. of con-sen
bytes
ECW
Words 0-7
Unpredictable
Concurrent-sense information*
Unpredictable
Model-dependent information
Concurrent-sense information
*The contents of the ECW are specified by bits 5 and 14 of word

0 of the SCSW. The combination of SCSW bit 5 zero, SCSW bit
14 one, and ERW bit 7 zero does not occur.
Measurement Block
Word
SSCH + RSCH Count
Sample Count
1
Device-Connect Time
2
Function-Pending Time
3
Device-Disconnect Time
4
Control-Unit-Queuing Time
5
Device-Active-Only Time
Reserved
16
31
Channel-Report Word (CRW)
SRCRSC A ERC Reporting-Source ID
4
8 1
16
31
Bit
1
2
3
4-7
8
10-15
16-31
Meaning
(S) Solicited CRW
(R) Overflow (one or more CRWs lost)
(C) Chaining (meaningless if bit 2 is one)
(RSC) Reporting-source code (see Reporting-Source table)
(A) Ancillary report
(ERC) Error-recovery code (see Error-Recovery-Code table)
Reporting-source ID (see Reporting-Source table)
Error-Recovery Codes
ERC
000001
000010
000011
000100
000101
000110
000111
001000
48
Condition
Available
Initialized
Temporary error
Installed parameters initialized
Terminal
Permanent error with facility not initialized
Permanent error with facility initialized
Installed parameters modified
Channel-Report Word (CRW) (Cont'd)
Reporting Source
The reporting-source-ID format depends on the RSC field of
the channel-report word, as follows:
RSC
0010
0011
0100
1001
1011
Reporting Source
Monitoring facility
Subchannel
Channel path
Configuration-alert facility
Channel subsystem
Reporting-Source ID
00000000
00000000
XXXXXXXX
XXXXXXXX
00000000
YYYYYYYY
00000000
YYYYYYYY
00000000
00000000
X = Subchannel number
Y = Channel-path ID (CHPID)
I/O Command Codes

Standard Command-Code Assignments (CCW
Bits 0-7)
xxxx
Invalid Command mmmm 1 Sense
mmmm mm 1 Write
1 --Basic Sense
mmmm mm1 Read
111 1 --Sense ID
1 --Read Ipl
xxxx 1
Transfer in Channel (a)
mmmm mm11 Control
1
Transfer in Channel (b)
11 --Control No mmmm 1
Invalid Command
(c)
operation
mmmm 11 Read Backward
x -- Bit Ignored
m -- Modifier bit for specific
type of I/O device
a Format- CCW
b Format-1 CCW
c Format-1 CCW
and nonzero m bit
Standard Meanings of Bits of First Sense Byte
Bit Designation
Bit
Designation
Command reject
4
Data check
1
Intervention required
5
Overrun
2
Bus-out check
6
(Device dependent)
3
Equipment check
7
(Device dependent)
49
Code Assignments
Code Table
AS- ISO (1)

BookMaster
DecHex
EBCDIC
CII -8 IBM-PCSymbol Names(2)
NUL
NUL NUL NUL
1 1
SOH
SOH SOH SOH d face
2 2
STX
STX STX STX e FACE
3 3
ETX
ETX ETX ETX HEART
4 4
SEL
EOT EOT EOT DIAMOND
5 5
HT
ENQ ENQ ENQ CLUB
6 6
RNL
ACK ACK ACK SPADE
7 7
DEL
BEL BEL BEL j bullet
8 8
GE
BS BS BS k revbul
9 9
SPS
HT HT HT l circle
1 A
RPT
LF LF LF m revcir
11 B
VT
VT VT VT male
12 C
FF
FF FF FF female
13 D
CR
CR CR CR note18
14 E
SO
SO SO SO note1616
15 F
SI
SI SI SI r sun
161
DLE
DLE DLE DLE M rahead
1711
DC1
DC1 DC1 DC1 L lahead
1812
DC2
DC2 DC2 DC2 s udarrow
1913
DC3
DC3 DC3 DC3 dblxclam
2 14
RES/ENP
DC4 DC4 DC4 par
2115
NL
NAK NAK NAK section
2216
BS
SYN SYN SYN overline
2317
POC
ETB ETB ETB x udarrowus
2418
CAN
CAN CAN CAN uarrow
2519
EM
EM EM EM darrow
261A
UBS
SUB SUB IFS rarrow
271B
CU1
ESC ESC ESC larrow
281C
IFS
FS IFS DEL } lnotusd
291D
IGS
GS IGS GS lrarrow
3 1E
IRS
RS IRS RS uahead
311F
ITB/IUS
US IUS US dahead
322
DS
SP SP
SP
3321
SOS
!
!
! xclam
3422
FS
"
"
" sdq
3523
WUS
#
#
# numsign
3624
BYP/INP
$
$
$ dollar
3725
LF
%
%
% percent
3826
ETB
&
&
& amp
3927
ESC
'
'
' ssq(3)
BookMaster is a trademark of the International Business

Machines Corporation.
50
Code Assignments (Cont'd)
AS- ISO (1)

BookMaster
DecHex
EBCDIC
CII -8 IBM-PCSymbol Names(2)
4 28
SA
(
(
( lpar
4129
SFE
)
)
) rpar
422A
SM/SW
`
`
` asterisk
432B
CSP
+
+
+ plus
442C
MFA
,
,
, comma
452D
ENQ

hyphen or minus
462E
ACK
.
.
. period
472F
BEL
/
/
/ divslash or slash
483
4931
1
1
1
5 32
SYN
2
2
2
5133
IR
3
3
3
5234
PP
4
4
4
5335
TRN
5
5
5
5436
NBS
6
6
6
5537
EOT
7
7
7
5638
SBS
8
8
8
5739
IT
9
9
9
583A
RFF
:
:
: colon
593B
CU3
;
;
; semi
6 3C
DC4
<
<
< lt
613D
NAK

eq
623E
>
>
> gt
633F
SUB
?
?
? quest
DecHex
See Next Page
See Above See Above
644 SP SP SP SP SP @
@
@ atsign
6541 RSP RSP RSP RSP RSP A
A
A
6642
B
B
B ac
6743
C
C
C ae
6844
D
D
D ag
6945
E
E
E aa
7 46
F
F
F at
7147
G
G
G ao
7248
H
H
H cc
7349
I
I
I nt
744A
[
J
J
J cent, lbrk
754B . .
.
.
. K
K
K period
764C < <

<
<
< L
L
L lt
774D ( (
(
(
( M
M
M lpar
784E + +
+
+
+ N
N
N plus
794F
|
|
!
| O
O
O vbar, xclam
8 5 &
&
&
&
& P
P
P amp
8151
Q
Q
Q ea
8252
R
R
R ec
8353
S
S
S ee
51
EBCDIC(4)
AS- ISO IBMBookMaster
DecHex81C 94C '37 5'' 1'47CII -8 -PCSymbol Names(2)
8454
T
T
T eg
8555
U
U
U ia
8656
V
V
V ic
8757
W
W
W ie
8858
X
X
X ig
8959
Y
Y
Y ss
9 5A
!
!
]
! Z
Z
Z xclam, rbrk
915B
$
$
$
$ [
[
[ dollar, lbrk
925C ` `
`
`
` \
\
\ asterisk, bslash
935D ) )
)
)
) ]
]
] rpar, rbrk
945E ; ;
;
;
; ^
^
^ semi, hat
955F
^
^ _
_
_ lnot, hat, us
966 - - `
`
` hyphen or minus,
grave
9761 / /
/
/
/ a
a
a divslash or slash
9862
b
b
b Ac
9963
c
c
c Ae
1 64
d
d
d Ag
1 165
e
e
e Aa
1 266
f
f
f At
1 367
g
g
g Ao
1 468
h
h
h Cc
1 569
i
i
i Nt
1 66A
j
j
j splitvbar
1 76B , ,
,
,
, k
k
k comma
1 86C % %
%
%
% l
l
l percent
1 96D _ _
_
_
_ m
m
m us
11 6E > >
>
>
> n
n
n gt
1116F ? ?
?
?
? o
o
o quest
1127
p
p
p os
11371
q
q
q Ea
11472
r
r
r Ec
11573
s
s
s Ee
11674
t
t
t Eg
11775
u
u
u Ia
11876
v
v
v Ic
11977
w
w
w Ie
12 78
x
x
x Ig
12179
`
`
` y
y
y grave
1227A : :
:
:
: z
z
z colon
1237B
#
#
#
# {
{
{ numsign, lbrc
1247C
@
@
@
@ |
|
| atsign, vbar
1257D ' '
'
'
' }
}
} ssq(3), rbrc
1267E
eq, eqv
1277F " "
"
"
" DEL
sdq, house
52
EBCDIC(4)
ISO IBM-PC BookMaster
DecHex81C 94C '37 5'' 1'47-8 437 85'Symbol Names(2)
1288
Os, Cc
12981 a a
a
a
a
ue
13 82 b b
b
b
b BPH
ea
13183 c
c
c
c
c NBH
ac
13284 d
d
d
d
d IND
ae
13385 e
e
e
e
e NEL
ag
13486 f
f
f
f
f SSA
ao
13587 g
g
g
g
g ESA
cc
13688 h
h
h
h
h HTS
ec
13789 i
i
i
i
i HTJ
ee
1388A
VTS
odqf, eg
1398B
PLD
cdqf, ee
14 8C
PLU
eth, ic
1418D
RI
ya, ig
1428E
SS2
thorn, Ae
1438F
SS3
pm, Ao
1449
DCS
degree, Ea
14591 j
j
j
j
j PU1
aelig
14692 k
k
k
k
k PU2
AElig
14793 l
l
l
l
l STS
oc
14894 m
m
m
m
m CCH
oe
14995 n
n
n
n
n MW
og
15 96 o
o
o
o
o SPA
uc
15197 p
p
p
p
p EPA
ug
15298 q
q
q
q
q SOS
ye
15399 r
r
r
r
r
Oe
1549A
SCI
aus, Ue
1559B
CSI
ous, cent, os
1569C
ST
aelig, Lsterling
1579D
OSC
cedilla, yen, Os
1589E
PM
AElig, peseta, mult
1599F
ACP
currency, fnof(5)
16 A
RSP
mu(6), aa
161A1
tilde, inve, ia
162A2 s s
s
s
s
cent, oa
163A3 t t
t
t
t
Lsterling, ua
164A4 u u
u
u
u
currency, nt
165A5 v v
v
v
v
yen, Nt
166A6 w w
w
w
w
splitvbar, aus
167A7 x x
x
x
x
section, ous
168A8 y y
y
y
y
umlaut, invq
169A9 z z
z
z
z
copyr, lnotrev, regtm

17 AA
inve, aus, lnot

171AB
invq, odqf, frac12
53
EBCDIC(4)
172AC
Dstroke or Eth, lnot,
frac14
173AD
[ SHY
|Ya, lbrk, inve
174AE
Thorn, regtm, odqf

175AF
regtm, overline, cdqf
176B
^
hat, cent, lnot,
degree, box14
177B1
Lsterling, pm, box12

178B2
yen, sup2, box34

179B3
smultdot, sup3, bxv
18 B4
copyr, acute, bxrj

181B5
section, mu(6),
bx1 12, Aa
182B6
par, bx2 21, Ac

183B7
frac14, smultdot,
bx 21, Ag
184B8
frac12, cedilla,
bx 12, copyr
185B9
frac34, sup1, bx2 22

186BA
[
lbrk, lnot, Ya, ous,
bx2 2
187BB
]
|

rbrk, vbar, umlaut,
cdqf, bx 22
188BC
overline, frac14,
bx2 2
189BD
umlaut, rbrk, frac12,
bx2 1, cent
19 BE
acute, frac34,
bx1 2, yen
191BF
mult, invq, bxur
192C
{
{
{
lbrc, Ag, bxll

193C1 A A
A
A
A
Aa, bxbj
194C2 B B
B
B
B
Ac, bxtj
195C3 C C
C
C
C
At, bxlj
196C4 D D
D
D
D
Ae, bxh
197C5 E E
E
E
E
Ao, bxcj
198C6 F F
F
F
F
AElig, bx121 , at
199C7 G G
G
G
G
Cc, bx212 , At
2 C8 H H
H
H
H
Eg, bx22 , Ag
2 1C9 I I
I
I
I
Ea, bx 22
2 2CA SHY SHY SHY SHY SHY
Ec, bx22 2
2 3CB
oc, Ee, bx 222
2 4CC
oe, Ig, bx222

2 5CD
og, Ia, bx 2 2
2 6CE
oa, Ic, bx2222

2 7CF
ot, Ie, bx12 2,
currency
54
EBCDIC(4)
2 8D
}
}
}
rbrc, Dstroke or Eth,
bx21 1, eth
2 9D1 J J
J
J
J
Nt, bx 212, Dstroke
or Eth
21 D2 K K
K
K
K
Og, bx 121, Ec
211D3 L L
L
L
L
Oa, bx21 , Ee
212D4 M M
M
M
M
Oc, bx12 , Eg
213D5 N N
N
N
N
Ot, bx 21 , idotless
214D6 O O
O
O
O
Oe, bx 12 , Ia
215D7 P P
P
P
P
mult, bx2121, Ic
216D8 Q Q
Q
Q
Q
Os, bx1212, Ie
217D9 R R
R
R
R
Ug, bxlr
218DA
sup1, Ua, bxul

219DB

m
m uc, Uc, BOX
22 DC

ue, Ue, BOXBOT
221DD

ug, Ya, BOXLEFT,
splitvbar
222DE

ua, thorn, BOXRIGHT,
Ig
223DF

ye, ss, BOXTOP
224E
\
\
\
bslash, ag, alpha, Oa

225E1
NSP
div, aa, ss
226E2 S S
S
S
S
ac, Gamma, Oc
227E3 T T
T
T
T
at, pi, Og
228E4 U U
U
U
U
ae, Sigma, ot
229E5 V V
V
V
V
ao, sigma, Ot
23 E6 W W
W
W
W
aelig, mu(6)
231E7 X X
X
X
X
cc, tau, thorn
232E8 Y Y
Y
Y
Y
eg, Phi, Thorn

233E9 Z Z
Z
Z
Z
ea, Theta(5), Ua
234EA
V
V
V
sup2, ec, Omega, Uc

235EB
Oc, ee, delta, Ug
236EC
Oe, ig, infinity, ya

237ED
Og, ia, phi, Ya

238EE
Oa, ic, epsilon,
overline
239EF
Ot, ie, intersect,
acute
24 F

SHYeth, identical
241F1 1 1
1
1
1
nt, pm
242F2 2 2
2
2
2
og, ge, eq
243F3 3 3
3
3
3
oa, le, frac34
244F4 4 4
4
4
4
*
oc, inttop, par
245F5 5 5
5
5
5
+
ot, intbot, section
246F6 6 6
6
6
6
oe, div
247F7 7 7
7
7
7
div, nearly(5),
cedilla
55
EBCDIC(4)
248F8 8 8
8
8
8
os, degree
249F9 9 9
9
9
9
j
ug, lmultdot, umlaut
25 FA
U
U
U
sup3, ua, smultdot

251FB
Uc, uc, sqrt, sup1
252FC

U Ue, ue, supn, sup3
253FD

V
V Ug, ya, sup2
254FE
Ua, thorn, sqbul

255FF EO EO EO EO EO RSP RSPye
(1) The ASCII controls and graphics are from ANSI X3.4. The ISO-8 controls are from ISO 6429, and the graphics are from ISO 8859-1. The
ISO-8 graphics are code page 00819, named ISO/ANSI Multilingual.
IBM-PC controls and graphics are shown. The graphics are common
to code page 00437, named Personal Computer, and code page
00850, named Personal Computer - Multilingual Page. Code pages
00437 and 00850 are shown separately beginning at X'80', after
which they diverge in content.
(2) The symbol names shown are to be preceded by an ampersand (&)
and followed by a period (.) to form a symbol. Source: SC34-5009.
(3) ASCII, ISO-8, and IBM-PC X'27' and EBCDIC X'7D' are an apostrophe having the appearance of a straight single quote. The
BookMaster apos produces a character having the appearance of an
accent acute.
(4) Five columns of EBCDIC graphics are shown. The first is the
81-character character set 0640, called the syntactic character set, that
is mapped the same on all EBCDIC code pages. The second is the
standard IBM 94-character character set mapped on code page 00037.
The third is code page 00037, named USA/Canada - CECP (Country
Extended Code Page). The fourth is code page 00500, named International #5. The fifth is code page 01047, named Latin 1/Open
Systems. Code pages 00037, 00500, 01047, and 00819 (ISO-8) all
map the 189-character character set 0697. Source: SE09-8002.
(5) , , and are of nonstandard width.
(6) EBCDIC X'A0' and ISO-8 X'B5' are micro but resemble mu. The
BookMaster usec produces a character of nonstandard width.
Control Character Representations

ACK
BEL
BS
BYP
CAN
CR
CSP
CU1
CU3
DC1
DC2
DC3
DC4
DEL
DLE
DS
EM
ENP
ENQ
EO
EOT
ESC
ETB
ETX
FF
FS
GE
HT
IFS
IGS
INP
IR
IRS
56
Acknowledge
Bell
Backspace
Bypass
Cancel
Carriage Return
Control Sequence Prefix
Customer Use 1
Customer Use 3
Device Control 1
Device Control 2
Device Control 3
Device Control 4
Delete
Data Link Escape
Digit Select
End of Medium
Enable Presentation
Enquiry
Eight Ones
End of Transmission
Escape
End of Transmission Block
End of Text
Form Feed
Field Separator
Graphic Escape
Horizontal Tab
Interchange File Separator
Interchange Group Separator
Inhibit Presentation
Index Return
Interchange Record Separator
IT
ITB
IUS
LF
MFA
NAK
NBS
NL
NUL
POC
PP
RES
RFF
RNL
RPT
SA
SBS
SEL
SFE
SI
SM
SO
SOH
SOS
SPS
STX
SUB
SW
SYN
TRN
UBS
VT
WUS
Indent Tab
Intermediate Transmission Block
International Unit Separator
Line Feed
Modify Field Attribute
Negative Acknowledge
Numeric Backspace
New Line
Null
Program-Operator Communication
Presentation Position
Restore
Required Form Feed
Required New Line
Repeat
Set Attribute
Subscript
Select
Start Field Extended
Shift In
Set Mode
Shift Out
Start of Heading
Start of Significance
Superscript
Start of Text
Substitute
Switch
Synchronous Idle
Transparent
Unit Backspace
Vertical Tab
Word Underscore
Additional ISO-8 Control Character

Representations
APC
BPH
CCH
CSI
DCS
EPA
ESA
HTJ
HTS
IFS
IGS
IND
IRS
MW
NBH
NEL
Application Program Command

Break Permitted Here
Cancel Character
Control Sequence Introducer
Device Control String
End of Guarded Area
End of Selected Area
Character Tabulation with
Justification
Character Tabulation Set
Information Separator Four
Information Separator Three
Index
Information Separator Two
Message Waiting
No Break Here
Next Line
OSC
PLD
PLU
PM
PU1
PU2
RI
SCI
SOS
SPA
SSA
SS2
SS3
ST
STS
US
VTS
Operating System Command

Partial Line Down
Partial Line Up
Privacy Message
Private Use One
Private Use Two
Reverse Line Feed (or Index)
Single Character Introducer
Start of String
Start of Guarded Area
Start of Selected Area
Single Shift Two
Single Shift Three
String Terminator
Set Transmit State
Information Separator One
Line Tabulation Set
Formatting Character Representations

NSP
RSP
Numeric Space
Required Space
SP
SHY
Space
Syllable Hyphen
Two-Character BSC Data Link Controls

Function
ACK-0
ACK-1
WACK
RVI
EBCDIC
DLE,X'70'
DLE,X'61'
DLE,X'68'
DLE,X'7C'
ASCII
DLE,0
DLE,1
DLE,;
DLE,<
Commonly Used Editing Pattern Characters

Code
(Hex)
20
21
22
40
4B
Meaning
Digit selector
Start of significance
Field separator
Blank
Period
Code
(Hex)
5B
5C
6B
C3D9
C4C2
Meaning
Dollar sign
Asterisk
Comma
CR (credit)
DB (debit)
ANSI-Defined Printer Control Characters

(A in RECFM field of DCB)
Code
blank
0
+
1
Action before Printing Record

Space 1 line
Space 2 lines
Space 3 lines
Suppress space
Skip to line 1 on new page
Hexadecimal and Decimal Conversion

From hex: locate each hex digit in its corresponding column
position and note the decimal equivalents. Add these to
obtain the decimal value.
From decimal: (1) locate the largest decimal value in the
table that will fit into the decimal number to be converted, and
(2) note its hex equivalent and hex column position. (3) Find
the decimal remainder. Repeat the process on this and subsequent remainders.
Note: Hexadecimal equivalents of all numbers from 0 to 255
are listed in the code tables.
57
Bits:
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
58
0
268,435,456
536,870,912
805,306,368
1,073,741,824
1,342,177,280
1,610,612,736
1,879,048,192
2,147,483,648
2,415,919,104
2,684,354,560
2,952,790,016
3,221,225,472
3,489,660,928
3,758,096,384
4,026,531,840
8
0123
Dec
Byte
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
16,777,216
33,554,432
50,331,648
67,108,864
83,886,080
100,663,296
117,440,512
134,217,728
150,994,944
167,772,160
184,549,376
201,326,592
218,103,808
234,881,024
251,658,240
7
4567
Dec
Halfword
Hex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1,048,576
2,097,152
3,145,728
4,194,304
5,242,880
6,291,456
7,340,032
8,388,608
9,437,184
10,485,760
11,534,336
12,582,912
13,631,488
14,680,064
15,728,640
6
0123
Dec
Byte
4567
Hex
Dec
0
0
1
65,536
2
131,072
3
196,608
4
262,144
5
327,680
6
393,216
7
458,752
8
524,288
9
589,824
A
655,360
B
720,896
C
786,432
D
851,968
E
917,504
F
983,040
5
Word
0123
Hex
Dec
0
0
1
4,096
2
8,192
3
12,288
4
16,384
5
20,480
6
24,576
7
28,672
8
32,768
9
36,864
A
40,960
B
45,056
C
49,152
D
53,248
E
57,344
F
61,440
4
Byte
4567
Hex
Dec
0
0
1
256
2
512
3
768
4
1,024
5
1,280
6
1,536
7
1,792
8
2,048
9
2,304
A
2,560
B
2,816
C
3,072
D
3,328
E
3,584
F
3,840
3
Halfword
Byte
0123
4567
Hex
Dec
Hex
Dec
0
0
0
0
1
16
1
1
2
32
2
2
3
48
3
3
4
64
4
4
5
80
5
5
6
96
6
6
7
112
7
7
8
128
8
8
9
144
9
9
A
160
A
10
B
176
B
11
C
192
C
12
D
208
D
13
E
224
E
14
F
240
F
15
2
1
Hexadecimal and Decimal Conversion (Cont'd)
Powers of 2 and 16
m
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
n
0
10
11
12
13
14
15
16
2m and 16n
1
2
4
8
16
32
64
128
256
512
1 024
2 048
4 096
8 192
16 384
32 768
65 536
131 072
262 144
524 288
1 048 576
2 097 152
4 194 304
8 388 608
16 777 216
33 554 432
67 108 864
134 217 728
268 435 456
536 870 912
1 073 741 824
2 147 483 648
4 294 967 296
8 589 934 592
17 179 869 184
34 359 738 368
68 719 476 736
137 438 953 472
274 877 906 944
549 755 813 888
1 099 511 627 776
2 199 023 255 552
4 398 046 511 104
8 796 093 022 208
17 592 186 044 416
35 184 372 088 832
70 368 744 177 664
140 737 488 355 328
281 474 976 710 656
562 949 953 421 312
1 125 899 906 842 624
2 251 799 813 685 248
4 503 599 627 370 496
9 007 199 254 740 992
18 014 398 509 481 984
36 028 797 018 963 968
72 057 594 037 927 936
144 115 188 075 855 872
288 230 376 151 711 744
576 460 752 303 423 488
1 152 921 504 606 846 976
2 305 843 009 213 693 952
4 611 686 018 427 387 904
9 223 372 036 854 775 808
18 446 744 073 709 551 616
Symbol
K (kilo)
M (mega)
G (giga)
T (tera)
P (peta)
E (exa)
59
60
IBM
File Number: S390-00

Printed in the United States of America
on recycled paper containing 10%
recovered post-consumer fiber.
SA22-7871-

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z/Architecture

First Edition (September 2001)

For information about Enterprise Systems Architecture/390

IBM, z/Architecture, zSeries, Enterprise Systems Architecture/390, and

Copyright IBM Corp. 2001

z/Architecture Reference Summary

z/Architecture Reference Summary

Machine Instruction Formats

First Halfword Second Halfword Third Halfword

z/Architecture Reference Summary

Machine Instruction Formats (Cont'd)

First Halfword Second Halfword Third Halfword

RSL Op Code L$ //// B%

Machine Instruction Formats (Cont'd)

Denotes association with first, second, third, or fourth operand

Machine Instructions by Mnemonic

z/Architecture Reference Summary

Machine Instructions by Mnemonic (Cont'd)

Machine Instructions by Mnemonic (Cont'd)

z/Architecture Reference Summary

Machine Instructions by Mnemonic (Cont'd)

Machine Instructions by Mnemonic (Cont'd)

z/Architecture Reference Summary

Machine Instructions by Mnemonic (Cont'd)

Machine Instructions by Mnemonic (Cont'd)

z/Architecture Reference Summary

Machine Instructions by Mnemonic (Cont'd)

Machine Instructions by Operation Code

Machine Instructions by Operation Code (Cont'd)

z/Architecture Reference Summary

Machine Instructions by Operation Code (Cont'd)

Compare and Form

Compare and Swap

Add Logical with

Compare until Substring Equal

Load and Test

z/Architecture Reference Summary

Condition Codes (Cont'd)

Set Program Mask

Test under Mask

Test under Mask

Translate and Test

Zero and Add

Condition Codes (Cont'd)

Load and Test

Store System Information

z/Architecture Reference Summary

Condition Codes (Cont'd)

Operand of Store Clock

Time-of-Day (TOD) Clock

Note: Bit 51 of the TOD clock corresponds to one microsecond.

Operand of Store Clock Extended

Assembler Instructions (Cont'd)

Drop base address register

Start new page in macro definition

Provide data for SYSADATA file

Conditional assembly branch counter

z/Architecture Reference Summary

Extended-Mnemonic Instructions for Branch

Extended-Mnemonic Instructions for

Branch Relative and Save

Halfword Halfword Halfword Halfword

Byte Byte Byte Byte Byte Byte Byte Byte

Fixed Storage Locations