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Sequential Logic
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Copyright 2005 Noam Nisan and Shimon Schocken
This presentation contains lecture materials that accompany the textbook The Elements of
Computing Systems by Noam Nisan & Shimon Schocken, MIT Press, 2005.
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Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 1
All sequential chips can be based on one low-level sequential gate, called
data flip flop, or DFF
The complex clock-dependency details can be encapsulated at the lowlevel DFF level
All the higher-level sequential chips can be built on top of the DFF using
combinational logic only.
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 2
Lecture plan
Clock
A hierarchy of memory chips:
Flip-flop gates
Binary cells
Registers
RAM
Counters
Perspective.
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 3
The Clock
HW
simulator
demo
tock
tick
clock
signal
tick
cycle
tock
tock
tick
cycle
tock
tick
cycle
cycle
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 4
Flip-flop
HW
simulator
demo
in
DFF
out
out(t) = in(t-1)
in
sequential
chip
out
in
sequential
chip
out
(notation)
clock
signal
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 5
in
Bit
out
in
DFF
out
out(t) = in(t-1)
in
DFF
out
load
in
MUX
out
DFF
out(t) = out(t-1) ?
out(t) = in(t-1) ?
Wont work
if load(t-1) then out(t)=in(t-1)
else out(t)=out(t-1)
OK
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 6
Bit (cont.)
HW
simulator
demo
Interface
Implementation
load
load
Bit
out
in
MUX
in
DFF
out
Load bit
Read logic
Write logic
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 7
Multi-bit registers
HW
simulator
demo
load
load
in
out
Bit
1-bit register
in
Bit Bit
...
Bit
out
w-bit register
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 8
HW
simulator
demo
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 9
HW
simulator
demo
load
register 0
register 1
register 2
in
(word)
..
.
register n-1
out
(word)
RAM n
address
Direct Access Logic
(0 to n-1)
Read logic
Write logic.
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 10
RAM interface
load
in
out
16 bits
RAMn
address
16 bits
log 2 n
bits
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 11
RAM anatomy
RAM 64
RAM8
..
.
RAM 8
register
..
.
Register
Bit Bit
...
RAM8
register
Bit
register
...
Recursive ascent
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 12
Counter
Needed: a storage device that can:
(a) set its state to some base value
(b) increment the state in every clock cycle
(c) maintain its state (stop incrementing) over clock cycles
(d) reset its state
inc
in
load reset
out
PC (counter)
w bits
w bits
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 13
in
comb.
logic
out
Sequential chip
in
(optional)
time delay
(optional)
comb.
logic
DFF
gate(s)
comb.
logic
out
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 14
Time matters
tock
clock
signal
tick
tock
tock
tick
cycle
tick
cycle
tock
tick
cycle
cycle
During a tick-tock cycle, the internal states of all the clocked chips are allowed
to change, but their outputs are latched
At the beginning of the next cycle, the outputs of all the clocked chips in the
architecture commit to the new values.
Implications:
a
Reg1
out
Reg2
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 15
Perspective
All the memory units described in this lecture are standard
Typical memory hierarchy
SRAM (static),
DRAM (dynamic),
Disk
Access
time
Cost
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.idc.ac.il/tecs , Chapter 3: Sequential Logic
slide 16