Mysc02 401

0.
35um CMOS Reference Manual
MYSC02-401
Rev 8.0
MIMOS Authorized Recipient Only
Date: 17/01/2011
Page 1 of 72
0.35um CMOS Reference Manual

MYSC02-401
Revision 8.0
Revision Author
Department
Document Location
Approval Committee
Confidentiality Status
Archive Requirement
Nurafizah Saidin
Wafer Fab Design Library
Department Document Center
Author Immediate Superior
Not Applicable
MYSC02-401
Rev 8.0
Date: 17/01/2011
Page 2 of 72
Revision History
Rev No
1.0
2.0
3.0
4.0
Date
19/01/2006
Change History
Originator
First Issue
Wee Leong
Son
1. Change PO2 as polygate

2. Add PO and HRES rule
12/01/2006
09/08/2006
16/01/2007
Wee Leong
Son
Change CB rule
Wee Leong
Son
Add Elements rules for basics devices
Fairuz Niza
Abu Bakar
5.0
16/07/2007 Add diode definitions layers
Fairuz Niza
Abu Bakar
6.0
08/09/2008
Fairuz Niza
Abu Bakar
7.0
11/03/2009
o
o
8.0
17/01/2011
1.
New template
2.
3.
4.
MIMOS INTERNAL USE ONLY
New template MIMOS Wafer fab 2009

New reviews and approval records due to
organizational changes.
Updated on density check for PO2, Metal-1,
Metal-2 and Metal-3.
Added elements rules for RM1, RM2 and
RM3.
Added ESD Implantation rules, ESD layout
guidelines, ESD design rules for
NMOS/PMOS protection circuit, SDI rules,
gate width rules, Antenna effect prevention
rules, metal stress relief for M1, M2 and M3,
latch-up prevention rules, power line rules
and guidelines and seal rings.
Updated on PO2 figure.
Robiah Hussin
Nurafizah
Saidin
Page 2 of 72
MYSC02-401
Rev 8.0
Date: 17/01/2011
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Review and Approval Records

Name
Title
Nurafizah Saidin
Engineer
Document Originator
Department
Date
Signatory
Wafer Fab Design

Library
Document Review
Name
Title
Department
Muhamad Amri Ismail
Senior Engineer
Wafer Fab Design

Library
Nurafizah Saidin
Engineer
Wafer Fab Design

Library
Date
Signatory
Date
Signatory
Document Approval
Name
Title
Iskhandar Md Nasir
Senior Staff
Engineer
Department
Wafer Fab - Design
Library
Page 3 of 72
MYSC02-401
Rev 8.0
Date: 17/01/2011
Page 4 of 72
TABLE OF CONTENTS
PAGE
1. INTRODUCTION ..................................................................................................... 6
1.1
Confidential Proclamation......................................................................... 6
2. DESIGN RULES .................................................................................................. 7
2.1
Drawn Mask Layer ................................................................................... 7
2.1.1 Key Process Sequence ........................................................................ 7
2.2
Design Layer.. 8
2.3
Terminology ........................................................................................... 10
2.4
Definition of Layout Rules....................................................................... 11
2.5
Pitches ................................................................................................... 12
2.6
Design Rules Description ....................................................................... 13
2.6.1 NWELL Rules (192)............................................................................ 13
2.6.2 Active Area Rules (120).14
2.6.3 PO (POLY1) Rules (140) .................................................................... 16
2.6.4 HRES Rules (135) .............................................................................. 18
2.6.5 PO2 (POLY2) Rules (130) .................................................................. 19
2.6.6 P+ S/D Rules (197) ............................................................................ 21
2.6.7 N+S/D Rules (198) ............................................................................. 23
2.6.8 Contact Rules (156)............................................................................ 25
2.6.9 Metal-1 Rules (160) ............................................................................ 27
2.6.10
Via1 Rules (178) ............................................................................. 29
2.6.11
Metal-2 Rules (180) ........................................................................ 30
2.6.12
Via2 Rules (179) ............................................................................. 32
2.6.13
Metal-3 Rules (181) ........................................................................ 33
2.6.14
Passivation Rules (107) .................................................................. 35
3.
ESD GUIDELINES.. 37
4.
ESD DESIGN RULES FOR NMOS/PMOS PROTECTION CIRCUIT 38
5.
ESD IMPLANTATION RULES.. 40
6.
SDI RULES.. 42
7.
GATE WIDTH RULES 43
8.
ANTENNA EFFECT PREVENTION RULES.. 43
9. LATCH-UP PREVENTION RULES 45

10. METAL STRESS RELIEF.. 47
11.1 Metal Slot for Metal-1 47
11.2 Metal Slot for Metal-2 49
11.3 Metal Slot for Metal-3 .. 50
11. POWERLINE RULES AND GUIDELINES. 53
12. SEAL RINGS.55
13. ELEMENT RULES............................................................................................. 56
13.1 MOS ....................................................................................................... 56
13.1.1 PMOS................................................................................................. 56
13.1.2 NMOS ................................................................................................ 57
13.2 RESISTOR ............................................................................................. 58
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13.2.1 RES_NWELL...................................................................................... 58
13.2.2 RES_NDIFF ....................................................................................... 59
13.2.3 RES_PDIFF........................................................................................ 60
13.2.4 RPOLY1 ............................................................................................. 61
13.2.5 RPOLYH ............................................................................................ 62
13.2.6 RM1 63
13.2.7 RM264
13.2.8 RM365
13.3 CAPACITOR .......................................................................................... 66
13.3.1 CPOLY ............................................................................................... 66
13.3.2 NCAP ................................................................................................. 67
13.3.3 PCAP ................................................................................................. 68
13.4 DIODE.................................................................................................... 69
13.4.1 PDIO .................................................................................................. 69
13.4.2 NDIO .................................................................................................. 70
13.5 BIPOLAR ............................................................................................... 71
13.5.1 VPNP ................................................................................................. 71
14. SUPPORT ...72
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1.
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INTRODUCTION
This manual contains information on process parameters of 0.35um (Double Poly Triple Metal)
AMS CMOS process for 3.3V application. It is intended to be reference guide for users. The
information in this manual are intended for those who want to design and layout a circuit based on
MIMOS FAB2 0.35um AMS CMOS 3.3V process.
1.1 Confidential Proclamation

This design rules document contains MIMOS confidential information and is intended for MIMOS
authorized recipient only. No part of this document may be reproduced or transmitted in any form
or by any means without the prior written permission from MIMOS.
Page 6 of 72
2.
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Page 7 of 72
DESIGN RULES
2.1 Drawn Mask Layer

2.1.1
Key Process Sequence

Mask
Seq.
Mask
Code
Mask
ID
Digitized Pattern
Digitized
Area
(Dark/Clear)
120
OD
Thin Oxide
135
HRES
HRES
140
PO
Poly-1
191
PW
N-Well
192
NW
N-Well
130
PO2
Poly-2
198
NP
NLDD Implant
197
PP
PLDD Implant
198
NP
N+S/D Implant
10
197
PP
P+S/D Implant
11
156
CO
Contact
12
197
PP
P+ contact implant
13
160
M1
Metal-1
14
178
V1
Via-1
15
180
M2
Metal-2
16
179
V2
Via-2
17
181
M3
Metal-3
18
107
CB
Bonding Pads
CAD Bias
(um)
Process
Bias (um)
+0.025
-0.025
+0.05
-0.025
-0.025
Note:
i.
Total 15 masks with 18 masking steps.
ii. P-Well mask is the reverse tone of N-Well mask without bias.
iii. LDD mask is the same as S/D masks.
iv. Drawn layers
N-Well, OD, HRES, Poly-1, Poly-2, N+S/D, P+S/D,
Contact, Metal-1, Via-1, Metal-2,Via2, Metal-3, PADS
v. CAD bias = (Dimension on mask Dimension on layout design)/2
vi. Process bias = (Dimension on silicon Dimension on mask)/2
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2.2 Design Layer

Layer
No
Layer Abbr.
Layer Name
-------
Use prohibited
51
HTNW
Hot NWell definition layer
NWEL
N-well
OD
MOS active region
13
PO2
POLY2 for gate and capacitor top plate
14
PO
POLY1 for resistor and capacitor bottom plate
PP
Source/Drain region P+ implant
NP
Source/Drain region N+ implant
15
CO
Contact hole on diffusion and poly region
16
M1
1st layer metal
17
VIA1
Vias between 1st and 2nd layers metal
18
M2
2nd layer metal
27
VIA2
Vias between 2nd and 3rd layers metal
28
M3
3rd layer metal
29
HRES
High resistive layer
19
CB
Passivation hole opening
31
INH_M1
M1 prohibited region
32
INH_M2
33
INH_M3
40
SRES
Ndiff or Pdiff resistor definition layer
45
Frame
Cell outline
45:1
FRAME_LAB
Frame Cell Label
111
PSUB
Analog block definition area
55
CAP
Capacitor definition layer
56
CAPOLY
CPOLY definition layer
57
DIODID
Diode definition layer
60
RESDEF
Nwell or PO resistor definition layer
61
M1_LAB
Label on M1
62
M2_LAB
Label on M2
63
M3_LAB
Label on M3
100
SPOWER
Power and Ground region on cell
80
EXCL
DRC exclusion layer for logo, text etc drawing
21
ESD
ESD recognition layer
Comment
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22
SDI
Source/Drain recognition layer for ESD devices

(thick)
24
SDI2
Source/Drain recognition layer for ESD devices

(thin)
16:7
M1SLOT
M1 mark for hole creation inside wide sheet M1
18:7
M2SLOT
28:7
M3SLOT
16:8
DM1
M1 dummy used mark layer for metal fill
18:8
DM2
28:8
DM3
13:8
DPO2
PO2 dummy used mark layer for poly fill
3:8
DOD
OD dummy used mark layer for active fill
105
PLDMY
Power line recognition layer
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2.3 Terminology
Mask Name
Description
ID
Code
NW
192
N Well definition.
PW
191
P Well definition.
OD
120
Thin oxide definition of source, drain, and interconnection.
HRES
135
High resistive layer
PO2
130
Poly2 Si for gate and capacitor top plate
PO
140
Poly1 Si for resistor and capacitor bottom plate
PP
197
P+ implantation definition.
NP
198
N+ implantation definition.
CO
156
Definition of contact window from M1 to OD or PO.
M1
160
Definition of 1st metal for interconnection.
VIA1
178
Definition of contact window from M2 to M1.
M2
180
Definition of 2nd metal for interconnection.
VIA2
179
Definition of contact window from M3 to M2.
M3
181
Definition of 3rd metal for interconnection.
CB
107
Definition of bonding pad.
Terminology
N+ OD
Active area covered with NP
P+ OD
Active area covered with PP
N+ Diffusion
Active area covered with NP
P+ Diffusion
Active area covered with PP
Cold N Well
Well connected to the most positive voltage (Vdd)
Hot N Well
Well not connected to the most positive voltage
Hot N+ Diffusion
All N+ diffusion regions outside the NWELL potential not equal to

the substrate voltage.
Hot P+ Diffusion
All P+ diffusion regions inside the NWELL potential not equal to

the N Cold diffusions
Cold Diffusions
"Outside N-Well : a diffusion which has the potential same as the

substrate
Inside N-Well : a diffusion which has the potential same as the NWell."
Note: OD is known as active area.

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2.4 Definition of Layout Rules
Figure 2.4: Illustration of the layout definition rules
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2.5 Pitches
The pitches are listed as follows.
1
OD transistor pitch.
1.0 um
OD interconnect pitch.
0.9 um
OD pitch with 1 contact.
1.1 um
OD pitch with 2 contacts.
1.3 um
PO2 transistor pitch
0.8 um
PO2 interconnect pitch.
0.8 um
PO2 pitch with 1 contact.
1.025 um
PO2 pitch with 2 contacts.
1.25 um
PO2 capacitance pitch
1.45um
10 PO resistor pitch (low resistance)
1.15um
11 PO resistor pitch (high resistance)
1.55um
12 M1 pitch.
0.95 um
13 M1 pitch with 1 contact.
1.05 um
14 M1 pitch with 2 contacts.
1.15 um
15 M2 pitch.
1.1 um
16 M2 pitch with 1 VIA contact.
1.2 um
17 M2 pitch with 2 VIA contacts.
1.3 um
18 M3 pitch
1.1 um
19 M3 pitch with 1 VIA contact
1.2 um
20 M3 pitch with 2 VIA contact
1.3 um
21 Min. length of a transistor.
0.35 um
22 Min. width of a transistor.
0.4 um
23 PO interconnect width.
0.35 um
24 OD interconnect width.
0.3 um
25 CO width.
0.4 um
26 VIA1 width.
0.5 um
27 VIA2 width
0.5 um
28 N+/P+ spacing.
2.4 um
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2.6 Design Rules Description

2.6.1
NWELL Rules (192)

Rule
Number
Description
Legend
Layout
Rule
NW.W.1
Minimum dimension of a NW region
1.7um
NW.W.2
Minimum dimension of a hot NW region
A'
3.0um
NW.S.1
Minimum space between two NW regions with

different potentials
3.0um
1.0um
NW.S.2
Minimum space between two NW regions with the

same potentials.
NW shall be merged if space is less than 1.0um
Figure 2.6.1: Illustration of the design rules for Nwell (NW)
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2.6.2
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Active Area Rules (120)

Rule
Number
Description
Legend
Layout
Rule
OD.W.1
Minimum width of an OD region to define the

width of NMOS/PMOS
0.4um
OD.W.2
Minimum width of an OD region for

interconnect (N+/ or P+)
0.3um
OD.S.1
Minimum space between two OD regions (both

regions are either inside or outside a NWell)
which can be either N+ to N+, P+ to P+,or N+
to P+
0.6um
OD.C.1
Minimum clearance of a NW region beyond a

N+ OD region which is inside the NW (for NW
contact)
0.2um
OD.C.2
Minimum clearance from NW edge to a N+OD

region which is outside the COLD NW
1.2um
OD.C.3
Minimum clearance from NW edge to a N+OD

region which is outside the HOT NW
2.6um
OD.C.4
Minimum clearance of a NW region beyond a

P+ OD region which is inside the NW
1.2um
OD.C.5
Minimum clearance from NW edge to a P+OD

region (for PW pick up) which is outside the
NW
0.2um
OD.C.6A
Minimum clearance from poly edge to the edge

of OD region on NP with opposite type of
doping
0.45um
OD.C.6B
Minimum clearance from poly edge to the edge

of OD region on PP with opposite type of
doping
H'
0.45um
OD.S.2
Minimum space of N+ OD to P+ OD
1) For Butted diffusion
0.0um
2) For Non-Butted diffusion
0.6um
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Figure 2.6.2: Illustration of the design rules for Active Area (OD)
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2.6.3
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PO (POLY1) Rules (140)
Rule Number
Description
Legend Layout Rule
PO.W.1
Minimum width of CPOLY
0.8um
PO.W.2
Minimum width of PO
0.65um
PO.W.3
Minimum width of RPOLYH
0.8um
PO.S.1
Minimum CPOLY spacing
0.65um
PO.S.2
Minimum PO spacing
0.5um
PO.S.3
Minimum RPOLYH spacing
0.75um
PO.C.1
Minimum PO CO to CPOLY spacing
1.2um
PO.C.2
Minimum OD to PO spacing
0.2um
PO.C.3
Minimum PO to PO2 spacing
0.65um
PO.E.1
Minimum PO enclosure of CPOLY
1.0um
PO.E.2
Minimum CPOLY enclosure of PO2 CON
0.6um
PO.E.3
Minimum PO enclosure of PO CO
0.25um
PO.R.1
PO on OD is not allowed
INFO_POLY1
PO check angles 90/135 degree
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Figure 2.6.3: Illustration of the design rules for poly1
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2.6.4
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HRES Rules (135)
Rule Number
Description
Legend Layout Rule
HR.W.1
Minimum HRES width
0.6um
HR.S.1
Minimum HRES spacing
0.6um
HR.R.1
HRES is not allowed over OD
HR.R.2
HRES is not allowed over PPLUS
HR.R.3
HRES is not allowed over PO2
HR.E.1
Minimum HRES enclosure of PO
3.0um
HR.S.2
Minimum HRES to PO2 spacing
0.35um
HR.S.3
Minimum HRES to PO spacing
3.0um
HR.S.4
Minimum HRES to OD spacing
0.35um
Figure 2.6.4: Illustration of the design rules for HRES
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2.6.5
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PO2 (POLY2) Rules (130)
Rule Number
PO2.W.1_2_3
Description
Legend
Layout
Rule
Minimum width of a PO2 region
0.35um
PO2.S.1
Minimum space between two PO2 regions on OD area
0.45um
PO2.C.1
Minimum clearance from an OD region to a PO2 on field

oxide
0.2um
PO2.C.2
Minimum clearance from a PO2 gate to a related OD

edge
0.5um
PO2.O.1
Minimum overlap of a PO2 region extended into field

oxide (End Cap)
0.4um
PO2.R.1
PO2 not allowed on poly resistor.
INFO_PO2
PO2 check angles 90/135 degree
Minimum density of PO2 area.

Density is calculated as total layout area/chip area.
Add dummy PO2 patterns for those with PO2 density
less than 14%. Dummy PO2 patterns must be placed on
PO2_DENSITY_14 field oxide area and distributed over chip as uniformly as
possible.
*Please be aware of the coupling capacitor effect while
dummy PO2 patterns are added.
14%
Maximum density of PO2 area.

PO2_DENSITY_70 Reduce PO2 density for those with PO2 density more
than 70%.
70%
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PO2
Figure 2.6.5: Illustration of the design rules for poly2
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2.6.6 P+ S/D Rules (197)

Rule
Number
Description
Legend
Layout
Rule
PP.W.1
Minimum width of a PP region
0.6um
PP.S.1
Minimum space between two PP regions Merge if the space is

less than 0.6um
0.6um
PP.C.1
Minimum clearance from a PP region to a OD region
0.35um
PP.C.2
Minimum clearance from a PP region to a N Channel PO2 gate

(Please refer to pg.23)
0.45um
PP.C.3
Minimum clearance from a PP edge to a related P-Channel PO2

gate
0.45um
PP.O.1
Minimum clearance from a PP region to a related OD region
0.45um
PP.E.1
Minimum extension of a PP region beyond a PP OD region
0.25um
PP.C.5
Minimum clearance of a PP region to a NP region when both PP

and NP regions are located on PO2 region. Overlap of PP and
NP on the same PO2 region (which is seated on FOX) is not
allowed.
0.25um
PP.C.6
Clearance of a PP region over an OD with NP region to define

CO with the same potential
0.00um
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Figure 2.6.6: Illustration of the design rules for P+ implant layer
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2.6.7
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N+S/D Rules (198)
Rule
Number
Description
Legend
Layout
Rule
NP.W.1
Minimum width of a NP region
0.6um
NP.S.1
Minimum space between two NP regions Merge if the space is

less than 0.75um
0.6um
NP.C.1
Minimum clearance from a NP region to an OD region
0.35um
NP.C.2
Minimum clearance from a NP region to a P Channel PO2 gate

(Please refer to pg.21)
0.45um
NP.C.3
Minimum clearance from a NP edge to an N channel PO2 gate
0.45um
NP.C.4
Minimum clearance from a NP region to a related OD region
0.45um
NP.E.1
Minimum extension of a NP region beyond a NP OD region
0.25um
NP.C.5
Minimum clearance of a NP region to a PP region when both NP

and PP regions are located on PO2 region. Overlap of PP and
NP on the same PO2 region (which is seated on FOX) is not
allowed.
0.25um
NP.C.6
Clearance of a NP region over an OD with PP region to define

CO with the same potential
0.00um
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Figure 2.6.7: Illustration of the design rules for N+ implant layer
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2.6.8
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Contact Rules (156)
Rule
Number
CO.W.1
Description
Minimum/Maximum width of a CO region
Legend
Layout
Rule
0.40um
Butted Contact is not allowed

CO.S.1
Minimum space between two CO regions
0.40um
CO.C.1
Minimum clearance from a CO on OD region to a PO2

gate
0.30um
CO.C.2
Minimum clearance from a CO on PO2 region to a OD

region
0.40um
CO.E.1
Minimum extension of an OD region beyond a CO region
0.15um
CO.E.2
Minimum extension of a PO2 region beyond a CO region
0.20um
CO.E.3
Minimum extension of a PP region beyond CO region
0.25um
CO.E.4
Minimum extension of a NP region beyond CO region
0.25um
CO.R.1
CO on gate region is forbidden
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Figure 2.6.8: Illustration of the design rules for Contact
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2.6.9
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Metal-1 Rules (160)
Rule Number
Description
Legend
Layout
Rule
M1.W.1
Minimum width of a M1 region
0.50um
M1.S.1
Minimum space between two M1 regions
0.45um
M1.E.1
Minimum extension of a M1 region beyond a CO region
0.15um
M1.S.2A_2B
Minimum space between metal lines when one or both

metal lines width and length is > 10um.
0.8um
This also includes all metals attached to these areas or

extending out for a distance of 1.0um or less.
INFO_M1
M1 check angles 90/135 degree
Minimum density of M1 area.

Add dummy M1 patterns for those with M1 density less
than 25%. Dummy M1 patterns must be placed on field
M1_DENSITY_25 oxide area and distributed over chip as uniformly as
possible.
dummy M1 patterns are added.
25%
Maximum density of M1 area.

M1_DENSITY_50
Reduce M1 density for those with M1 density more than
50%.
50%
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Figure 2.6.9: Illustration of the design rules for Metal-1
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2.6.10 Via1 Rules (178)

Rule
Number
Description
Legend
Layout
Rule
VIA1.W.1
Minimum and maximum width of a VIA1
0.50um
VIA1.S.1
Minimum space between two VIA1 regions
0.45um
VIA1.E.1
Minimum extension of a M1 region beyond a VIA1 region
0.20um
VIA1.C.1
VIA1 can be fully or partially stacked on CO
*VIA1.0
VIA can be located at region on top of M1 over OD, PO2 over

field oxide, or field oxide
Figure 2.6.10: Illustration of the design rules for Via1
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2.6.11 Metal-2 Rules (180)

Rule Number
Description
Legend
Layout
Rule
M2.W.1
0.60um
M2.S.1
0.50um
M2.E.1
Minimum extension of a M2 region beyond a VIA region
0.15um
M2.S.2A_B
Minimum space between wide metal lines.
0.80um
Wide metal definition: when one or both metal line width

are greater equal to 10um; this also includes all metals
attached to these areas and extending out for a distance
of 1.0um or less.
INFO_M2

possible.
25%

M2_DENSITY_50
50%.
50%
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2.6.12 Via2 Rules (179)

Rule Number
Description
Legend Layout Rule
VIA2.W.1
Minimum and maximum width of a VIA2
0.50um
VIA2.S.1
Minimum space between two VIA2 regions
0.45um
VIA2.S.2
Minimum space between VIA2 to VIA1
B'
0.10um
VIA2.E.1
0.20um
VIA2.C.1
VIA2 can be fully or partially stacked on CO
VIA2.C.2
VIA2 cannot stacked VIA1
*VIA2.0
VIA2 can be located at any region but not on VIA1.
Figure 2.6.12: Illustration of the design rules for Via2
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2.6.13 Metal-3 Rules (181)

Rule Number
Description
Legend
Layout
Rule
M3.W.1
0.60um
M3.S.1
0.50um
M3.E.1
0.15um
M3.S.2A_B
Minimum space between wide metal lines.
0.80um
Wide metal definition: when one or both metal line width

are greater equal to 10um; this also includes all metals
attached to these areas and extending out for a distance
of 1.0um or less.
INFO_M3

possible.
25%

M3_DENSITY_50
50%.
50%
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2.6.14 Passivation Rules (107)

Rule
Number
CB.R.1
Description
Legend
Layout
Rule
The pad structure must be M3/VIA2/M2 /VIA1/M1.

VIA2 and VIA1 should form a diamond pattern in the
center of passivation window.
CB.W.1
Minimum dimension of a CB region bonding pad
86um
CB.S.1
Minimum space between two CB regions for bonding

pad
15um
CB.E.1
Minimum extension of a M1 region over a CB region
5.0um
CB.E.2
5.0um
CB.E.3
5.0um
CB.E.4
Minimum extension of a M1 region over the nearest

VIA1 (vias on the four corner of diamond)
3.0um
C.B.E5

VIA2 and VIA1 (vias on the four corner of diamond)
3.0um
C.B.E.6

VIA2 (vias on the four corner of diamond)
3.0um
CB.W.2
Minimum and maximum width of a VIA1 region in

bond pad area
0.50um
CB.W.3
Minimum and maximum width of a VIA2 region in

bond pad area
0.50um
CB.S.2
Minimum space between two VIA1 region
0.80um
CB.S.3
Minimum space between two VIA2 region
0.80um
CB.C.1
Minimum clearance between a VIA2 and VIA1
0.30um
CB.R.2
Minimum ratio of total exposed VIA1 area to CB

opening, 5%
CB.R.3
Minimum ratio of total exposed VIA2 area to CB

opening, 5%
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PAD
Figure 2.6.14: Illustration of the design rules for Passivation layer (CB)
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3.0 ESD Guidelines

Rule
Description
Number
ESDGuide.1
NMOS and PMOS I/O and ESD protection devices must follow a finger type
layout style. Every finger should be drawn with the same width.
ESDGuide.2
For a finger type ESD protection device the drain area should be located
between two source areas.
ESDGuide.3
PO2 as a gate should avoid using sharp shape but recommended used 45
degree.
ESDGuide.4
The corner of a metal line, which offers ESD current to pass through should be
drawn with a 45 degree corner.
ESDGuide.5
To avoid contact damaged by ESD current, place as many as possible contacts
on the source and drain active area. The contact count for both drain and
source should be equal. The contact to contact spacing should follow the
minimum design rule.
ESDGuide.6
To avoid via damaged by ESD current, place as many as possible vias on the
source and drain metal layer and on all interconnections in the ESD discharge
path. The via to via spacing should follow the minimum design rule.
ESDGuide.7
Recommended minimum contact (CO) spacing to the diffusion edge at drain
side for NMOS and PMOS is 2.0um.
ESDGuide.8
Recommended minimum width of metal lines for all connections within the IO
area is 4.8um.
ESDGuide.9
Recommended minimum width of metal line connecting to pad and protection
device is 28.8um.
ESDGuide.10 Metal from pad is advised to connect continuously to the transistor diffusion
without any poly jumps or diffusion.
ESDGuide.11 Recommended minimum metal width for power rail(VDD and GND) is 17.25um
ESDGuide.12 A pick-up ring should ideally surround the ESD protection device to avoid latch
up issues. For the NMOS device the pick-up ring is a P type and for the PMOS
device a N type.
ESDGuide.13 The pick-up ring and guard ring should be connected to different supply
voltages. For the NMOS device, the P type pick-up ring and N type guard ring
should be connected to VSS and VDD respectively. For the PMOS device, the
N type pick-up ring and P type guard ring should be connected to VDD and VSS
respectively.
ESDGuide.14 The N type guard ring of the NMOS device should be constructed in NWELL.
ESDGuide.15 The VIA1 and VIA2 cannot stack together. Minimum spacing of VIA1 and VIA2
is 0.1um.
ESDGuide.16 SDI layer have to be drawn over ESD MOS to define it as thick gate ESD MOS
with minimum length of 0.5um. If thin gate ESD MOS of minimum length
0.36um is desired, another layer SDI2 is to be added besides the SDI layer.
ESDGuide.17 ESD layer is to be drawn on the source of the ESD MOS for the DRC check to
run the ESD Design Rules for 0.35um NMOS and PMOS Protection Circuits.
*All these guidelines are not verified by the DRC.
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4.0 ESD Design Rules for NMOS/PMOS Protection Circuits

Rule
Number
Description
Legend Layout
Rule
ESD.1
Minimum contact (CO) spacing to polygate (PO2) at the source

side for PMOS.
0.85um
ESD.2
Minimum contact (CO) spacing to polygate (PO2) at the drain side

for PMOS.
2.55um
ESD.3
Minimum PO2 length of NMOS gate (thick gate).
0.5um
ESD.4
Minimum PO2 length of PMOS gate (thick gate).
0.5um
ESD.5
Minimum single finger width for NMOS.
40um
ESD.6
Minimum single finger width for PMOS.
40um
ESD.7
Minimum contact (CO) spacing to polygate (PO2) at the source

side for NMOS.
0.85um
ESD.8
Minimum contact (CO) spacing to polygate (PO2) at the drain side

for NMOS.
4.0um
ESD.9
Minimum PO2 length of NMOS gate (thin gate).
0.36um
ESD.10 Minimum PO2 length of PMOS gate (thin gate).
0.36um
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PMOS ESD
NMOS ESD
Figure 4.0: Illustration of the design rules of ESD NMOS/PMOS.

*Figure 4.0 above showing NMOS/PMOS ESD Design Rules are not a complete NMOS/PMOS ESD layout.
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5.0 ESD Implantation Rules

Rule
Number
Description
Legend
Layout
Rule
ESD.W.1 Minimum width of an ESD implant region.
0.9um
ESD.S.1
Minimum space between two ESD implant region. Merge if

the space is less than 0.9um.
0.9um
ESD.S.2
Minimum space between ESD implant and NP or PP region.
0.2um
ESD.C.1
Minimum clearance from an ESD implant region to an NP

OD region.
0.45um
ESD.C.2
Minimum clearance from an ESD implant region to an PP

OD region.
0.45um
ESD.C.3
Minimum clearance from an ESD implant region to Nchannel PO gate.
0.7um
ESD.C.4
Minimum clearance from an ESD implant region to Pchannel PO gate.
0.7um
ESD.O.1
Minimum overlap from an ESD implant edge to an OD

region
0.7um
ESD.C.5
Minimum clearance from an ESD implant region to an ESD

OD region.
0.9um
ESD.E.1
Minimum enclosure of an ESD implant region over an ESD

implant OD region.
0.3um
*ESD layer is drawn over the Source of the ESD NMOS/PMOS following above rules.
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ESD
Figure 5.0: Illustration of the design rules of ESD layer
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6.0 SDI Rules

Rule
Number
Description
Legend Layout
Rule
SDI.1
Min enlosure of SDI/SDI2 over PMOS ESD
0.3um
SDI.2
Min enlosure of SDI/SDI2 over NMOS ESD
0.3um
SDI.3
ESD have to be inside SDI
SDI.4
SDI2 without SDI is not allowed
*SDI layer is used to recognize MOS as thick gate ESD MOS whereas SDI with SDI2 layers are
used to recognize MOS as thin gate ESD MOS.
SDI/SDI2 on PMOS ESD
SDI/SDI2 on NMOS ESD
Figure 6.0: Illustration of the design rules of SDI.
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7.0 Gate Width Rules

Rule
Number
Description
Legend
Layout
Rule
GATEN.W.1 Maximum dimension of a N-gate width and length
20um
GATEP.W.1 Maximum dimension of a P-gate width and length
20um
8.0 Antenna Effect Prevention Design Rules

Rule
Number
Description
Layout
Rule
PO2.ANT.1 Maximum drawn ratio of PO2 perimeter area to the active PO2 gate area
connected directly to it.
100
CO.ANT.1
10
Maximum drawn ratio of CO area to the active PO2 gate area connected
directly to it.
VIA1.ANT.1 Maximum drawn ratio of VIA1 area to the active PO2 gate area
50
VIA2.ANT.1 Maximum drawn ratio of VIA2 area to the active PO2 gate area
50
M1.ANT.1
Maximum drawn ratio of M1 perimeter area to the active PO2 gate area
400
M2.ANT.1
400
M3.ANT.1
400
*PO2 thickness is 0.3350um = 3350 A.

*M1 thickness is 0.6800um = 6800 A.
The definition of PO2, M1, M2 and M3 antenna ratio is
ratio = perimeter x thickness
gate area
ratio =
2(L1+W1) x t
L2xW2
The definition of CO, VIA1 and VIA2 antenna ratio is

ratio = contact or via area
gate area
ratio = contact or via area
L2 x W2
where
L1 : floating metal length connected to gate
L2 : connected transistor channel length
W1: floating metal width connected to gate
W2: connected transistor channel width
t : metal thickness
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Figure 8.0: Illustration describing antenna ratio.
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9.0 Latch-Up Prevention Rules

Rule
Number
LUP.1
LUP.2
LUP.3
LUP.4
Description
Maximum distance from any point inside
Source/Drain OD area of PMOS to nearest pickup
OD in the same NWEL
Source/Drain OD area of NMOS to nearest pickup
OD in the same PWEL region
Source/Drain OD area of NMOS to nearest pickup
OD in the same PSUB region
Maximum N+ OD and P+ OD area allowed without
surrounding guardring
Legend
Layout
Rule
20um
20um
20um
400um2
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Guard ring
N+/P+
400um2
Figure 9.0: Illustration of the design rules for Latch-up prevention
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10.0 Metal Stress Relief

10.1 Metal Slot for Metal-1
Rule
Number
Legend
Layout
Rule
M1SLOT.W.1 Minimum width of a M1SLOT region
1.0um
M1SLOT.S.1
Minimum space between two M1SLOT regions
8.0um
M1SLOT.E.1
Minimum extension of a M1 region beyond a M1SLOT

region
10um
M1SLOT.A.1
Minimum area of a M1SLOT region
AMS.1.M1
AM.W.3.M1
AMS.DN.M1
Description
Maximum width of M1 region allowed without M1SLOT

Minimum width of a M1 branch connected to wide M1
region
Minimum slot density for wide M1 region. Density
calculated as: M1SLOT/Wide metal layout area
10um2
D
30um
10um
Minimum M1SLOT density is required to be 1.5%

M1SLOT.E.2
M1SLOT without M1 is forbidden
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Figure 10.1: Illustration of the design rules for metal1 slot
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Rule
Number
Legend
Layout
Rule
1.0um
M2SLOT.S.1
8.0um
M2SLOT.E.1

region
10um
M2SLOT.A.1
AMS.1.M2
AM.W.3.M2
AMS.DN.M2
Description

region
10um2
D
30um
10um

M2SLOT.E.2
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Rule
Number
Legend
Layout
Rule
1.0um
M3SLOT.S.1
8.0um
M3SLOT.E.1

region
10um
M3SLOT.A.1
AMS.1.M3
AM.W.3.M3
AMS.DN.M3
M3SLOT.E.2
Description

region
10um2
D
30um
10um
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11.0 Power Line Rules and Guidelines

Rule Number
Description
Legend
Layout
Rule
PL_M1.W.1
Minimum width of a M1 Power Line region
4.0um
PL_M1.S.1
Minimum space between two M1 Power Line regions
1.0um
PL_M2.W.1
4.0um
PL_M2.S.1
1.0um
PL_M3.W.1
4.0um
PL_M3.S.1
1.0um
ADP.S.1_CO
Minimum space between two CO Power Line regions
0.8um
ADP.S.1_V1
Minimum space between two VIA1 Power Line regions
0.8um
ADP.S.1_V2
Minimum space between two VIA2 Power Line regions
0.8um
0.4um
0.4um
0.4um
0.4um
0.4um
0.4um
0.4um
0.4um
ADP.C.1_CO_V1
ADP.C.1_V1_V2
ADP.E.1_CO_PO
ADP.E.1_CO_M1
ADP.E.2_V1_M1
ADP.E.2_V1_M2
ADP.E.2_V2_M2
ADP.E.2_V2_M3
Minimum space between CO Power Line & VIA1

Power regions
Overlap of CO Power Line & VIA1 Power regions not
allowed
Minimum space between VIA1 Power Line & VIA2
Power regions
Minimum extension of a PO Power Line region beyond
a CO Power Line region
Minimum extension of a M1 Power Line region beyond
a CO Power Line region
a VIA1 Power Line region
INFO_PL_M1
M1 Power Line should turn 45 degrees from corners
INFO_PL_M2
INFO_PL_M3
ADP.R.0D
CO and VIA1 overlap or VIA1 and VIA2 overlap not

allowed in Power Line structures
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Figure 11.0: Illustration of the design rules for power line rules
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12.0 Seal Ring

Seal ring is provided in the C035a MIMOS technology library. MIMOS recommend scribe line seal
and scribe guard ring rules as following schematic diagram. Assembly isolation depends on the
capability of assembly house. The 25um is for reference.
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13.0 ELEMENT RULES

13.1
MOS
13.1.1 PMOS
Device
PMOS
Description
pmos 4 pins
Model Name
pch
Model Netlist
hspice, spectre
GDSII/Sample Layout
Yes
Fixed/Variable Layout
PCell
Parameters
Min
Max
Gate length, l ()
0.35
20
Gate width, w ()
0.4
20
No. of fingers, m
100
Figure 13.1.1: PMOS
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13.1.2 NMOS
Device
NMOS
Description
nmos 4 pins
Model Name
nch
Model Netlist
hspice, spectre
GDSII/Sample Layout
Yes
PCell
Parameters
Min
Max
Gate length, l ()
0.35
20
Gate width, w ()
0.4
20
No. of fingers, m
100
Figure 13.1.2: NMOS
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RESISTOR
13.2.1 RES_NWELL
Device
RES_NWELL
Description
nwell resistor
Model Name
nwl
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
Sheet resistance, rsh (/)
1.4K
1.556K
1.711K
Min
Max
Width, w ()
Length, L ()
150
Figure 13.2.1: RES_NWELL
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13.2.2 RES_NDIFF
Device
RES_NDIFF
Description
n+ diffusion resistor
Model Name
dfn
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
102.725
146.75
190.775
Min
Max
Width, w ()
0.7
10
Length, L ()
1.4
150
Figure 13.2.2: RES_NDIFF
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13.2.3 RES_PDIFF
Device
RES_PDIFF
Description
p+ diffusion resistor
Model Name
dfp
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
186.48
207.2
227.92
Min
Max
Width, w ()
0.7
10
Length, L ()
1.4
150
Figure 13.2.3: RES_PDIFF
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13.2.4 RPOLY1
Device
RPOLY1
Description
poly1 resistor
Model Name
rpoly1
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
81.04
101.3
121.56
Min
Max
Width, w ()
0.9
10
Length, L ()
1.8
150
Figure 13.2.4: RPOLY1
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13.2.5 RPOLYH
Device
RPOLYH
Description
high poly1 resistor
Model Name
rpolyh
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
953.6
1.192K
1.4304K
Min
Max
Width, w ()
0.8
10
Length, L ()
1.6
150
Figure 13.2.5: RPOLYH
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13.2.6 RM1
Device
RM1
Description
metal-1 resistor
Model Name
rm1
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
0.100
Min
Max
Width, w ()
0.8
32
Length, L ()
0.8
500
Figure 13.2.6: RM1
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13.2.7 RM2
Device
RM2
Description
metal-2 resistor
Model Name
rm2
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
0.100
Min
Max
Width, w ()
0.8
32
Length, L ()
0.8
500
Figure 13.2.7: RM2
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13.2.8 RM3
Device
RM3
Description
metal-3 resistor
Model Name
rm3
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
Min
Typ
Max
0.050
Min
Max
Width, w ()
0.8
32
Length, L ()
0.8
500
Figure 13.2.8: RM3
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13.3 CAPACITOR
13.3.1 CPOLY
Device
CPOLY
Description
square poly1-insulate-poly2 capacitor
Model Name
cpoly
Model Netlist
hspice, spectre
GDSII/Sample Layout
yes
PCell
Parameters
2
Area Capacitance, c (fF/um )
Min
Typ
1.000
1.053
Min
Width, w ()
Length, l ()
Max
1.200
Max
25
200
25
200
Figure 13.3.1: CPOLY
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13.3.2 NCAP
Device
NCAP
Description
nmos capacitor
Model Name
ncap
Model Netlist
hspice, spectre
GDSII/Sample Layout
Yes
PCell
Parameters
Area Capacitance, c (fF/um2)
Width, w ()
Length, l ()
Min
Typ
Max
4.362
Min
Max
100
100
Figure 13.3.2: NCAP
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13.3.3 PCAP
Device
PCAP
Description
pmos capacitor
Model Name
pcap
Model Netlist
hspice, spectre
GDSII/Sample Layout
Yes
PCell
Parameters
Area Capacitance, c (fF/um2)
Width, w ()
Length, l ()
Min
Typ
Max
3.929
Min
Max
100
100
Figure 13.3.3: PCAP
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DIODE
13.4.1 PDIO_D
Device
PDIO_D
Description
P+/NW diode
Model Name
pdiode
Model Netlist
hspice, spectre
GDSII/Sample Layout
Yes
variable
Parameters
Min
Max
Length, l ()
0.7
500
Width, w ()
0.7
500
Figure 13.4.1: PDIO
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13.4.2 NDIO_D
Device
NDIO_D
Description
N+/PW diode
Model Name
ndiode
Model Netlist
HSpice, Spectre
GDSII/Sample Layout
Yes
Variable
Parameters
Min
Max
Length, l ()
0.7
500
Width, w ()
0.7
500
Figure 13.4.2: NDIO
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13.5 BIPOLAR
13.5.1 VPNP
Device
VPNP
Description
Vertical PNP
Model Name
vpnp5, vpnp10
Model Netlist
hspice, spectre
GDSII/Sample Layout
Yes
Fixed
Parameters
Min
Max
Emitter size ()
5x5
10 x 10
Figure 13.5.1: VPNP10
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14. SUPPORT
For questions or information, please contact
Iskhandar Md Nasir (Senior Staff Engineer)
Tel: +60 3 8995 5000 ex5149, +60 3 8657 9907 (DL)
Email: iskhand@mimos.my
Muhamad Amri Ismail (Senior Engineer)
Tel: +60 3 8995 5000 ex5520
Email: amris@mimos.my
Nurafizah Saidin (Engineer)
Tel: +60 3 8995 5000 ex5710
Email: nurafizah.saidin@mimos.my
MIMOS Wafer Fab Design Library
Mimos Berhad, Technology Park Malaysia, 57000 Kuala Lumpur, Malaysia
Tel: +603 8995 5000
Page 72 of 72

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35um CMOS Reference Manual

MIMOS Authorized Recipient Only

0.35um CMOS Reference Manual

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

1. Change PO2 as polygate

Add Elements rules for basics devices

16/07/2007 Add diode definitions layers

MIMOS INTERNAL USE ONLY

New template MIMOS Wafer fab 2009

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

Review and Approval Records

Wafer Fab Design

Muhamad Amri Ismail

Wafer Fab Design

Wafer Fab Design

MIMOS INTERNAL USE ONLY

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

ESD DESIGN RULES FOR NMOS/PMOS PROTECTION CIRCUIT 38

ESD IMPLANTATION RULES.. 40

GATE WIDTH RULES 43

ANTENNA EFFECT PREVENTION RULES.. 43

9. LATCH-UP PREVENTION RULES 45

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

MIMOS INTERNAL USE ONLY

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

1.1 Confidential Proclamation

MIMOS INTERNAL USE ONLY

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

2.1 Drawn Mask Layer

Key Process Sequence

MIMOS INTERNAL USE ONLY

0.35um CMOS Reference Manual

MIMOS Authorized Recipient Only

2.2 Design Layer

Hot NWell definition layer

MOS active region

POLY2 for gate and capacitor top plate

POLY1 for resistor and capacitor bottom plate

Source/Drain region P+ implant

Source/Drain region N+ implant

Contact hole on diffusion and poly region

1st layer metal

Vias between 1st and 2nd layers metal

2nd layer metal

Vias between 2nd and 3rd layers metal

3rd layer metal

High resistive layer

Passivation hole opening

Ndiff or Pdiff resistor definition layer

Frame Cell Label

Analog block definition area

Capacitor definition layer

CPOLY definition layer

Diode definition layer

Nwell or PO resistor definition layer

Power and Ground region on cell