IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 02 | August 2016

ISSN (online): 2349-784X

Low Voltage and Low Power in SRAM Read and

Write Assist Techniques
Dipti Choudhary
PG Student
Department of VLSI
Indraprastha Engineering College, Dr. APJ Abdul Kalam
University, U.P., India

Vipul Bhatnagar
Assistant Professor
Department of Electronics & Communication Engineering
Indraprastha Engineering College, Dr. APJ Abdul Kalam
University, U.P., India

Abstract
This paper presents Read and Write assist techniques which are now commonly used, by minimizing the operating voltage i.e.,
Vmin of an SRAM cell. Basically read assist refers to retain the data when SRAM cell is at low voltage supply with reduced size.
And write assist refers to write new data in the cell at low supply voltage with reduced size of transistor. Write failures (writeability) or read failures (read-ability) are causing limitation to minimum supply voltage means minimizing the supply voltage
causing hurdle in writing and reading a data. Write and Read failures are significantly affected by voltage optimization and SRAM
6T cell property is highly dependent on supply voltage. Various SRAM cells are designed which offers better resilience as
compared to SRAM 6T cell. In this paper, various read and write assist techniques are discussed and compared. The major problem
is faced during write assist at low voltage as the cell gets flipped and the data cannot be written. This effect gets more pronounced
as the size of transistor is being reduced day by day as per consumer demand. As a result, it assists SRAM write operation with
better performance and stability.
Keywords: Assist Techniques, Read Assist, SRAM Write Assist
________________________________________________________________________________________________________
I.

INTRODUCTION

Fig.1 shows a typical SRAM cell is made up of 6 MOSFET. Fig.2 shows each bit in SRAM is stored in four transistors
M1,M2,M3,M4 that form two cross coupled inverters and this storage cell has two states named 0 and 1 state. Two more access
transistors (M5 and M6 i.e., ACL and ACR) are also implied which serve to control the access to storage cell during write and read
operation.

Fig. 1: Conventional 6T SRAM cell schematic.

Fig. 2: Conventional 6T SRAM cell schematic with cross coupled inverters and it states.

The memory cell consists of simple CMOS latch (two inverters connected back to back) and two complementary access
transistors (M5 and M6). The cell will preserve one of its two possible states, as long as the power supply is available. The access
transistors (M5 and M6) are turned on whenever a word line (row) is activated for read or write operation, connecting the cell to

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the complementary bit-line columns. Cell access is enabled by the word line (WL) that controls the access transistors (M5 and
M6) and which decide that whether the cell will be connected to bit line bar (BLB) or bit line (BL). These access transistors are
used to transfer data for write operation and read operation. It is not necessary to have only two bit lines (BLB or BL). There is
possibility of more than six transistors in a SRAM cell. Generally, fewer transistors per cell, the smaller each cell can be made.
And therefore, cost of processing a silicon wafer is fixed relatively. Thus by using smaller cell and packaging more bits on one
wafer reduces the cost per bit of memory. SRAM cell has three different states which are named as writing (when content has to
be updated), reading (when retention of data is requested), and standby mode (when circuit is idle). SRAM cell which operates in
write mode should have write-stability; cell which operates at read mode should have readability.
Working
Firstly, write/writing i.e. write stability, the write cycle is initiated by applying value which is to be written to the bit lines that is
by setting BLB to 1 state and BL to 0 state. This is quite similar to applying a reset pulse to an SR-latch which causes the Flip-flop
to change its state. To write 1, it can be done by inverting the values of bit lines. The word line (WL) is then asserted the value
which was needed to be stored is latched in. And this works as the input drivers of bit line are designed to be much stronger than
the transistor in the cell itself so that it can easily override the previous state of cross-coupled inverters. Generally, access NMOS
transistors M5 and M6 have to be robust than either bottom NMOS (M1 and M3) or top PMOS (M2 AND M4). Consequently,
when one pair of transistor (M3 and M4) is only slightly overridden by writing process then the opposite pair (M1 and M2) gate
voltage is also changed. This meant M1 and M2 transistors can be easier overridden and so on. The cross coupled inverters magnify
the write processing. SRAM can store its data as long as power is supplied. The term random access means that in an array of
SRAM cell each of the cells can be write/read in any sequence no matter which cell was last accessed.
Secondly, read/ reading i.e. readability (data has been requested) is initiated by pre-charging both bit lines BLB and BL. That
means driving it to threshold voltage VTH (can vary between 0 and 1). Now, word line WL is asserted. This word line (WL)
asserted and enables both access transistors (M5 and M6). Bit line (BL) voltage either slightly rise or drop where drop refers to
that bottom transistor NMOS M3 gets turned ON and top transistor PMOS gets M4 OFF and rise refers that top transistor PMOS
M4 is turned ON and bottom transistor NMOS M3 is turned OFF. If bit line (BL) voltage raises then bit line bar (BLB) voltage
drops and if bit line (BL) voltage drops then bit line bar (BLB) voltage rises.
Thirdly, standby mode, when the cell is idle. If word line (WL) is not asserted the access transistors (M5 and M6) disconnect
cell from bit line. The two cross coupled inverters formed by M1, M2, M3, and M4 will continue to reinforce each other as long
as they are connected to power supply.
Different works are compared depending on assist features and often little trade off are also seen. Power and cost are prominent
factors to analyze optimal method. Firstly, we have method should meet delay and functional requirements. Once these conditions
are met then implementation cost and power can be examined. A range of SRAM functional assist methods have been proposed
and discussed [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20 ,21,22,23].
Portable electronics devices have extremely low power to achieve long battery life time. To minimize the power consumption
numerous device-/circuit-/architectural-level techniques have been implemented. Supply voltage scaling has significant impact on
overall power dissipation. The effect of process variation in scaled CMOS technology is a key issue of performance. And SRAM
is one of the highly sensitive circuits to process variations due to too small size of device in order to achieve high density. Process
variations can also be due to local or global mismatches between devices. Overall power dissipation is significantly impacted by
supply voltage scaling. The dynamic power reduces quadratically, with the supply voltage reduction while the leakage power
reduces linearly. However, the sensitivity of circuit parameters to process variations increases as the supply voltage is reduced.
SRAM bit cells employing minimum-sized transistor, limits the circuit operation in the low-voltage regime. These least transistors
geometry is also vulnerable to intradie as well as interdie process variations. Intradie process variations include line edge roughness
(LER) and random dopant fluctuation (RDF). This can lead to mismatch of threshold voltage between the adjacent transistors in a
bit cell of memory which can result in asymmetrical characteristics. The combined effect of increased process variation along with
lower supply voltage may result in increased memory failures such as write failure, read failure, hold failure and access time failure.
And it is predicted that embedded cache memories, those occupies significant portion of total die area will be more prone to failures
with scaling.
II. ASSIST METRICS
The object of this work is focused on the functional metrics of margin sensitivity and performance. In this section, we define and
quantify of the margin and performance metrics used in this analysis.
Margin Sensitivity
Margin sensitivity can be defined as the change in margin with respect to the change in applied assist bias voltage. This can be
expressed as:
Sensitivity = (margin)/V
Margin may refer to either SNM or WM. Margin sensitivity is defined a useful metric for quantitatively comparison of assist
method effectiveness and provides a mean of quantitatively determining the attainable margin improvement. To compare the assist

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methods to one another and also across the technology nodes is applicable to all the bias based assist methods. We perform noise
margin analysis using custom predictive technology models (PTMs) using pre-defined scaled SRAM dimensions consistent with
the dense SRAM published values to compare the margin sensitivity of the specific assist methods [24,25]. Using different assist
methods, limitation factors will constrain the terminal bias values that can be applied. Voltage suppression schemes like +VSS
(write), -VDD (write) or WL (read) have limiting factor by different mechanisms. Since there are boosting schemes like +WL
(write), negative BL (write), +VDD (read) or VSS (read), their common limiting factor is Vmax. Considering an example, bias
used collapsing the supply voltage (+VSS or VDD), and becomes limited due to data retention failure at un-accessed cell which
share collapsed supply voltage. With reduced word line voltage, performance limitations can quickly limit the allowable bias
available for read stability margin gains obtained for WL (read).
The nominal VDD is based on published industry values for the nodes of interest. In this paper, we have used Vwc (worst case
voltage) refers to the minimum voltage on which SRAM should be able to perform both write and read operation across the
complete array without considerable failure. So for this we have to assure that VDmin must be at or below pre-defined Vwc of
each methodology node for a given array without any hurdle.
As part of the methodology defined in this investigation, we will place particular emphasis on the specific conditions that
represent worst case operation voltage (Vwc) for the technology. We define Vwc as the minimum voltage at which the SRAM
must be able to perform both a read and write operation across the entire array without failure. Vwc is recognized as technology
and application dependent. Thus, we need to ensure that the VDDmin for a given array is at or below our predefined Vwc for each
technology node. This condition accounts for factors such as NBTI shifts over product lifetime, voltage droop, and testing
equipment variability. Here, we will also determine impact and variation of assist method on margin distribution in addition to the
shift in the mean margin value.
Performance
The performance of the given assist method is determined by using time required for bit line signal development for read assist
and write delay for write assist method. For the calculation, we are concerned more about the delta and allow us to focus on two
important performance parameters. We can reduce delay to the period of time required to develop a sufficient differential voltage
on the BL (BL) to set the sense amplifier and time needed to charge word line ( WL)
read = WL + BL
The read assist method of reduced WL voltage is considered to determine how the assist method may impact the read. For this
example, while the BL will be increased, the WL will be reduced. The write performance (write) estimate will require three
components:
write = BL + wcell + WL
By following a similar approach as with the read performance evaluation, considering the deltas associated with the assist
methods for comparison purposes. wcell is the delay associated with the cell state change given the applied BL differential and
WL voltage, and BL is the delay (or part of delay that does not overlap with WL) required to establish the BL-BLB voltage
differential for the write operation; the value WL is constant.
Margin Analysis
The margin analysis shows the limitations of the assist methods in the relevant design area. To derive a final effectiveness factor
we used margin sensitivity factor and performance factor and a graphical (margin/delay) space analysis will also be used [26]. Fig.
3 Shows delay requirements of the memory and delineated by the margin of the desired functional window. The read /write margins
and corresponding performance degrade when VDD is reduced to Vwc. Assist methods help in improving margin and delay to
much extent. The graph allows us to readily understand potential advantage, trade off of a given assist approach and provides
additional insight into the net functional impact of a given assist method.

Fig. 3: Schematic diagram for read/write delay versus read/write margin and desired functional window based on margin limited yield and
performance requirements [26].

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III. READ ASSIST TECHNIQUES

SRAM cells employ aggressively small cells that make them vulnerable to process variation in nano-scale CMOS technologies.
To ensure fast and reliable read operation requires additional techniques and treatment like read-assist technique which is caused
by increased effect of process variations in nano-scale technologies and it should result in considerable reduction in leakage power
dissipation. Fig. 4(a-d) shows variety of read assist with their graphical representation.

(a)

(b)

(c)

(d)
Fig. 4: Schematic timing diagram representation for read assist (a) raised array global VDD, (b) negative VSS at the cell, (c) VDD boost at the
cell, (d) WL droop. represents the time for sense amplifier to set. Text box denotes modulated terminals.

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(a)

(b)

(c)

(d)

Fig. 5: Read SNM as a function of (a) raised array global VDD, (b) negative VSS at the cell, (c) VDD boost at the cell, (d) WL droop [26].

Four read assist techniques which are represented in fig. 4 (a-d) are shown with SNM function in fig 5(a-d). There are four
leading techniques for read assist applied in SRAM bit cells. These techniques has significantly overcome read failures in SRAM
bit cell and capable of providing better read stability. During read operation, read failures occur in bit cell when the enough charge
on the bit line is transferred to the internal storage nodes and flip it states. There are two ways to achieve read stability in SRAM
bit cell with the help of read assist techniques. First method is to improve the cross coupled inverter pair stability by reducing the
VSS and raising the core VDD in SRAM bit cell during read operation. There is an advantage of reducing VSS that is to
significantly reduce the read delay by strengthening both pull down and pass gate transistors. The second method to increase the
read stability in SRAM; pull down transistor should be stronger than pass gate transistor.
Fig.6. shows one other technique for read assist is using 8T SRAM cell in which we can isolate read path from storage nodes
and write path. Here in this cell there are 6T for storage purpose and 2T for read buffer. While reading the cell, the read current
will flow through the two read buffer transistor i.e. R1 and R2 and its variation will not affect the read margin.
The write margin is an important parameter in scaled supply voltages and supply voltage scaling is an effective way to decrease
the power consumption of the system on chips.

Fig. 6: 8T SRAM which isolates the read path from write path and the storage nodes.

IV. WRITE ASSIST TECHNIQUE

In order to enhance the write margins of SRAMs, various techniques of write assist have been proposed. And write-assist (WA)
techniques are important and results in reducing the VMIN of SRAMs. Write assist help the bit cell to state during write operation.
WA techniques have been proposed in literature to improve the scaling. There are several write-assist techniques:
Negative bit-line Write assist
Word-line boosting Write assist
VSS raising Write assist
VDD lowering Write assist.
Raise global VDD Write assist.
Weaken pull-up PMOS write assist.
Strengthening of pass-gate NMOS write assist.
There are publications who address to enhance write margin by reducing the latch strength that include reducing the supply
voltage VDD [2,5,6,8,11,17,] , by raising VSS [12,22,23] and by reducing the strength of the pull-up PMOS by NWELL bias
[10,19]. And there is no clear agreement in the industry to state that which of the methods can result as optimal solution.
Negative Bit-Line (NBL) Write Assist
Negative bit-line write assist technique optimizes write margin producing negative voltage on low going bit line instead of ground
of SRAM. This negative voltage on bit line BL increases the strength of access transistors by increasing VGS from word line
voltage (VWL). This approach of negative bit line is to create the bit line voltage below 0 during write margin. Thus to create
larger VGS of the pass transistor NMOS, either source voltage needs to be decreased or gate voltage need to be increased. The

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increase on VGS causes the access transistors to become stronger and hence result can flip the bit cell easily. Fig. 7 shows negative
bit line with graphical representation. The negative bit line voltage can be generated internally by using capacitive coupling
technique. In NBL technique which uses capacitive coupling, the negative voltage level on BL and the time at which this voltage
is applied to the bit line are very important.

Fig. 7: a schematic representation of write assists Negative Bit Line approach.

This write assist technique works on the column and therefore all the un-accessed bit cells in the column gets an increase in VGS
on pass transistor. As word lines WL are not asserted for all those cells. This technique ultimately increases the VGS of access
transistor. The benefit of this write assist scheme increases well when supply voltage is scaled down.
Word Line Boosting Write Assist
Here is another method to write assist that cause bit cell to flip during write event and is done by boosting the word line WL higher
than the supply voltage. The VGS of access transistor is increased by boosting and improves the strength and after strength
increased of access transistor it helps in flipping the bit cell. The boost voltage can be produced internally by capacitive coupling
similar to negative bit line approach. This technique works on row unlike negative bit line technique (works on column). This write
assist technique is better than the nominal case with no write assist. The benefit of this write assist scheme increases significantly
as the supply voltage is scaled down. Fig 8 shows word line boosting write assist with graphical representation.

Fig. 8: Schematic representation for write assists Word Line Boosting.

VSS Raising Write Assist

Here is another way to aid write assist technique that is by raising ground. The concept is to weaken the pull up transistor PMOS
but here it is done by weakening the PMOS gate voltage. The ground is raised during write operation. This ground voltage can be
generated by internally using a regulator. This WA technique also impacts the dynamic read noise margin (DRNM) of the halfselected bit cells, if implemented globally for the whole array. This technique reduces the risk of data retention failure. This write
assist is better than non write assist case but the gain very small. Fig. 9 shows VSS raising write assist with graphical representation.

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Fig. 9: Schematic representation for write assists VSS Raising.

VDD Lowering Write Assist

This technique states that world line voltage VWL can be reduced by weakening the pull up transistor with respect to the pass gate
transistor. And once the pull up transistor is weakened, and then it becomes easier to write a new data to the bit cell. This write
assist technique is implemented by using an external lower supply voltage i.e. second, which will be connected via a multiplexer
to write selected columns. There is another way also to generate second external supply voltage during write operation and it can
be done by on chip regulators. Fig 10 shows VDD lowering write assist with graphical representation.
There are other methods also to lower VDD like an appropriately sized pre-discharged capacitance to create lower voltage level
etc. the major challenge faced during this technique is to make sure that lower column voltage should be higher than the retention
voltage of unselected bit cells on same column. This technique decreases the DRNM of half selected bit cell. There is a reason,
that making pull up PMOS transistor further weak does not help much because PMOS is already weak in current generation bit
cells. In this write assist technique performance is better than a nominal case but the gain is minuscule. The write assist methods
simulation result is described in fig. 11 (a-d) for fig 7-10.

Fig.10: Schematic representation for write assists VDD Lowering.

(a)

(b)

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(c)
(d)
Fig. 11: Write margin as a function of (a) negative bit-line approach, (b) word line boost, (c) VSS rising and (d) VDD lowering [26].

V. NOISE MARGIN
Noise margin is defined as the amount by which a signal exceeds the minimum amount for proper operation. In simple words noise
margin is the amount of the noise that a circuit can stand with. Noise margins are those negative margins result in compromised
operation and positive values ensuring proper operation.
Write Static Noise Margin
The write noise margin is defined as the minimum bit line needed to flip the state of cell. The value of the write margin depends
on the cell design, SRAM array size and process variation. Write SNM (WSNM) is measured using butterfly or VTC curves.
Read Static Noise Margin
RSNM determines the read stability of the SRAM cell. The cell is most vulnerable when accessed during a read operation because
it must retain its state in the presence of the bit line pre-charge voltage. If the cell is not designed properly, it may change its state
during a read cycle which results in either a wrong data being or a destructive read where the cell changes state.
Data Retention Voltage (DRV)
The minimum supply voltage which is supported by the cell beyond which the cell state flips is the Data Retention Voltage.
This is primarily due to use of high threshold voltage transistors in the cell, which reduces the current in the cell required to sustain
the latch operation during standby mode.
Leakage Power
Leakage power is primarily the result of unwanted sub threshold current in the transistor channel when the transistor is turned
off. This sub threshold-driven leakage power is strongly influenced by variations in the transistor threshold voltage V T.
Read Delay
It is dened as the time delay between 50% WL activation to when the sense amplier has reached 90% of its full swing, should
be measured at the worst case scenario.
Write Delay
The write delay is dened as the time between the activation 50% of WL to when QBAR is 90% of its full swing.
VI. CONCLUSION
As the CMOS technology has been the corner stone of semiconductor devices for years. Moores law motivates the technology
scaling in order to improve performance such as power consumption, speed, area. The challenges arise because of reduced size of
transistor, operation at low voltage, read assist, write assist, and retention failures. Now, it is becoming common to work on read
and write assist techniques to have robust operation at lower supply voltages. Analysis suggest, negative bit line write assist
technique seem most prominent at lower supply voltages. Understanding trade-offs in terms of area, performance is crucial to
choose the best write assist technique in nano-scale SRAM to have robust low voltage operation.
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