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CMPEN 411

VLSI Di
Digital
it l Circuits
Ci
it
Spring 2011
Lecture 12: Logical Effort

[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003


J. Rabaey, A. Chandrakasan, B. Nikolic]

Sp11 CMPEN 411 L12 S.1

PMOS/NMOS Ratio Effects


5 x 10

-11

= (W/Lp)/(W/Ln)
tpLH

4.5

tpHL

of 2.4 (= 31 k/13 k)
gives symmetrical
response

tp

of 1.6
1 6 to 1
1.9
9 gi
gives
es
optimal performance

3
3.5

3
1

= (W/Lp)/(W/Ln)

Sp11 CMPEN 411 L12 S.2

Example of Inverter Chain Sizing


In

Out
Cg,1

1
CL = 8 Cg,1

CL/Cg,1 has to be evenly distributed over N = 3 inverters


F = CL/Cg,1 = 8/1
f =

Sp11 CMPEN 411 L12 S.3

Heads up

This lecture
z

Logical Effort
- Reading assignment textbook pp251-257, and handout

Next lecture
z

Designing energy efficient logic


- Reading
R di assignment
i
Rabaey,
R b
et al,
l 5.5 & 6
6.2.1
21

Sp11 CMPEN 411 L12 S.4

History

First proposed by Ivan Sutherland and Bob Sproull in


1991
z
z

Logical Effort: Designing for Speed on the back of an


Envelope, IEEE Advanced Research in VLSI, 1991
Both authors are vice president and fellow at Sun
Microsystems

Gain-based synthesis
y
based on Logical
g
effort
z

Implemented in IBMs logic synthesis tool BooleDozer

Also adopted by Magmas logic synthesis tool

Sp11 CMPEN 411 L12 S.5

Inverter Delay

Divide capacitive load


load, CL, into
z

Cint : intrinsic - diffusion and Miller effect (Cg)

Cext : extrinsic - wiring and fanout

tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint)


=0.69(ReqCint + ReqCext)
z

where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the
gate

Sp11 CMPEN 411 L12 S.6

Logical Effort Delay Model

Delay of logic gate has two components


d=f+p

f: effort delay

p: parasitic delay

Effort delay fg has two components:

f=gh
g: logical effort
h: electrical effort = Cout/ Cin (the ratio of

output capacitance to input capacitance)

Sp11 CMPEN 411 L12 S.7

Gate Delay Components

Cin

Logic
g
Gate

Cout

Split delay of logic gate into three components


Delay = Logical Effort x Electrical Effort + Parasitic Delay

Logical Effort
z Complexity of logic function (Invert, NAND, NOR, etc)
z Define inverter has logical effort = 1
z Depends only on topology not transistor sizing

Electrical Effort
z Ratio of output capacitance to input capacitance Cout/Cin

Parasitic Delay
z Intrinsic delay
z Independent of transistor sizes and output load

Sp11 CMPEN 411 L12 S.8

Computing Logical Effort

g represents the fact that


that, for a given
load, complex gates have to work harder
than an inverter to produce a similar
(speed) response
z

the logical effort of a gate tells how much


worse it is at producing an output current than
an inverter (how much more input
capacitance a gate presents to deliver the
same output current)

Logical effort is the ratio of the input


capacitance of a gate to the input
capacitance
capac
ta ce o
of a
an inverter
e te de
delivering
e g
the same output current
Defined to be 1 for an inverter

Sp11 CMPEN 411 L12 S.9

Computing Logical Effort

Sp11 CMPEN 411 L12 S.10

Logic Gate Delay

Sp11 CMPEN 411 L12 S.11

Logic Gate Delay

Sp11 CMPEN 411 L12 S.12

Example

Estimate
E
ti t the
th delay
d l off an inverter
i
t driving
d i i 4 identical
id ti l
inverter: (FO4)

g=

Sp11 CMPEN 411 L12 S.13

h=

p=

d=

Example

Sp11 CMPEN 411 L12 S.14

Path Delay of Complex Logic Gate Network

T t l path
Total
th delay
d l th
through
h a combinational
bi ti
l llogic
i bl
block
k
tp = dj = pj + hj gj

the minimum
th
i i
d
delay
l th
through
h th
the path
th d
determines
t
i
th
thatt each
h stage
t
should bear the same gate effort
h1g1 = h2g2 = . . . = hNgN

Sp11 CMPEN 411 L12 S.15

Application of Logical Effort

Alternative logic structures, which is the fastest?


F = ABCDEFGH

Sp11 CMPEN 411 L12 S.16

Application of Logical Effort

Alternative logic structures, which is the fastest?


F = ABCDEFGH

g1=10/3 g2=1

1 6/3 g2=5/3
2 /3
g1=6/3
g1=4/3 g2=5/3 g3=4/3 g4=1

Sp11 CMPEN 411 L12 S.17

Review: Design Technique 4

Isolating fan-in
f
f
from
fan-out
f
using buffer
ff insertion

CL

Sp11 CMPEN 411 L12 S.18

CL

Questions

d = gh+p

How to derive the model from Elmore delay model?

Why logical effort g is independent of transistor sizing?

How to calculate parasitic delay p ? Why it is independent of


transistor sizing?

How to calculate single delay parameter:

What if the ratio of p-type to n-type transistor widths changes?

Sp11 CMPEN 411 L12 S.19

From Elmore model to Logical Effort Model


R
Cin

Cp

Cout

Elmore Delay = R(Cp


R(Cp+Cout)
Cout)
= R*Cout + R*Cp
= RCin*(Cout/Cin)+R*Cp

g
Sp11 CMPEN 411 L12 S.20

Parasitic Delay
CgateP

RonP

RonN

CgateN

Sp11 CMPEN 411 L12 S.21

Main cause is drain capacitances

These scale
Th
l with
ith ttransistor
i t width
idth
so it is independent of transistor
sizes

For inverter:

CdrainP

Parasitic Delay ~= 1.0


CdrainN

How to calculate single delay parameter:

Ch
Characterize
t i process speed
d with
ith single
i l d
delay
l parameter:
t

~= 15 ps for 0.18um

~=20 ps for 0.25 um

How to estimate it for a new process? (such as 0.13 or 0.09 um)

Sp11 CMPEN 411 L12 S.22

Inverter Chain Delay

For each stage:

Delay = Logical Effort x Electrical Effort + Parasitic Delay


= 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps)
= 2.0 units

Sp11 CMPEN 411 L12 S.23

Multistage Logic Network

Path

logical effort, G = gi

Path

electrical effort, H = Cout/Cin

Parasitic
P
iti
Path
D=
D

d
delay,
l
P = pi

effort, F= fi = gi hi

F+P

Sp11 CMPEN 411 L12 S.24

(gi = L.E. stage i)


(hi = E.E. stage i)
( i = P.D.
(p
P D stage
t
i)

Paths that Branch

C
Consider
paths that branch:

GH

h1

h2

= GH?

Sp11 CMPEN 411 L12 S.25

15

90

5
15

90

Paths that Branch

No! Consider
C
paths that branch:

=1

= 90 / 5 = 18

GH

= 18

h1

= (15 +15) / 5 = 6

h2

= 90 / 15 = 6

= g1g2h1h2 = 36 = 2GH

Sp11 CMPEN 411 L12 S.26

15

90

5
15

90

Add Branching Effort


Branching effort:
b=

Sp11 CMPEN 411 L12 S.27

Con path + Coff path


Con path

Multistage Networks
Path electrical effort: H= Cout/Cin
Path logical effort: G = g1g2g
gN
Branching effort: B = b1b2bN
P th effort:
Path
ff t F=
F GBH
Path delay D = F+P=GBH+P

Sp11 CMPEN 411 L12 S.28

Optimal Number of Stages


Cin
Coutt

Minimum delay when:


stage effort = logical effort x electrical effort = 3
3.4-3.8
4-3 8 ~ 4

Fan-out-of-four (FO4) is convenient design size (~5)

FO4 delay: Delay of


inverter driving four
copies of itself

Sp11 CMPEN 411 L12 S.29

Method of Logical Effort

C
Compute
the path effort:
ff
F = GBH
G

Find the best number of stages N ~ log4 F

Compute the stage effort f = F1/N

Sketch the p
path with this number of stages
g

Work either from either end, find sizes:


Cin = Cout*g/f

Sp11 CMPEN 411 L12 S.30

Example of Inverter (Buffer) Staging


1
Cg,1 = 1

Cg,1 = 1
16

Cg,1 = 1
1

tp

64

65

18

15

2.8

15.3

CL = 64 Cg,1
4

CL = 64 Cg,1
8

2.8

Cg,1 = 1

Sp11 CMPEN 411 L12 S.31

CL = 64 Cg,1
8

22.6
CL = 64 Cg,1

Summary

Sp11 CMPEN 411 L12 S.32

Next Lecture and Reminders

Next lecture
z

Designing energy efficient logic


- Reading assignment Rabaey, et al, 5.5 & 6.2.1

Sp11 CMPEN 411 L12 S.33

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