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10 9 8 7 6 5 4 3 2 1
ISBN13: 978-0-13-508443-4
ISBN10: 0-13-508443-1
8.
9.
(a) Hex: 30, 31, 32 , 33, 34, 35, 36, 37, 38, 39
(b) Binary: 11 0000, 11 0001, 11 0010, 11 0011, 11 0100, 11 0101, 11 0110, 11 0111,
11 1000, 11 1001.
ASCII (hex) Binary
30
011 0000
31
011 0001
32
011 0010
33
011 0011
34
011 0100
35
011 0101
36
011 0110
37
011 0111
38
011 1000
39
011 1001
0
1
2
3
4
5
6
7
8
9
10.
000000 22 55 2E 53 2E 41 2E 20 69 73 20 61 20 63 6F 75
000010 6E 74 72 79 22 0D 0A 22 69 6E 20 4E 6F 72 74 68
000020 20 41 6D 65 72 69 63 61 22 0D 0A
4
6
C
12.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
1
1
1
1
1
1
"U.S.A. is a cou
ntry".."in North
America"..
13.
4
6
C
14.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
0
0
0
0
0
0
1
15.
A
4
6
C
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
0
1
1
0
1
0
0
1
16.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
1
1
1
1
1
1
1
0
17.
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
1
0
0
0
0
0
0
0
D
X
0
1
Q
NC
0
1
18.
LSB
19.
LSB
20.
CLK
No
Yes
Yes
(a) 4
(b) 4
(c) 4
(d) 1 048 576, 220
(e) 1024K
(f) 1 073 741 824, 230
(g) 1 048 576 K
(h) 1024M
(i) 8388608, 8192K
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
1 million pages
The storage of the chip is measured in Megabits while the Computer memory is measured
in Megabytes.
True, the more address lines the more memory locations.
True, the memory location size is fixed.
True, the more data lines the more memory locations
True
access time
True
electrically erasable
True
DRAM
SRAM
DRAM and SRAM
(c)
(c)
(a) 32Kx8, 256K
(f) 8Kx1, 8K
(b) 8Kx8, 64K
(g) 4Kx8, 32K
(c) 4Kx8, 32K
(h) 2Kx8, 16K
(d) 8Kx8, 64K
(i) 256Kx4, 1M
(e) 4Mx1, 4M
(j) 64Kx8, 512K
(a) 128K 14 8
(f) 256K 8 4
(b) 256K 15 8
(g) 8M 20 8
(c) 512K 16 8
(h) 16M 11 4
(d) 2M 18 8
(i) 512K 16 8
(e) 512K 16 8
42.
43.
44.
45.
A0
A11
A12
1
3
A13
46.
47.
~CS
A12
8kx8
U?
A13
A14
A15
Vcc
1
2
3
6
4
5
A
B
C
G1
G2AN
G2BN
Y0N
Y1N
Y2N
Y3N
Y4N
Y5N
Y6N
Y7N
15
14
13
12
11
10
9
7
~CS
74138
48.
49.
A14
32kx8
U?
A15
A16
A17
Vcc
1
2
3
6
4
5
A
B
C
G1
G2AN
G2BN
Y0N
Y1N
Y2N
Y3N
Y4N
Y5N
Y6N
Y7N
15
14
13
12
11
10
9
7
~CS
74138
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
62. The following circuit shows an output circuit for Figure 0-30.
74LS373
D0
Q0
System
Data Bus
To LEDs
A0
D7
Q7
A15
63.
OC
System
address
bus
WR
D0
Switches
A0
D4
To system
Data Bus
D7
Q7
G1
System
Address
Bus
A15
Q0
RD
G2
28.
29.
30.
10
4096 bytes
128 bytes
2 timers
256 bytes
8031
32 pins
1 serial port
UV-EPROM
EEPROM
NV-RAM
Flash
(a) 4K ROM, 128 Bytes of RAM
(b) 16K ROM, 256 Bytes RAM
(c) 32K ROM, 256 Bytes RAM
The OTP version of the 8051
The 8031 does not have on-chip ROM.
DS89C420/430 are the best for home development, because you can program it serially
using IBM PC.
8
8
8
DPTR or PC (program counter)
Necessary
28H, A
(a), (d), (f), and (g)
(a), (c), (d), (f), and (g)
44H, A
1EH, A
Low, high
Assembly language
Assembler program
True
List file
False
True
No
They are not real code (real code produces op code). Pseudo-instructions only give
instruction to the assembler and does not generate opcodes.
True
Section 2.4: The Program Counter and ROM Space in the 8051
21.
22.
23.
0000H
It executes whatever is at location 0000h which could be garbage in this case.
(a) 2 bytes
(b) 2 bytes
(c) 1 byte
(d) 2 bytes
(e) 1 byte
(f) 1byte
(g) 1 byte
11
24.
0000
0000
0002
0004
0006
0007
0008
000A
000C
7D25
7F34
7400
2D
2F
2412
80FE
25.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
26.
27.
28.
0000h, FFFFh
32K
1K
ORG 0h
MOV R5, #25h
MOV R7, #34h
MOV A, #0
ADD A, R5
ADD A, R7
ADD A, #12h
HERE: SJMP HERE
END
3FFFh (16K)
1FFFh (8K)
7FFFh (32K)
1FFFh (8K)
0FFFh (4K)
0FFFh (4K)
FFFFh (64K)
45617274
68
3938372D
3635
47414245
48203938
1
2
ORG 200H
MYDATA_1:
DB "Earth"
MYDATA_2:
DB "987-65"
MYDATA_3:
DB "GABEH 98"
5
6
END
1
2
ORG 340H
DAT_1: DB 22,56H,10011001B,32,0F6H,11111011B
END
30.
0340
0340
0344
16569920
F6FB
12
8
D7, D6
D2, D0
when there is a carry from D7
when there is a carry from D3 to D4
CY = 1
(a) CY = 1
(b) CY = 0
(c) CY = 0
38.
ORG 0H
MOV R0, #5
MOV A, #0
HERE:
ADD A, #55h
DJNZ R0, HERE
END
46.
47.
48.
D3, D4
08
Bank 1
8 Bits
Bank 0
Bank 0:00h-07h, Bank 1: 08h-0Fh, Bank 2: 10h-17h, Bank 3: 18h-1Fh
(a) RAM Location 04
(b) RAM Location 00
(c) RAM Location 07
(d) RAM Location 05
(a) RAM Location 14h
(b) RAM Location 10h
(c) RAM Location 17h
(d) RAM Location 15h
SETB PSW.4
INSTRUCTION
ORG
MOV
MOV
MOV
0
R0,#66H
R3,#7FH
R7,#5DH
Contents of
the Stack
?
?
66H
7FH
13
PUSH
PUSH
PUSH
CLR
MOV
MOV
POP
POP
POP
49.
NO,
0
3
7
A
R3,A
R7,A
3
7
0
09H
0AH
0AH
0AH
0AH
0AH
09H
08H
07H
5DH
5DH
5DH
5DH
5DH
5DH
7FH
66H
7FH
Contents of
the Stack
?
?
?
?
?
66H
7FH
5DH
5DH
5DH
5DH
7FH
66H
?
pop 7
pop 3
pop 0
50.
INSTRUCTION
ORG
MOV
MOV
MOV
MOV
PUSH
PUSH
PUSH
CLR
MOV
MOV
POP
POP
POP
0
SP,#70H
R5,#66H
R2,#7FH
R7,#5DH
5
2
7
A
R2,A
R7,A
7
2
5
14
RISC stands for "Reduced Instruction Set Computer". CISC stands for "Complex (or
Complete) Instruction Set Computer".
CISC
RISC
RISC
CISC
256
the instruction following the jump
PC
short jump, 2
long jump, 3
less ROM space is consumed
True
False
c, LJMP is not a short jump.
2, because it can only go 128 to 127 bytes in the program
True
MOV R6, #10
BACK: MOV R5, #100
HERE: DJNZ R5, HERE
DJNZ R6, BACK
13.
MOV R6, #10
BACK: MOV R5, #100
AGAIN:MOV R4, #100
HERE: DJNZ R4, HERE
DJNZ R5, AGAIN
DJNZ R6, BACK
14.
15.
16.
20,000
128
127
3
2
2K
64K
2 bytes
2 bytes
15
23.
24.
25.
26.
They need to be equal (in order for the stack to remain unchanged) so that when the RET
instruction is executed it goes back to place where it originated; otherwise, it returns to a
wrong place.
When POP is executed, the contents of the stack are copied to the destination register and
SP is decremented by one.
SP
Stack content
09
(00)
08
(0E)
SP
Stack content
0B
(67)
0A
(99)
09
(02)
08
(0B)
16
10 MHz
0.667 s
1 s
0.480 s
True, both instructions take 2 machine cycles to execute.
813.75 s
750 s
((4 x 250) x (200 x 100)) x 1.085 s = 21.7 seconds
(250 x 150) x 5 x 0.75 s = 140625 s
Duration of each machine cycle: 1/(11.0592MHz) = 90.422 ns
Number of machine cycles: (1 + 1 + 1 + 4) x 150 x 90.422ns = 94.944 s
1 / 16MHz = 62.5 ns
(1+1+1+4) x 200 x 62.5 ns = 87.5s
(1+1+4) x 250 x 200 x 100 x 90.422 ns = 2.713 seconds
(7 x 250) x 150 x 62.5 ns = 16.406 ms
Although the period of each machine cycle is twelve times shorter in DS89C420/30, the
fact that the execution of many instructions take more number of machine cycles than in
AT89C51, does not allow the performance to become twelve times faster in
DS89C420/30. As an example, if you divide the answer of Problem 35 by the answer of
Problem 39, we can figure out that in this particular case, DS89C420/30 is almost 8.6
times faster than AT89C51, not 12 times faster.
40
Pins 40, 20 are assigned to Vcc and Gnd, respectively.
32
8 Pins, 39-32, are designated for P0.
8 Pins, 01-08, are designated for P1.
8 Pins, 21-28, are designated for P2.
8 Pins, 10-17, are designated for P3.
output
P0
P1
ORG 0000h
MOV A, #0FFH
MOV P1, A
MOV A, P1
MOV P0, A
MOV P2, A
MOV P3, A
HERE: SJMP HERE
END
12.
ORG 0000h
MOV A, #0FFH
MOV P2, A
MOV A, P2
MOV P0, A
MOV P1, A
HERE: SJMP HERE
END
13.
14.
10 and 11
0000h; This means that the starting of the code must begin at location 0000h. In other
words it belongs to code ROM.
17
15.
(a)
(b)
ORG 0000h
AGAIN:
MOV A, #55h
MOV P1, A
MOV P2, A
ACALL DELAY
MOV A, #0AAh
MOV P1, A
MOV P2, A
ACALL DELAY
SJMP AGAIN
ORG 0000h
MOV A, #55h
AGAIN:
MOV P1, A
MOV P2, A
ACALL DELAY
CPL A
SJMP AGAIN
END
END
18
21.
ORG 0000h
AGAIN:
SETB P1.3
SETB P1.7
SETB P2.5
ACALL DELAY
CLR P1.3
CLR P1.7
CLR P2.5
ACALL DELAY
SJMP AGAIN
END
22.
ORG 0000h
SETB P1.3
AGAIN:
JNB P1.3, AGAIN
MOV A, #55h
MOV P2, A
HERE: SJMP HERE
END
23.
ORG 0000h
SETB P1.3
AGAIN:
JB P1.3, AGAIN
HERE:
MOV A, #55h
MOV P0, A
ACALL DELAY
MOV A, #0AAh
MOV P0, A
ACALL DELAY
SJMP HERE
END
19
24.
ORG 0000h
SETB
AGAIN:
JB
MOV
MOV
SJMP
HERE:
MOV
MOV
SJMP
END
P2.0
P2.0, HERE
A, #66H
P1, A
AGAIN
A, #99H
P1, A
AGAIN
25.
ORG 0000h
SETB P1.5
AGAIN:
JNB P1.5, AGAIN
CLR P1.3
SETB P1.3
CLR P1.3
26.
ORG 0000h
SETB P1.3
AGAIN:
JB
P1.3, HERE
CLR P1.4
SJMP AGAIN
HERE: SETB P1.4
SJMP AGAIN
END
27.
20
28.
ORG
0000H
SETB P1.7
SETB P1.6
AGAIN:
JB
P1.7, HERE
CLR P1.0
SJMP NEXT
HERE:
SETB P1.0
NEXT:
JB
P1.6, COPY
CLR P1.7
SJMP AGAIN
COPY:
SETB P1.7
SJMP AGAIN
END
21