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OCSNM1/RMCSM1 Data Communication &

Network Principles Section A 4


Serial synchronous data transmission
Clock encoding and extraction
Character oriented synchronous transmission
Bit oriented synchronous transmission

Synchronous data transmission


The receiver clock runs synchronously with
the transmit clock. How is this achieved?
(a) By encoding the clock with the data

Relevant section to read in Stallingss book:


6.1
Relevant section to read in Halsalls book:
3.3
Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 1

Clock encoding techniques (1)


Bipolar encoding
This is an RZ (Return to Zero) signal. Easy
to recover clock but has a disadvantage.

(Halsall Fig 3.8a)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

(Halsall Fig 3.7a)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 2

Clock encoding techniques (2)


Manchester encoding
Used for Ethernet LANs.
How is it decoded?
What is a disadvantage of Manchester encoding?

(Halsall Fig 3.8b)

Section A 4, Page 3

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 4

(b) Clock recovery techniques NRZI - Non-Return to Zero (Invert)

Principle of clock recovery from NRZI data


using a DPLL

NRZI encoding does not encode the clock but


allows the clock to be recovered from the data
using a Digital Phase-Locked Loop (DPLL)

What limitations are imposed on the content


of an NRZ data stream before NRZI
encoding?

(Halsall Fig 3.9a)

How is NRZI
encoded?
What advantage does
it offer compared to
Manchester
encoding?

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 5

DPLL waveforms

(Halsall Fig 3.9b)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 6

Some 3 level data encoding formats

DPLL must synchronise (lock) initially,


then only minor phase adjustments are
required

(Halsall Fig 3.9c)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

(Halsall Fig 3.10a)

Section A 4, Page 7

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 8

3 level and 4 level data encoding formats

Synchronous transmission general principle of data framing

4B3T or 2B1Q may be used for line


transmission in ISDN access circuits

(Halsall Fig 3.4)

(Halsall Fig 3.10b)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 9

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 10

Character-oriented synchronous transmission IBM BISYNC (BSC)

Character-oriented synchronous transmission character synchronisation

With no start and stop bits, how does the


receiver find character or byte boundaries?
What happens when there is no data to send?

SYN is a control character (ASCII 0x16)


that allows character sync. to be achieved

(Halsall Fig 3.12b)

(Halsall Fig 3.12a)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 11

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 12

Bit-oriented synchronous transmission as used


in SDLC & HDLC (1)

Bit-oriented synchronous transmission as used


in SDLC & HDLC (2)

Bit-oriented synchronous protocols have


superseded obsolete character-oriented
synchronous protocols such as IBM Bisync
In a Bit Oriented Protocol, the frame contents can
be any number of bits, between certain limits. It
does not need to be a multiple of 8 bits.
A special Flag sequence at the start and end of
each frame, achieves frame synchronisation.
The flag sequence is never allowed to appear in
the actual frame contents.

The receiver hunts for a Flag sequence 01111110 to detect


the start of a frame.
Zero insertion or Bit stuffing provides data transparency

(Halsall Fig 3.13a)

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 13

Data transparency in SDLC & HDLC


When the transmitter is sending the frame contents, if the
original data contains 5 logic 1 bits in succession, an
extra logic 0 bit is always inserted (zero insertion).
While receiving the frame contents, whenever 5 logic 1
bits are followed by a 0, the 0 bit is removed (zero
deletion).
This not only achieves data transparency but it also
ensures that there are not normally more than 6 logic 1
bits in succession (flag pattern) anywhere in an
SDLC/HDLC frame (unless the abort pattern is sent).
SDLC/HDLC can be used with NRZI line coding to allow
a bit rate clock to be recovered from the NRZI data stream
at the receiver.
Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 15

Data Comm. & Net. Principles, Ed. 3, D. Lauder

Section A 4, Page 14