IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 03 | September 2016

ISSN (online): 2349-784X

Design and Implementation of High Speed Vedic

Multiplier using Brent Kung Adder on FPGA
Gaurav Raj
M. Tech. Student
Department of Electronics & Communication Engineering
United Institute of Technology, Allahabad, Naini

Depanjan De
Head of Dept.
Department of Electronics & Communication Engineering
United Institute of Technology, Allahabad, Naini

Abstract
This paper presents the design and implementation of high speed Vedic multiplier (Urdhva Tiryagbhyam algorithm) using
parallel prefix adders on Virtex 6 FPGA. Brent kung adder, which is a parallel prefix adder is used for addition of partial
products. Use of Brent kung adder will improve the speed of addition but hardware complexity will increase. A 16-bit and 8-bit
vedic multiplier is designed using Verilog Hardware Description Language and synthesized on XiIlinx Design Suite 14.7 and
simulated using Isim simulator. Compared to existing designs the proposed design is having significant improvement in delay.
The proposed 16-bit/8bit vedic multiplier is having 37% and 32% improvement in delay respectively, compared to an existing
recent design.
Keywords: Vedic Multiplier, Xilinx, FPGA, Full Adder
________________________________________________________________________________________________________
I.

INTRODUCTION

The performance of a processor is mainly determined by its speed. In arithmetic operations, multiplication is an important
fundamental function. Some of the important digital signal processing (DSP) applications such as filtering, convolution Fast
Fourier Transform (FFT) etc. and arithmetic functions such as inner products, multiply and accumulate (MAC) unit, frequently
use operations based on multiplication [1]. In digital image processing systems multiplier is an important unit [2]. In addition to
ALU, multipliers are used in other parts of processor design such as various data path units. For processing acquired signal in
real time applications, high speed processing is an essential requirement. So demand for high speed multiplier circuit with
reduced power consumption has been continuously increasing.
II. BACKGROUND
The requirement of high speed processing demands the development of fast multiplier circuit [7]. A high speed Vedic multiplier
based on Urdhva Triyakbhyam Sutra is proposed in [1]. In this paper multipliers with four, eight, sixteen and thirty two bits are
implemented using Vedic technique and its performance has been compared with conventional method based multiplier which
evidently shows that Vedic multipliers are much faster[l]. For Vedic multipliers with large number of bits, design complexity
reduces due to their hierarchical nature. Reference [7] presents a similar method for hierarchical multiplier design for Urdhva
multiplier wherein 4x4 and 8x8 multipliers are designed using 2x2 multipliers [8]. Comparison of Urdhava and Nikhilam
multipliers is drawn in [4] for various bit multiplications starting from 8x8 bits to 64x64 bits. For small inputs Urdhava
multiplier performs better than Nikhilam multiplier and when size of multiplicand increases, Nikhilam multiplier performs much
faster than Urdhava multiplier. So integrated Vedic multiplier architecture is proposed in [4], which is capable of selecting
appropriate multiplier based on the given inputs. The work presented in [3] focuses on implementation and comparison of array ,
Urdhava and Nikhilam multiplier for 8bits, 16bits and 32 bits. It is observed that the Urdhava multiplier is best among the three.
Currently, the speed of multiplier is limited by the speed of adders used in partial product addition. Performance comparison
of various adders is done in [9]. It is observed that carry save adder is having minimum delay, but among seven adder topologies
carry increment adder has best balance between area and delay. Logic optimization of adders through technology independent
mapping was proposed by R. Uma and P. Dhavachelvan in [lO].The work presents 20 different logical constructions to
implement one bit full adder circuit. From the performance analysis on delay, power dissipation, transistor count etc. it is
observed that full adder with XOR and MUX gives best performance. Full adder with XNOR, NOT and MUX is the second
optimized adder. Reference [II] focuses on the importance of full adder block in a multiplier circuit and therein a full adder
circuit is implemented using two XNOR gates and a MUX. Carry skip adder is used for implementing high speed Urdhava
multiplier in [12]. In [13] MAC unit is designed using Urdhava multiplier with improvement in delay and area. Using Urdhava
multiplier, high speed ALU is designed in [14]. All the above methodologies, mentioned in literature, use various adders for
addition of partial products. But from [9], [10] and [11], it is observed that full adder with multiplexer and XOR gate gives
minimum delay. Therefore the proposed Vedic multiplier, uses MUX based adder for adding the partial products to obtain
minimum delay.

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Design and Implementation of High Speed Vedic Multiplier using Brent Kung Adder on FPGA
(IJSTE/ Volume 3 / Issue 03 / 013)

III. OBJECTIVE
The main aim of this paper is to design a high speed multiplier. The proposed design integrates the high speed multiplication
features of Urdhva Triyakbhyam Sutra and mux based adders for minimizing delay. Urdhva Triyakbhyam Sutra is used for
generating partial products and mux based adders for adding partial products.
IV. RESULTS
Binary multiplication is an important operation in many high power computing applications and floating point multiplier design
and multiplication is the most time, area and power consuming operation. Applications such as High Power Computing (HPC),
Image processing and Signal processing is based on binary multiplication. Vedic Mathematics provides principles of high speed
multiplication. Urdhva Tiryagbhyam algorithm is the best algorithm for binary multiplication in terms of area and delay. But as
the number of bits increases, delay also increases as the partial products are added in a ripple manner. Thus by the use of faster
adders and better design for the addition of partial products, overall delay of multiplication can be largely reduced. 1. 8x8 Vedic
multiplier Compared to 8x8 vedic multiplier designed in base paper, a new architecture having three 8-bit brent kung adders is
designed.
8x8 Vedic Multiplier

Fig. 1: Conventional Design

Fig. 2: Modified Design for 8 bit Multiplier

Table 1
Comparison Results
Multipliers
Delay (in ns)
No. of slices
base paper 8 bit
9.130
107 out of 46560
modified 8-bit
6.176
104 out of 46560

Fig. 3: Synthesis Results

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Design and Implementation of High Speed Vedic Multiplier using Brent Kung Adder on FPGA
(IJSTE/ Volume 3 / Issue 03 / 013)

16x16 Vedic multiplier

Compared to 16x16 Vedic multiplier designed in base paper, a new architecture having three 16-bit brent kung adders is
designed.

Fig. 4: Conventional 16 bit Vedic Multiplier

Fig. 5: Modified 16 bit Vedic Multiplier

Table - 2
Comparison Results
Multipliers
Delay (in ns)
No. of slices
base paper 16 bit
16.994
594 out of 46560
modified 16-bit
10.548
490 out of 46560

Fig. 6: Synthesis Results

V. CONCLUSION
A High speed Vedic Multiplier has been designed using Verilog HDL, synthesized using Xilinx Design Suite 14.7 and
implemented on Virtex 6 FPGA. Urdhva Tiryagbhyam algorithm is used for multiplication and Brent Kung parallel prefix adder
is used for addition of partial products. The proposed design for 16 bit vedic multiplier yields 37% and 8 bit yields 32 %
improvement in delay respectively.
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Ch. Harish Kumar, "Implementation and Analysis of Power, Area and Delay of Array, Urdhva, Nikhilam Vedic Multipliers", International Journal of
Scientific and Research Publications, Volume 3, Issue I, January 2013

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Design and Implementation of High Speed Vedic Multiplier using Brent Kung Adder on FPGA
(IJSTE/ Volume 3 / Issue 03 / 013)
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