| { | | cmmicrmcencnccemaie Chapter 11 ss#=sesesasn Layout of Analog and Mixed Analog-Digital Circuits Franco Maloberti Department of Electronics, University of Pavia - 27100 Pavia, aly 1. Introduction In many of the chapters of this book, theoretical considerations of the design of analog circuits, data converters and mixed analog-digital systems have been discussed. The design flow consists of the following steps after theoretical ‘analysis: logic, electrical simulation and verification and finally the translation of results into the physical description (and physical verification) of the system its layout. It is well known that designing a layout is a tedious and error prone task. Thus, in order to avoid trivial work and to reduce the possibility of (human) error, convienient CAD tools for automatic, error-free layout generation have been introduced, For the design of digital circuits, where an extremely large number of transistors is very common, the use of such CAD tools is mandatory. However, the principles on which these tools are based do not coincide with the design strategies that should be used for analog or mixed analog- silicon the effect is also unisotropic: the pressure induces variations of the electrical properties in a different way in the two orthogonal directions; the unisotropy has a minimum in the 45°direction. Because of this minimum, 45° is often the preferred orientation of resistors designed with monocristalline layers in <100> silicon.Franco Maloberti 351 Well Substrate bias Fig. 10: Layout of resistor realized by well diffusion. 6. Layout of Capacitors Capacitors are achieved in MOS technology by using diffusion, polysilicon or metal as plates and silicon oxide or polysilicon oxide as dielectric. The structures correspond to a parallel-plate element with capacitance given by: c= me 4 o €9 is, as known, the absolute dielectric constant. Relative dielectric constant (¢,), the area of the plates (A) and the oxide thickness (t,,) are the main parameters controlling the capacitor value. However, second-order effects must be taken into account when precise capacitors have to be designed. These effects are related to fabrication inaccuracies and to the fringing effects at the boundary of the structures, Fabrication inaccuracies can give rise to errors in oxide thickness. When this error corresponds to a gradient, its first-order effect is cancelled by matched elements that are arranged in a common centroid fashion. Fig. 11 shows the layout of two capacitors (C, and C,) that need to be equal. The two capacitors are split into eight equal parts that are connected in parallel. This arrangement guarantees that a gradient in the oxide thickness either in the x or y direction does not affect the capacitor matching, [7] Another significant limititation which is due to fabrication steps is the undercut effect. A capacitor is a parallel-plate structure with the upper one normally smaller than the lower one. The area of the smaller plate is assumed to be that of the capacitor. However, because of the undercut effect the actual352 Layout of Analog and Mixed Analog-Digital Circuits area is smaller than the designed one. If the plate is a rectangle with designed sides a and b, with an undercut x, the actual area A’ is smaller than the designed A: A'S A. 2x(a+b) = A-xP @ / ai ae iL POL Fig, 11: Layout of two matched capacitors (common centroid structure). ‘The resulting reduction is proportional to the perimeters of the plate. It follows that in order to get the same proportional reduction in matched capacitors they should have the same area-perimeter ratio. This condition can easily be fulfilled in matched capacitances whose ratio must be a rational number. Equal “unit” capacitances connected in parailel can do the job; equal elements, of course have the same area-perimeter ratio. For non-integer ratios, the following strategy is usually used: a number of unit capacitors are connected in parallel with the addition of a rectangular clement, which value ranges from 1 to 2 unit capacitances (Fig. 12). Some technologies allow use of a contact poly 2-metal even in the thin oxide region where poly 1 overlaps poly 2. In this case the layout is more efficient, as shown in Fig, 12 b.Franco Maloberti 353 UNITY. CAPACITOR PoLY2 we, POLY + POLY 2 POLY! (b) Fig, 12: Layout of a non-integer multiple of unity capacitance; a) poly interconnection of the top plates; b) metal interconnection of the top plates. In order to limit the boundary-dependent errors, rounded or 45° corners are used. When the contact on the thin oxide area is not allowed by the technology (there is the risk of faliure), plate endings for exiting the thin oxide area must be used. Furthermore these poly endings should match. For precise applications even the contribution of parasitics of the metal lines used for interconnections is important. The capacitors should be designed in such a way that the parasitic capacitances are minimized and matched. It is not possible to concentrate the above considerations, illustrated in Fig. 13, into standard design rules. However, the awareness of the multiplicity of these practical problems will stimulate one to think about an optimum layout solution.354 Layout of Analog and Mixed Analog-Digital Circuits a) Common centroid ) Dummy pol? strips 6) Contact on top of thick oxide 4) Matched pole terminals '€) Matched metal lines f) Protective well 9) Well multiple biased Fig. 13: Two matched capacitors lid out accordingly to some analog tricks. Finally, it is worth mentioning a fundamental limitation on the capacitor accuracy. This comes from fringing effects. Equation (1) is valid under the assumption that the electric field between the two plates of the capacitor is uniform. In reality, at the boundary of the plates the electric field is not uniform and its fringing causes an intrinsic error in the use of equation (1). Since the fringing depends not only on the voltage of the two plates but also on the voltage of nearby conductors, its effect cannot be quantified. However, this contribuion to capacitor inaccuracy is proportional to the ratios t,,/W and t,,/L. If these ratios are smaller than 1/500 the effect becomes negligible compared to those resulting from fabrication-associated errors. 7. Stacked Layout for Analog Cells The advantages of using stacks of transistors have already been discussed. They involve reducing the parasitic capacitance of the source-substrate and drain- substrate junctions and have the advantage of saving area because they allow the sharing of the same contact space (for the source or drain). Moreover, the use of elements with the same orientation improves the matching and also reduces the effects of physical parameter gradients by allowing the use of interdigitized structures. This section considers a generalization of the stacked technique applied to analog building blocks. It is evident that the most efficient situation is the design of a stack with elements that have the same width, considering that the length of the stacked transistors is not very important. To get an idea of the topological degrees of freedom, it is worthwhile noting that, if a transistor is made of an even numberFranco Maloberti 355 of parts, its stacked representation will have its source connection (or the drain) on both sides of the stack; by contrast, when an odd number of elementary components are used, the source is on one side of the stack and the drain is on the other. Thus, depending on the number of parts in which a transistor is divided both source and drain or same terminal can be made available at the ending of the stack. If different transistors have sources or drains connected to the same electrical node they can be combined in the same stack in order to share the area corresponding to the common node. For this it is necessary that elements with equal width, whether they are single transistors or part of them, are combined into a single stack. Advantages in active area and junction capacitance reduction will result. Fig. 14 shows an example where four transistors (part of a telescopic folded-cascode op-amp) are designed on the same stack. Since the width of the transistors is an integer multiple of 40 um, they are split into a number of parts 40 um wide. The two transistors M; and My are also interdigitized in order to get good matching. The sources of My and M, partially share the same contact area (node 1 and 2) with the drains of M, and M3. Le Gena an Sl Ss is Fig. 14: Schematic and stacked layout of four n-channel transistors. When designing an analog cell, simply changing the dimensions of a few transistors can lead to a very critical situation, whereas by contrast many other elements can, within limits, have a range of dimensions without significantly affecting the performance of the circuit. In order to achieve a well-designed layout, it is often worth changing the dimension of non-critical transistors (layout oriented design technique) in such a way that the dimensions fit the requirements of the stacked arrangement. The layout of an analog cell can be organized as the interconnection of superimposed or side by side stacks; all the stacks should be made of elements which have equal width and a topological symmetry that corresponds to the electrical symmetry [8] ee ee ee Stet et356 Layout of Analog and Mixed Analog-Digital Circuits Two examples of a fully stacked layout of a two-stage op-amp and of a folded cascode operational amplifier are given in Fig. 15 and Fig. 16. The arrangement of the transistors is given in the associated schematics. It is interesting to observe that the layout drawn with the suggested approach is compact and regular with a close correspondence between the electrical and physical symmetries. Moreover, all the transistors have the same orientation, ensuring good matching. For the two stage op-amp the compensation capacitor occupies all the empty areas. Only one level of metal is used in the interconnections. If the technology makes more than one level of metal available the extra layers can be used for interconnecting at system level. 8. Digital Noise Coupling In analog circuits that are integrated with digital sections the problem of digital noise coupling and the techniques for its avoidance are very important issues. The sources of digital noise coupling are: = capacitive couplings = couplings through the power supply = couplings through the substrate Capacitive coupling is mainly originated by analog lines which are routed parallel to the digital buses. Even if the transversal coupling of metal lines (or metal and poly lines) is very weak its effect becomes substantial when two paths are running parallel for a long distance. This situation is typical when reference voltages and clock signals must be delivered to a distant analog block, or, when for shielding purposes the analog Viyp (or Ves) is used to bias a shielding ring that is placed close to another shielding ring which in tum is biased by a digital power supply. In such cases the noise protection given by the shielding can be Eliminated by the capacitive coupling between the analog and the digital lines. ‘Another source of capacitive coupling is crossing. Generally digital signals are run as a bus with a lot of lines. It follows therefore that a crossing can often mean interaction with a lot of noisy sources. This kind of coupling is critical when the analog line is connected to the virtual ground of an operational amplifier. The collected noise is directly integrated into the feedback element and is made available at a low impedance nodeFranco Maloberti 37 Mal c a | ci © Fig. 15: a) Schematic of a two stages op-amp; b) transistor’s arrangement; c) stacked layout358 Layout of Analog and Mixed Analog-Digital Circuits (a) aa GBM EGS) i 2h ela aren TEL SETS nt ea Hoey eT (b) Fig. 16: a) Schematic of a folded cascode op-amp; b) Transistor’s arrangement; ©) Stacked layoutee | Franco Maloberti 359 In switched capacitor circuits, crossing between analog lines and docks is often unavoidable. A typical layout of complementary switches is shown in Fig, 17 [9]. It should be noted that the metal used to interconnect the n-channel and the p- channel transistor must cross the digital phase driving the gate of the transistors that are placed in the well. Fig. 17: a) Layout of a minimum area complementary toggle switch; b) layout for large W/L. ratio. The reduction of noise injection due to capacitive coupling often is achieved from a simple awareness of the problem. A suitable placement and routing allows us to limit its effect. When parallel analog and digital lines (which should be kept as short as possible) are really necessary, they can be decoupled by using an appropiately large distance in between and, if necessary, by putting a grounded line (horizontal shielding) between the two critical paths. Another important source of digital noise are power supply connections. An integrated circuit usually employs the same pins for both the analog and the digital biasing. Moreover the circuit is connected to the external world by a pad, a wire bonding and a pin. After the pad, a common analog and digital biasing line runs for a while before there is a definite splitting of the analog biasing network and the digital biasing network. This situation is described by the equivalent circuit shown in Fig. 18. In general, the current in the analog part of the circuit is constant or slightly varying in time; by contrast, the current flowing in the digital section is made up of sharp pulses, almost synchronous360 Layout of Analog and Mixed Analog-Digital Circuits with the clock. The current pulses are necessary to charge or discharge the parasitic capacitance of the nodes driven from one logit sate to. the Fomplementary one. The amplitude of the pulses is dominated Py the switching of digital output drivers, since they are required to actuate external loads that are typically a capacitance of 100 pF (in series with the bonding inductance). determines a voltage drop aV due to the The bias current (analog and digital) importantly to the inductance of the resistance of the connection, and more bonding. Pin [bet Digital section ; Rh LA\AH — Analog section ce \ analog Fig. 18: Equivaten circuit ofthe bias connection ina mixed A/D circuit, AV = Rl + Rolaaog +E @ ‘asa rule of thumb, the typical inductance of a bonding connection is around ‘8 frum Thus, for usual bondings, it can range from 3 to 10 nfl. Moreove’, TnHlatfional contribution of capacitance and inductance of frame and pin aie at aigo be taken into account. The resulting inductance is such that the soe ltage can be as large as tens or hundreds of mY”. Table 4 shows (yPicl oeuing loads for duakin-lne (DIL) and chip-carrer (CC) 40-pin packages ‘Table 4: Parasitic inductances and capacitances in packages. I ton | cm | Ho | cco HCO [int pin 0 | 25 pF | 150H i 10 pF 3a [pins pin 36 | 15 pF ant | 13pF nH [pin 10, pin 31 {ee 0.7 pF 4nH 1.0 pF 3 nH [pmatpinnt| 250 oaFranco Maloberti 361 The drop voltage expressed by (3) (usually referred to as ground or Vpp bouncing) gives rise to an effect equivalent to a power supply noise. This noise has high frequency components; in the analog section it must be rejected by proper power supply rejection ratios (PSRR). Unfortunately PSRR is quite poor at high frequencies. Therefore it is very important to reduce the generation of the power supply noise. In general this is achieved by suitable bonding and biasing strategies that refer to the following general rules: - Firstly, it is advisable to keep as separate as possible the analog from the digital biasing networks. They should merge only very close to the pad. ~ Secondly, when possible, it is recommended to use separate pads for the analog and digital section with relative bonding (eventually multiple-ones) to the same pin (Fig. 19). In such a case the inductance of the analog bonding acts as a filtering element. Pad Pin Li Digital DONT Digital section Le R, | digital Analog section lot ii Pad Ry | analog Analog Fig. 19; Equivalent circuit of bias conncetion with separate bonding. - Thirdly, when extra pins are available, separate pins for the analog and the digital bias should be used. Such a complete separation in the biasing of the two sections gives evident advantages in terms of noise limitation, even if special care must be paid to substrate biasing. A delay in the substrate biasing (because of a delayed biasing of the analog or digital supply) can determine latch-up. - Fourthly, it is always suggested to choose for bias connections the pins that are in the middle of the frame. These result in the minimum parasitic inductance. Another important source of noise is the coupling through the substrate. Output digital drivers very often employ transistors with a huge W/L aspect ratio since they must actuate large external capacitances. The drain diffused areas are consequently large and big capacitive couplings with the substrate results (because of the drain-substrate junction). When the driver switches from one logic state to the complementary state the output node exhibits a fast excursion with a resulting capacitive current. Moreover, during switching, high362 Layout of Analog and Mixed Analog-Digital Circuits current flow can result in impact ionization in the drain area (hot carrier effects) with a resulting substrate current. The relatively high specific resistance of the substrate establishes a considerable amount of noise voltage even for an extremely low avalanche current. The noise coming from the substrate can be limited either by reducing the noise injection or by using shielding strategies. In turn, the noise injected can be reduced by limiting the couplings with the substrate and by special care in the design of digital output drivers. They, in particular, should control the derivative of the output current in order to limit the inductance-dependent drop voltage component. Fig. 20: Example of layout with well protection strategy. Another method of reducing the substrate noise is to use suitable shields for intercepting the substrate noise and draining it towards non-critical nodes. Shielding can be achieved by plates or by rings. A typical plate shield is a well diffusion put under a capacitor array or under a critical metal line. In order to have real shielding (and non-noise collecting) the plate must be carefully biased and connected to a quiet, low-impedance node. Shielding can even be achieved by using the circuit itself or the wells inside which part of the circuit is integrated. For example, in a digital output driver the layout can be arranged in such a way that results in self-shielding: the transistor inside the well is designed surrounding its complementary transistor (Fig. 20). Shielding rings are typically well rings or substrate-bias rings. Substrate bias offers a low impedance path for the noise currents that are going around the substrate. Wells create a surface barrier along the path of those noisy currents.Franco Maloberti 363 Very often a substrate bias ring and a concentric well placed on the side of the analog circuit are used in order to create a double protection for the analog sections. A very much debated point concerns which voltage is better to bias the shielding rings: analog or digital Vpp or Veg. The use of an analog bias determines a corruption of quiet lines (if a non-negligible current must be collected); by contrast, the use of a digital bias reduces the efficiency of the shielding, The decision is often decided on by the specific situation. However very often the digital biases are preferred. 9. Floor Planning of Mixed Analog-Digital Blocks A typical mixed analog-digital block typically contains in the analog section an input signal conditioner, a continuous time or a switched capacitor filter and, eventually, data converters. These analog blocks are made up by active analog cells (operational amplifiers or comparators), passive components (resistors or capacitors) and switches. Moreover, very often a specific digital logic constitutes an essential part of the block (for example, the generator of the disoverlapped phases). The design of the layout of active and passive components must be oriented by analog system requirement. For example, if operational amplifiers must be placed side to side, it is worthwhile to use only one bias block. In this case, the biasing lines in the layout of the op-amp should cross the op-amp in a fashion that the connection is automatically established when the cells are placed side to side (Fig. 21). More in general, the input-output connection in the cell must be located in the proper side, in order to minimize the path and crossing of the inter-block routing. Thus, before designing the layout of the components, it is necessary to define the floor pian of the analog block. The general of reference are: - put the analog critical components as far as possible from the digital elements - make the connections to the critical nodes as short as possible - avoid crossing between the analog biasing lines and digital busses Fig, 22 shows the typical floorplan of a switched capacitor filter. It can be noted that the switches that are the components closer to the digital world are placed on one side of the layout. The operational amplifiers that, by contrast, are the more critical analog elements, are placed on the other side of the layout. The capacitors that are in the middle are usually protected by a well shielding, The crossing of analog bias and signal lines and the digital bus bringing in the switches command is strictly avoided.364 Layout of Analog and Mixed Analog-Digital Circuits IN+ IN- OUT IN| OUT IN+ IN- OUT vpD BIAS CELL. vss pe Fig. 21: Path of bias lines and Vipp - Vss for basic analog cells, Phases Switches Prot. [| Ring aff Capacitor O [| Array iF LI LI Bias cell & Op-AMPs| Fig. 22: Typical floorplan of an $C filter. For a fully differential structure, the floor plan shown in Fig. 23 is normally used. The arrangement utilized for a single ended circuit is made symmetrical around the operational amplifiers. The switches are now at the two sides of the floor plan and the digital busses used to drive them are never crossing and far away from the analog ones.LTT Franco Maloberti 365 [Hi Digital bus Analogue bus Fig. 23: Typical floorplan of a fully differential SC filter. At a more complex level, when many analog and digital sections must be arranged on the same chip, guidelines similar to the ones already mentioned for floor planning of switched capacitor circuits should be used. In addition, it is important to introduce a well-defined physical separation between the analog and the digital circuitry with suitable protections and decoupling, as discussed in Section 8. A special care must be put in the power supply distribution: networks as separated as possible, for the analog and digital section, must be used. These recommendations are resumed in Fig. 24 where a possible floorplan of a mixed analog-digital circuit with protection and power supply distribution is shown.366 Layout of Analog and Mixed Analog-Digital Circuits Analog Oo Oo Guard Rings Section o vob vob Ic Digital Analog vss" Digital O Section Guiput uffers Oo Fig. 24: Typical floorplan of mixed analog digital chip. 10. Concluding Remarks The layout of analog and mixed analog/digital circuits is an important issue for integrated systems. While digital layouts are realized with automatic tools, the physical description of analog blocks is still mainly manual and, generally speaking, requires a specific expertise. The realization of mixed analog/digital circuit must combine results obtained from automatic tools with the results of manual activity. New computer aids for this kind of task will become available in the near future; however, it is necessary to have the knowledge to critically analyze and interactively optimize the solutions proposed by existing and coming CAD tools. 11. References [) SM. Sze (Ed.), VLSI Technology, McGraw-Hill, New York, 1983. 2] Austria Mikro Systeme: AMS Design Rules CMOS Manuals. (] KC. Hsieh, PR. Gray, D. Senderowicz, D.G. Messerschmid, "A low noise chopper stabilized differential switched-capacitor filtering technique," IEEE J. Solid-State Circuits, SC-16, 708-715, 1981Franco Matoberti 367 PR. Gray, R.G. Mayer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, New York. DJ. Allstot, W.C. Black, "Technological design considerations for monolithic MOS switched capacitor filtering systems,” Proceedings of the IEEE, 967-986, 1983. A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, John Wiley & Sons, New York, 1984. J.L. McCreary, P.R. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques,” IEEE J. Solid-State Circuits, SC-10, 371-379, 1975. U, Gatti, F. Maloberti, V. Liberali, "Full stacked layout of analogue cells,” Proc. IEEE Int. Symp. on Circ. and Syst., 1123-1126, 1989. R. Gregorian, G. Temes: Analog MOS Integrated Circuits, John Wiley & Sons, New York, 1986.