Académique Documents
Professionnel Documents
Culture Documents
discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/263469266
CITATIONS
READS
803
1 author:
Mohammad Maadi
University of Alberta
13 PUBLICATIONS 9 CITATIONS
SEE PROFILE
All content following this page was uploaded by Mohammad Maadi on 29 June 2014.
The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the original document
and are linked to publications on ResearchGate, letting you access and read them immediately.
International Journal of Electronics and Electrical Engineering Vol. 3, No. 2, April, 2015
AbstractIn
this
paper,
an
8b/10b
encoding
serializer/deserializer (SerDes) circuit using a DC-balanced,
partitioned block, 8b/10b transmission code was presented.
The information format of this transmission code consists of
packets which are variable in length and can be suitable for
high speed applications. Serializer and deserializer blocks
were designed separately. The serializer circuit gets the 8-bit
data in parallel mode and delivers the 10-bit codedserialized data to deserializer and deserializer decodes the
information and delivers the 8-bit parallel information.
Except serializer circuit which was designed using Cadence
in 0.6 m CMOS technology, all of the blocks were designed
in Verilog and VerilogXL in XILINX. Finally all of the
blocks were combined together to have an integrated system.
I.
INTRODUCTION
A. Design Procedure
Except 10-bit parallel to serial converter, the complete
structure (shown in Fig. 1) has been designed using
Verilog (XILINX 10.1 and CADENCE). The 10-bit
parallel to serial converter has been designed in Cadence
from schematic to layout extraction and post-layout
simulation. Since we want to integrate the Verilog codes
and the blocks of the layout, the Verilog codes were
implemented in Cadence using VerilogXL as well. All of
needed clock frequencies and the adjusting of
synchronization between these clocks (serializer and
deserializer) have been implemented separately by
different Verilog codes.
In designing of 10-bit parallel to serial converter
circuit, we tried to consider many critical performance
parameters such as die area, power dissipation, latency
and throughput.
III.
SYSTEM ARCHITECTURE
144
International Journal of Electronics and Electrical Engineering Vol. 3, No. 2, April, 2015
TABLE I.
Definition in
VERILOG
Lxy
L22
40
L04
L13
L31
145
Number of
Number of
1s
0s
International Journal of Electronics and Electrical Engineering Vol. 3, No. 2, April, 2015
TABLE II.
Time
CLOCK
datain
dispin
dataout
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
725
750
775
800
825
850
875
900
925
950
975
1000
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000000000
101000011
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001000
000001001
000001010
000001011
000001100
000001101
000001110
000001111
000010000
000010001
000010010
000010011
000010100
000010101
000010110
000010111
000011000
000011001
000011010
000011011
000011100
000011101
000011110
000011111
000100000
000100001
000100010
000100011
000100100
000100101
000100110
000100111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0010111001
1010100011
0010101110
0010101101
1101100011
0010101011
1101100101
1101100110
1101000111
0010100111
1101101001
1101101010
1101001011
1101101100
1101001101
1101001110
0010111010
0010110110
1101110001
1101110010
1101010011
1101110100
1101010101
1101010110
0010010111
0010110011
1101011001
1101011010
0010011011
1101011100
0010011101
0010011110
0010110101
1001111001
1001101110
1001101101
1001100011
1001101011
1001100101
1001100110
1001000111
dispo
ut
0
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
Time
CLOCK
datain
dispin
dataout
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
550
575
600
625
650
675
700
725
750
775
800
825
850
875
900
925
950
975
1000
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0000000000
0010010101
0000000001
0000000010
0000000011
0000000100
0000000101
0000000110
0000000111
0000001000
0000001001
0000001010
0000001011
0000001100
0000001101
0000001110
0000001111
0000010000
0000010001
0000010010
0000010011
0000010100
0000010101
0000010110
0000010111
0000011000
0000011001
0000011010
0000011011
0000011100
0000011101
0000011110
0000011111
0000100000
0000100001
0000100010
0000100011
0000100100
0000100101
0000100110
0000100111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
101011111
000010101
101011110
101011101
101011100
000111011
000101111
000100000
000100111
000110111
000110000
000111111
000101011
000111000
000101101
000101110
000101111
000110000
000100001
000100010
000110011
000100100
000110101
000110110
100110111
000101000
000111001
000111010
100111011
000111100
100111101
100111110
000111111
000100000
000111110
000111101
000100011
000111011
000100101
000100110
000101000
dispo
ut
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
z
146
International Journal of Electronics and Electrical Engineering Vol. 3, No. 2, April, 2015
IV.
TABLE IV.
Specification
Value
Power Consumption
<5mw
Die Area
0.15mm2
CMOS Technology
0.6m
VDD
5V
V.
CONCLUSION
REFERENCES
[1]
[2]
[3]
147
International Journal of Electronics and Electrical Engineering Vol. 3, No. 2, April, 2015
[4]
[5]
[6]
148