Serial No.

: I__Microprocessor_260816_EE_LS2

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Electrical Engineering

CLASS TEST

2016
Microprocessor

EE

Date : 26/08/2016

ANSWERS

1.

(c)

7.

(b)

13.

(b)

19.

(b)

25.

(d)

2.

(c)

8.

(c)

14.

(a)

20.

(b)

26.

(d)

3.

(b)

9.

(a)

15.

(b)

21.

(a)

27.

(a)

4.

(d)

10.

(a)

16.

(d)

22.

(c)

28.

(b)

5.

(d)

11.

(c)

17.

(d)

23.

(d)

29.

(d)

6.

(d)

12.

(c)

18.

(c)

24.

(c)

30.

(b)

CTEE16 | Microprocessor

EXPLANATION
1. (c)
1.
2.
3.
4.

MOV A, C
STC
CMC
DCR C

C 00 H
1.

A 00 H

2.

CY 1

3.

CY 0

4.

C FF H
Flags

S
1

Z
0

X
0

AC
0

X
0

P
1

X
0

CY
0

= 84 H
2. (c)
Number of address lines = log2 (32 K) = log2(25 210) = 15
Length of stack pointer = Length of program counter = 15
Since it is an 8 bit microcomputer
So, Numbers of data lines = 8.
3.

(b)
When XRA instruction is executed Sign, Zero, Parity flags are modified to reflect the result of operation with
Carry and Auxiliary flags being reset.

4.

(d)
Total five memory accesses are involved when the instruction LHLD 2000 is executed by the microprocessor
one Op-code fetch cycle and four memory read cycles.

5.

(d)
LDA 7500 H// Load the contents in location 7500 H to accumulator CMA//Complement accumulator ( A )
INR A// Increment A by one ( A + 1)
STA 7500 H// Store contents of accumulator to memory locaton 7500 H
HLT// Halt the program
Contents in location 7500 H are twos complemented.

6.

(d)
Address itself is given so STA is direct addressing mode.

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8
7.

(b)
[A] = 0 1 0 1 0 1 1 0
[B] = 1 0 1 0 1 0 0 1

S Z AC P CY
ADD B 1 1 1 1 1 1 1 1 1 0
0
1
0
1
INR A

1
00 0 0 000 0 0 1

INR doesnt effect carry flag.

8.

(c)
Address of instruction following the CALL instructions is stored in stack at a location pointed by stack
pointer.

9. (a)
ANI instruction resets the carry flag. So, the control of program will not go back to LOOP.
10. (a)
Using tristate buffer, a number of devices can transmit information enabling one device at a time.
11.

(c)
ORA A

MVI B, 64H

CY = 0 to reset the carry

B = (64)H = (100)10

DCR B content of B is decreamented by 1.

All the flags are affected except carry flag. So, conditional jump it not carry (CY = 0) will be true always and
loop will be executed infinitely.
12.

(c)
6000 : LXI SP, 1000H// SP is loaded with 1000 H
6003 : PUSH B
// Contents of BC are pushed into stack and SP = SP 2 = 0FFE
6004 : PUSH D
// Contents of DE are pushed into stack and SP = SP 2 = 0FFC
6005 : CALL 2500 // Call the subroutine at 2500 H and push the content of program counter in
stack, so SP = SP 2 = 0FFC 2 = 0FFA
6008 : POP B// Contents of top of stack are loaded in BC pair
and SP = SP + 2 = 0FFA + 2 = 0FFC
6009 : HLT// Halt the program
After HLT instruction is executed PC is stored with 600A and stack pointer with 0FFC

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CTEE16 | Microprocessor
13.

(b)
Accumulator is initially loaded with C4 H. Instruction ORA A resets the carry flag
CY
RRC

0
CY
0

CY
RAL

CY
RRC

0
CY
0

Contents of accumulator are 62 H.

14.

(a)
LXI SP, 9000 ; SP 9000
LXI H, 005D ; HL 005D
PUSH H ; SP = SP 2 = 8FFE
POP PSW ; Pop the contents 005D onto PSW register.
PSW = accumulator + status register
PSW = 00 5D
Status Register =

AC

CY

15.

(b)
L X I B, 000A H 00 B, OA C
LOOP:DCX B Flag is not affected
MOV A, B
ORA C A is not zero because C is not zero so, Z = 0
JNZ LOOP Loop will be executed until C is zero and Z = 1
So, loop will execute OA times i.e 10 times.

16.

(d)
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0

1
3

0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1

Range : 3000 H 3FFFH

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17.

(d)

CY
1
x x x x 0 0 0 0

A:

After execution of RRC 4 time

0 0 0 0 x x x x

A:

Which is equivalent to dividing by (10000)2 or 16.

18. (c)
(1)
(2)
(3)
(4)
(5)
(6)

SP
SP 2
SP 2
PC
SP + 2
SP

4000
3FFE
3FFC
3050
3FFE
3FFE

H
H
H
H
H
H

PC 3009 H
PC 300A H

19.

(b)
Pointers (HL pair) cant be used to access I/O mapped I/O.
Indirect addressing is not possible. When ALE signal goes high multiplexed bus is used as address bus
and when it goes low multiplexed bus is used as data bus.
For I/O mapped I/O instructions are fewer e.g. IN, OUT.
But for memory mapped I/O instructions are more e.g., ADD M, MOV M, A etc.

20.

(b)
HL
04 84 H
SP
20 99 H
DAD
25 1 D H
Result of DAD instruction is stored in HL pair while the content of stack pointer remain unchanged.

21.

(a)
FF00

MVI A, DC H

FF02

ORA

FF03

LXI FF08 H

FF06

SUB M

FF07

OUT A2 H

FF09

HLT

FF08

A2 H

(DC A2) H = 3A H
Contents of accumulator = 3A H
Data displayed at port A2 is 3A H.

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CTEE16 | Microprocessor
22.

11

(c)
1

SOD SDE

0
X

R7.5 MSE M7.5 M6.5 M5.5

Serial data enable bit is zero.

Serial data is disabled.
MSE - Mask set enable bit is 1.
Masking of bit is enabled.
RST 7.5 and RST 6.5 are masked while RST 5.5 is enabled.
24. (c)
(1) A 8F H
(2) (8F CA) H = C5 H

[Borrow in substraction is 1, so carry flag is 0]

S
1

Z
0

X
0

P
1

X
0

AC
1

X
0

CY
0

= 94 H

No carry is generated
So, data displayed at port 1 is C5 H.
25.

26.

(d)
TRAP
RST 7.5
RST 6.5
RST 6.5
INTR

Edge and level both

Edge trigger
Level trigger
Level trigger
Level trigger

TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

Vectored (0024)
Vectored (003C)
Vectored (0034)
Vectored (002C)
Non vectored

TRAP
RST 7.5
RST 6.5
RST 6.5
INTR

Non maskable
Maskable
Maskable
Maskable
Maskable

(d)
MOV
MVI
ADD
CMP

Does not affect any flag

Does not affect any flag
Flags affected
Flags affected

27.

(a)
HLT and NOP are the machine control instructions. These instructions affect the operation of the processor.

28.

(b)

IO / M is high so its IO operation. WR goes low so its a write operation. Hence (b).

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29.

(d)
When POP B instruction is executed, the first data byte present at top of the stack i.e. (1000)H is stored in
C register and the next data byte present at memory location (SP + 1) (1001)H will be stored in register
B and value of SP becomes (1002)H.

30.

(b)
Machine cycles of OUT 20 H are
Opcode fetch, memory read (For stored address) and I/O write.
Hence, RD = 2 ; WR = 1 ; ALE = 3.

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