Académique Documents
Professionnel Documents
Culture Documents
College of Engineering
Tibanga, 9200 Iligan City, P.O. Box No.5644 Tel. Nos. (063) 221-4050 Loc.130
Direct line (063) 2351E-mail:fbalagao@yahoo.com
Homepage: http://www.msuiit.edu.ph/coe
Resistors Layout
In partial fulfillment for the course
ECE 135 (CAD Tools and Layout)
Submitted by:
TOLEDO, John Xavier P.
Submitted to:
Prof. Jefrey C. Pasco
April 2016
ABSTRACT
R= s
Where,
Rs
( WLT )=R ( WL )
s
= sheet resistance
Rs = 59
W = 2.5 m W = 0
No. of
L=
R(W W )
1640 (2.5 m)
=
=2.895 m
Rs (No . of Segments)
59 (24)
Figure 2. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Total Width
Total Length
No. of
Segments
Resistance
Value
N+ Diffusion
without
Silicide
(w/RPO)
2.5 m
69.48 m
24
1639. 73
L=
R(W W )
1640 (1.8 m0.0765 m)
=
=28.21 m
Rs (No . of Segments)
6.82(16)
Figure 3. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Total Width
Total Length
No. of
Segments
Resistance
Value
N+ Diffusion
with Silicide
(w/o RPO)
1.8 m
451.36 m
16
1640. 43
L=
R(W W )
1640 (2.5 m)
=
=1.285 m
Rs (No . of Segments)
133 (24)
Figure 4. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Total Width
Total Length
No. of
Segments
Resistance
Value
P+ Diffusion
without
Silicide (w/
RPO)
2.5 m
30.84 m
24
1640. 69
L=
R(W W )
1640 (1.8 m+0.08 m)
=
=16.555 m
Rs (No . of Segments)
7.76 (24 )
No. of Segments =
Figure 5. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Total Width
Total Length
No. of
Segments
Resistance
Value
P+ Diffusion
with Silicide
(w/o RPO)
1.8 m
397.32 m
24
1640
L=
Rs = 7.9
W = 1.8 m W = -0.057 m
R(W W )
1640 (1.8 m+0.08 m)
=
=16.09 m
Rs (No . of Segments)
7.9 (24)
No. of Segments =
Figure 6. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Total Width
Total Length
No. of
Segments
Resistance
Value
N+ Poly with
Silicide (w/o
RPO)
1.8 m
386.16 m
24
1640.71
L=
R(W W )
1640 (1.8 m+0.057 m)
=
=16.09 m
Rs (No . of Segments)
7. 8 9 (24)
No. of Segments =
Figure 7. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Total Width
Total Length
No. of
Segments
Resistance
Value
P+ Poly with
Silicide (w/o
RPO)
1.8 m
379.70 m
24
1641.47
L=
Rs = 927 W = 24 m W = 0.182 m
R(W W )
840 k (24 m0.1 8 2 m)
=
=899.275 m
Rs (No . of Segments)
927 (24)
No. of Segments =
Figure 8. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Width per
Segment
Total Length
No. of
Segments
Resistance
Value
N-Well under
STI
24 m
21582.6 m
24
839976
h. N-Well Under OD
Calculations:
Given R= 840k
40
L=
Rs = 440 W = 20 m W = 0.141 m
R(W W )
840 k (20 m0.1 41 m)
=
=947.815 m
Rs (No . of Segments)
440 (40)
No. of Segments =
Figure 8. Schematic Diagram, Layout, Verifications Results LVS and LPE-, and
Largest Parasitic
Value.
Resistor Type
Width per
Segment
Total Length
No. of
Segments
Resistance
Value
N-Well Under
OD
20 m
37912.60 m
40
840000
Resistor Type
Exact Value
Layout Value
N+ Diffusion
without Silicide
(w/RPO)
N+ Diffusion with
Silicide (w/o
RPO)
P+ Diffusion
without Silicide
(w/ RPO)
P+ Diffusion with
Silicide (w/o
RPO)
N+ Poly with
Silicide (w/o
RPO)
P+ Poly with
Silicide (w/o
RPO)
N-Well Under STI
1640
1639. 73
Percent
Difference (%)
0.01646
1640
1640. 43
0.02622
1640
1640. 69
0.04207
1640
1640
1640
1640.71
0.04329
1640
1641.47
0.08963
840000
839976
0.00286
N-Well Under OD
840000
840000
CONCLUSION
Resistors are the most common type of passive component in analog
integrated circuits, and many different types are available. CMOS offers doped
polysilicon resistors that are superior to diffused resistors and well resistors are
used to obtain large values of resistance. The value of most resistors can be
determined by means of simple computation involving length and width.
Based on Table 8, the layout resistance value for each type hardly achieved
exact value of resistance. The increase or decrease of resistance is based on the
percentage tolerance of the resistor. Based on the layout for each resistor, each
segment has the same width and oriented in the same manner with other
segments. Each resistor has included dummy except in the NWell under OD and also
each segment is connected in serpentine manner in order to cancel the
thermoelectric effect.
REFERENCES
1. Hastings, Alan; The Art of Analog Layout (2016), 2 nd ed., Publishing