Seatwork in

Advanced Logic Circuits Design

Name:
Course/Year/Section:

Date:

1. Given the truth table below.

a. create the equivalent vhdl program using behavioral modeling with the
implementation of sequential circuits with negative edge trigger clock.
Initial
State

Q
2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

Q
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Q
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Cont
rol
Sign
al
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Next
State

Q
2
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1

Q
1
0
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1

Q
0
1
0
1
0
1
0
1
0
0
1
0
1
1
0
1
0

b. draw the equivalent state diagram using moore model