Linear Tech Journal2016

May 2016
Volume 26 Number 2
I N T H I S I S S U E
multi-output clock
20A LED Driver with Accurate 3%
Full Scale Current Sensing Adapts to
synthesizer with integrated
VCO and low jitter 12
negative current-reference
linear regulator 20
Multitude of Applications
Josh Caldwell and Walker Bai
load sharing for three or

four supplies with unequal Rapidly evolving LED lighting applications are replacing nearly
voltages 26
all traditional forms of illumination. As this transformation
accelerates, power requirements for LED drivers increase,
monolithic SEPIC/boost with higher currents making it more challenging to maintain
regulators with wide VIN
range, high efficiency,
current sensing accuracy without sacrificing efficiency. LED
and power-on reset and drivers must do this while managing current delivery to
watchdog timers 28 multiple independent LED loads at high speeds, and be able
to connect parallel drivers with accurate current sharing.
Some high power LEDs have unique mechanical and
electrical considerations, where the anode is electrically
tied to the thermally conducting backtab. In a traditional
LED driver with a step-down regulator configuration,
where thermal management is achieved by cooling the
chassis, the anode connection to the backtab creates a
mechanical-electrical design challenge. The backtab must
have good thermal conductivity to the heat sink, but
also be electrically isolated from it if the voltage at the
tab is different from the chassis. Since is it difficult for
LED manufacturers to change processing or packaging,
the LED driver itself must meet this design challenge.
One option is to use a 4-switch positive buck-boost LED

driver, but the additional switching MOSFETs add system
complexity and cost. An inverting buck-boost topology
uses only one set of switching power MOSFETs, and allows
The LTC4125 5W AutoResonant wireless power transmitter features foreign object
the anode heat sink to be tied directlyelectrically and
detection and completes linear wireless charging solutions (see page 31). (continued on page 4)
w w w. li n ea r.com
Linear in the News
In this issue...
COVER STORY SINGAPORE TEST FACILITY EXPANDS TO BOOST PRODUCTION

CAPACITY
20A LED Driver with Accurate 3% Full Scale In February, Linear opened the companys third semiconductor test facility in
Current Sensing Adapts to Multitude of Applications
Josh Caldwell and Walker Bai 1 Singapore. The additional space for staff, equipment and materials will allow
the company to more than double its production capacity of analog circuits and
DESIGN FEATURES Module (power module) products. This strengthens Linears ability to meet the
growing demand for high performance analog integrated circuits worldwide.
Multi-Output Clock Synthesizer with Integrated
VCO Features the Low Jitter Required to Drive The new 87,000 square foot facility is located beside Linear Technologys
Modern High Speed ADC and DAC Clock Inputs current 191,000 square foot facility in Singapore. The companys Singapore
Chris Pearson 12
test operation, started 27 years ago in 1989, has sophisticated capabilities for
1.5A, Negative Regulator Expands Family of high volume testing of the companys numerous products, including many
Current-Reference Linear Regulators package types, tape and reel, as well as pack and ship to customers worldwide.
Dawson Huang 20 The location also includes Linears Singapore Design Center and the area sales
office supporting Singapore, Malaysia, India and Australia/New Zealand.
DESIGN IDEAS
Continued Expansion
Whats New with LTspice IV?
Gabino Alonso 24 Over the years, Linear has continued to expand its Singapore test opera-
tions, with expansion of its first building in 1997 and a second five-story
Easy Balanced Load Sharing for Three or Four building completed in 2005. This third major expansion, adding an addi-
Supplies, Even with Unequal Supply Voltages tional 87,000 square foot test facility, is now complete. With head count of
Vladimir Ostrerov and Chris Umminger 26
nearly a thousand employees today, Linear has a highly experienced team,
capable of testing the most high performance analog ICs. The facility provides
Design Once; Use Twice: Monolithic SEPIC/Boost
Regulators with Wide VIN Range Satisfy Requirements test capability for over 90 percent of the companys global demand.
of Both Consumer and Commercial Vehicles
Molly Zhu 28 Over the past decade, Linears products have grown in sophistication
and complexity. This has paralleled the companys increasing participa-
new product briefs 30 tion in the key electronics growth markets of industrial and automotive.
Industrial, at 44 percent of the companys business in the most recent fiscal
back page circuits 32
year, is a broad market that includes industrial process control, factory
automation, robotics, instrumentation and medical, among others.
Linear has also enjoyed significant growth in its automotive business, reaching
20 percent of the companys business. This market is driven by the increas-
ing use of electronic systems, replacing mechanical and other systems, in
all aspects of the car, from safety and navigation to electronic steering and
braking and many systems under the hood. This technical transformation
has resulted in analog and power devices that are increasingly complex, and
require sophisticated test systems, now installed in the companys Singapore
facility. These test systems enable Linear to provide the high quality and
reliability demanded by industrial and automotive manufacturers.
2 | May 2016 : LT Journal of Analog Innovation

Linear in the news
Linears Singapore receive the highest quality products

test facility expands
to boost production
in the shortest possible lead times.
capacity.
CONFERENCES & EVENTS
Sensor+Test 2016, Nuremberg Exhibition Centre,

Nuremberg, Germany, May 1012, Booth 241,
Hall 1Showcasing Linears broad line
of high performance ICs, including
SmartMesh IP solutions. There will
be workingdemo applications from
European customers usingLinears
products. www.sensor-test.de/welcome-to-
the-measurement-fair-sensor-test-2016/
Internet of Things World 2016, Santa Clara

Convention Center, Santa Clara, California,
In addition to test capability for the components of our global manufacturing
May 1012Linears Dust Networks
companys analog and power ICs, the operations. Given the excellent conditions
wireless sensor network products.
Singapore facility has extensive test capa- for growth in the region, as well as the
https://iotworldevent.com/
bility for Linears growing line of Module skill and dedication of our employees here,
power products. These are complete power Singapore will remain as the headquarters Space Tech Expo, Pasadena Convention Center,
systems-in-package with integrated induc- and focal point for all Linear Technology Pasadena, California, May 24-26, Booth 8025
tor, MOSFET, DC/DC regulator ICs and operations in Asia. We will continue to Showcasing products for space and harsh
supporting components. Each Module enhance our capabilities here to deliver environments. www.spacetechexpo.com/
product is thoroughly tested using Linears advanced technology solutions to rapidly
NXP FTF Technology Forum, JW Marriott, Austin,
stringent electrical, package and thermal growing markets around the world.
Texas, May 1619Power management ICs
reliability tests. The new Singapore
Lothar Maier, Chief Executive Officer and Module products. www.nxp.com/
expansion provides the company with
of Linear Technology, added, I have support/classroom-training-events/nxp-ftf-
additional capacity for testing Module
high confidence in our Singapore test tech-forum:NXP-FTF-TECH-FORUM-HOME
products to meet growing demand.
infrastructure and the talent base weve
Wireless Japan 2016, Tokyo Big Sight, Japan,
Also located in Singapore is the cultivated here over many years, and
May 2527, Booth 1233Demonstrating
companys reliability testing center. we expect to grow it. Our advanced test
Linears Dust Networks wireless
This is a fundamental part of Linears operations here ensure that our customers
sensor network products and their
operations, focusing on ensuring in the demanding and fast growing auto-
ecosystem in Japan. www.wjexpo.com
superior product quality for automo- motive and industrial markets continue
tive and other demanding markets. to receive the highest quality products. Sensors Expo & Conference, McEnery Convention
Center, San Jose, California, June 2123, Booth
Grand Opening Complete Manufacturing Capability
940Presenting Linears energy harvest-
In February, Linears management team Linears Singapore test operation is just ing family and low power wireless sensor
was in Singapore for the opening of one part of the companys advanced networks. www.sensorsexpo.com/
the expanded test facility. They toured manufacturing operations. These
the new facility and spent time with include two wafer manufacturing IEEE Nuclear and Space Radiation Effects
the Singapore operations team. facilities, located in Milpitas, California Conference, DoubleTree and Oregon Convention
and Camas, Washington, as well as Center, Portland, Oregon, July 1115, Booth
Robert Swanson, Linear Technology 33Showcasing products for space and
a wafer sort and package assembly
co-founder and Executive Chairman, harsh environments. www.nsrec.com/ n
operation in Penang, Malaysia. These
who flew to Singapore for the opening,
facilities ensure that Linear customers
said, The facilities in Singapore are vital
May 2016 : LT Journal of Analog Innovation | 3

To meet high performance demands, the LT3744 can be configured
as a synchronous step-down or inverting buck-boost controller
to drive LED loads at continuous currents exceeding 20A. The
supply input for the LT3744 is designed to handle 3.3V to 36V.
(LT3744, continued from page 1) 300 100

125C 380 TYPICAL UNITS 125C 380 TYPICAL UNITS
mechanicallyto the chassis ground, 25C VCTRL1 = 0V 90 25C VCTRL1 = 1.5V
250 45C 45C
eliminating the need for electrical isola- 80
tors on the heat sink, and simplifying 70

NUMBER OF UNITS
NUMBER OF UNITS
200
the mechanical design of the system. 60
150 50
To meet high performance demands, the 40
LT3744 can be configured as a synchro- 100
30
nous step-down or inverting buck-boost 20
50
controller to drive LED loads at continu- 10
ous currents exceeding 20A. The supply 0 0

300 200 100 0 100 200 300 59 59.4 59.8 60.2 60.6 61
input for the LT3744 is designed to handle REGULATED VLED_ISP - VLED_ISN VOLTAGE (V) REGULATED VLED_ISP - VLED_ISN VOLTAGE (mV)
3.3V to 36V. As a step-down converter,
Figure1. The LED current regulation amplifier Figure2. At full current, the LED current regulation
it regulates LED current from 0V up in the LT3744 has a typical offset of 300V with loop has a typical accuracy of 1.7% with VCTRL =
to the supply voltage. As an inverting VCTRL=0V. 1.5V.
buck-boost converter, the LT3744 can
accurately regulate LED currents with dissipation, the LT3744 can be easily to 1/20th of the total current control
output voltages from 0V down to 20V. paralleled with other LT3744s to drive range. This is critical in applications
Full-range analog current regulation high pulsed or DC currents in LED loads. where the total digital PWM dimming
accuracy is 3%, and even at 1/20th scale, range is limitedor in applications where
HIGH ACCURACY CURRENT
it is better than 30%. The LT3744 has very high dimming range is required.
SENSING
three independent analog and digital As an example, with a 100Hz PWM
The LT3744 features a high accuracy dimming frequency and a 1MHz switch-
control inputs with three compensation
current regulation error amplifier, which ing frequency, the LT3744 is capable of
and gate drive outputs for a wide range
achieves accurate analog dimming down 1250:1 PWM dimming, which can be
of LED configurations. By separating
the inductor current sense from the LED combined with 20:1 analog dimming to
current sense, the LT3744 can be config- extend the total diming range to 25,000:1.
ured as a buck or inverting buck-boost. PWM1
5V/DIV Figure 1 shows the production consistency
For ease of system design, all input of the LT3744 with regard to offset voltage
signals are referenced to board ground SW
10V/DIV over temperature, in this case 380 typical
(SGND, signal ground), eliminating the units when the analog control input is
need for complex discrete level-shifters. at 0V. With the low offset of the error
ILED
In the inverting buck-boost configura- 1.67A/DIV amplifier, the control loop is capable of
tion, the total LED forward voltage a typical accuracy of 10% at 1/20th
IL
can be higher than the input supply 20A/DIV
scale analog dimming. The distribution
voltage, allowing high voltage LED of the regulated voltage across the LED
strings to be driven from low voltage
1s/DIV, 5-MINUTE PERSISTENCE current sensing pins with the control
supplies. When PCB power density calls input equal to 1.5V is shown in Figure 2.
for spreading the component power Figure3. The LT3744 features flicker-free LED The accuracy at full range is better than
dimming.

design features
In projection systems, reducing the turn-on time of the light source reduces timing
constraints. With a reduction in timing constraints, the image refresh rate can
increase, allowing higher resolution images and a reduction in the rainbow effect
from fast-moving white objects. The LT3744 is capable of transitioning between
the different output current states in less than three switching cycles.
Figure4. The LT3744 is capable of driving VIN

EN/UVLO EN/UVLO VIN L1: IHLP-5050FD-ER1R2M01
a single LED with three different current PWM1 1F 56F 24V
4 RS: WSL28163L000D
levels. PWM2 RSLED: WSL28163L000J
PWM3 TG M1
M1: BSC050NE2LS
CTRL1 220nF
M2: SiR438DP
CTRL2 BOOST M3, M4, M5, M6, M7, M8: Si7234DP
CTRL3 D1, D2. D3, D4: BAT54A
SW L1 RS C1, C2, C3: 10T4B330M
LT3744 1.2H 20A MAXIMUM
2V 3m
VREF INTVCC
2.2F 22F C1
100k 330F C2
RHOT BG M2 330F C3
FAULT BLUE
45.3k 330F
CTRLT VEE M4
RNTC ISP M6 51k
SGND
680k ISN M3 M8
D1 D2
M5 10F
SYNC PWM_OUT1 M7
D3
SS PWM_OUT2
D4
10nF RT VFNEG
PWM_OUT3
82.5k
LED_ISP
VEE LED_ISN RSLED
FB 3m
VC1 VC2 VC3
287k 287k 287k
10nF 10nF 10k

10nF
3%, which corresponds to 1.8mV on is 1 H, the PWM dimming frequency The LT3744 features three regulated
the 60mV full-scale regulation voltage. is 100Hz with an on-time of 10sec current states, allowing color-mixing
(1000:1 PWM dimming). Roughly 30,000 system designers to sculpt the color
FLICKER-FREE PERFORMANCE
dimming cycles are shown, with no temperature of each LED. Color mixing
One of the most important metrics in LED jitter in the switching waveformevery delivers high color accuracy, corrects
driver performance is in the recovery of recovery switching cycle is identical. inaccurate LED colors, and eliminates
the LED current during PWM dimming. variations in production systems. While
The quality of the end product is highly HIGH SPEED DIMMING BETWEEN
the LT3743 has low and high current states,
THREE DIFFERENT REGULATED
dependent on the behavior of the driver the LT3744 features three current states so
CURRENTS
in the first few switching cycles after the that all three RGB LED colors can be mixed
rising edge of the PWM turn-on signal. In projection systems, reducing the
with each other at their own light outputs
The LT3744 uses proprietary PWM, turn-on time of the light source reduces
to independently correct the other colors.
compensation and clock synchronization timing constraints. With a reduction in
technology to provide flicker-free perfor- timing constraints, the image refresh rate Figure 4 shows a 24V input/20A output,
manceeven when driving LEDs to 20A. can increase, allowing higher resolution single LED driver with three different regu-
images and a reduction in the rainbow lated currentsdetermined by the analog
Figure 3 shows a 5-minute capture of the effect from fast-moving white objects. voltages on the CTRL and the digital
LED current recovery with a 12V supply The LT3744 is capable of transitioning state of the PWM pins. Note that since
delivering 20A to a red LED. The switch- between the different output current RS is only used for peak inductor current
ing frequency is 550kHz , the inductor states in less than three switching cycles. and absolute overcurrent protection,

Within miniature pocket or smartphone projection systems, total solution space
and cost are paramount. The LT3744 combines switched output capacitor
technology with a floating gate driver to create a complete RGB solution from
a single LED driver, a significant space savings over multi-IC drivers.
it does not need to be a high accuracy A COMPLETE RGB LED SOLUTION The LT3744 combines switched output
resistorwhich reduces system cost. FOR POCKET OR SMARTPHONE capacitor technology with a floating gate
PROJECTORS
driver to create a complete RGB solution
PWM dimming between the three differ- Within miniature pocket or smartphone from a single LED driver. The LT3744
ent current states is shown in Figures
projection systems, total solution space uses a unique gate driver for the PWM
5 and 6. In Figure 5, the PWM signals
and cost are paramount. In these applica- output pins. The negative rail of the driver
are sequentially turned on and off.
tions, PCB space is extremely limited and floats on the VFNEG pin, allowing it to
PWM3 has the highest priority and the total volume of the driver solution pull down the gates of all of the switches
PWM1 has the lowest. This allows (including component height) must be that are off to negative voltages. This
rapid, single input signal transitions to
minimized. Using only one LED driver ensures that the switches in-series with the
change the output current. As shown
for all three LEDs drastically reduces output capacitors do not turn on in any
in Figure 6, there can be any arbitrary
spaceallowing use of larger batter- condition. This driver allows up to a 15V
interval between the PWM input signals.
ies or higher power LEDs for improved difference between any string of LEDs.
battery lifetime and projected lumens.
Each LED can be turned on sequentially,
with a time delay in between, or with any
Figure7. The LT3744 is capable of driving

all three color component (R, G and B) VIN
EN/UVLO EN/UVLO VIN L1: MSS1048-682NL
LEDs in a pocket or smartphone projector 3.3V
PWM1 20F 47F RS: WSPL08056L000FEA18
from a single Li-ion battery. PWM2 RSLED: WSLP1206R0120D
PWM3 VEE
M1: BSC010NE2LSI
CTRL1 M2: SiR438DP
CTRL2 TG M1
220nF M3, M4, M5, M6, M7, M8: Si7234DP
CTRL3 D1, D2. D3, D4: BAT54A
BOOST D5: PMEG4010
SW L1 RS
LT3744 6.8H 20A MAXIMUM
2V 6m
VREF INTVCC
2.2F 22F 330F
100k 2.2F G
RHOT 330F B R
FAULT BG M2
45.3k 330F G
CTRLT VEE M4
RNTC ISP
SGND
680k ISN M3
D1 D2
SYNC PWM_OUT1 M6
D3
SS PWM_OUT2 M5
10nF
D4 107k
RT VFNEG M8
PWM_OUT3 M7
40.2k
LED_ISP
VEE LED_ISN
RSLED
FB 12m
VC1 VC2 VC3
6.8nF 10k
6.8nF
6.8nF
D5
VEE

design features
In addition, with the three independent analog control inputs, each

LED can operate at a different regulated current. When the LT3744 is
configured as an inverting buck-boost, a single lithium-ion battery can
drive three independent LED strings using only a single controller.
Summary of Linears high power LED driver-controller family
LT3741 LT3743 LT3744 LT3763 LT3791
V IN range 6V36V 6V36V 3.3V36V 6V60V 4.7V60V
LED output range 0V34V 0V34V 20V36V 0V55V 0V52V
buck and inverting

Topology buck buck buck buck-boost
buck-boost
LED current regulation accuracy 6% 6% 3% 6% 6%

1
10 scale LED current accuracy 60% 60% 17% 60% 35%
Full-scale LED current sense 50mV 50mV 60mV 50mV 100mV
Common anode connection for LEDs L
LED fault indication L L L
Low side LED PWM gate driver(s) 0 2 3 1 1
Individual LED current states 1 2 3 1 1
pattern input into the PWM digital inputs. LED strings using only a single control- 324W 2-LED DRIVER USING TWO
In addition, with the three independent ler. Figure 7 shows a 3.3V/5A inverting PARALLEL LT3744 LED DRIVERS
analog control inputs, each LED can tri-color buck-boost LED driver designed A significant limiting factor in any high
operate at a different regulated current. specifically for RGB pocket projectors. power/high current controller design is
When the LT3744 is configured as an power density in the PCB. PCB power
inverting buck-boost, a single lithium- density is limited to roughly 50Wcm2
ion battery can drive three independent to prevent excessive temperature rise
within the power path components.
In extreme cases, where an LED load
PWM1 PWM1 requires more power than a single driver
5V/DIV 5V/DIV
PWM2 PWM2
can support (while remaining within
5V/DIV 5V/DIV power density limits), multiple convert-
PWM3 PWM3
5V/DIV 5V/DIV ers can be paralleled to spread the load.
An efficient high current LED driver-

controller, with modern power MOSFETs,
ILED ILED
6.67A/DIV 6.67A/DIV can provide roughly 200W (at a solution
size of approximately 4cm2) and limit all
power path component temperatures to
25sec/DIV 25sec/DIV
under 80C. For LED loads higher than
Figure5. The LT3744 transitions between any of Figure6. The different current states can be turned 200W, the LT3744 can be paralleled with
three regulated current states and off in less than on at any timewith or without time in between other LT3744s to limit the temperature rise
three switching cycles. each state.

VIN
1F 22F 12V
100k 10F 56F
D1 4 2
EN/UVLO VIN INTVCC

PWM1 PWM1
PWM2 PWM2
PWM3 BOOST
100k
M1 47F
TG 2
L1
0.22F
82.5k 0.82H 2m
FAULT
SW
VREF
470F
1nF 100k M2
CTRLT U1 BG
470F
LT3744 2.43k
100k
CTRL1 ISP
100k ISN D5 D6
CTRL2
2.2F 100k FB
SYNC
100k PWM_OUT1
RT
PWM_OUT2
604 M5 M9
SS VFNEG
1nF
10nF LED_ISP
M6 M10
SGND VEE VC1 VC2 LED_ISN
M13
M15
1nF
1nF 25.5k 25.5k
226k 226k 10nF 10nF

D3
2m
VIN
1F 22F
100k 10F 56F
D2 4 2
D1, D2: NXP PMEG4002EB
D3D8: BAT54A
EN/UVLO VIN INTVCC L1, L2: VISHAY IHLP-5050FD-ERR82
PWM1 M1, M3: BSC032NE2LS
PWM2 M2, M4: BSC010NE2LS
BOOST M5M12: Si7234DP
PWM3
100k M13M16: BSC010NE2LS
M3 47F
TG 2
L2
0.22F
82.5k 0.82H 2m
FAULT
SW
VREF
470F
1nF 100k M4
CTRLT U2 BG
470F
LT3744 2.43k
100k
CTRL1 ISP
100k ISN D7 D8
CTRL2
2.2F 100k FB
SYNC
100k PWM_OUT1
RT
PWM_OUT2
604 M7 M11
SS VFNEG
1nF
10nF LED_ISP
M8 M12
SGND VEE VC1 VC2 LED_ISN
M14
1nF
1nF 25.5k 25.5k M16
226k 226k 10nF 10nF
D4
2m
Figure8. A 57A/324W 2-LED driver

design features
Figure11. Parallel board

temperatures at 100% duty
cycle delivering 324W to the INDUCTOR
LED
SWITCHING
MOSFETS
CHANNEL 1
CHANNEL 2 LT3744
9A/DIV
10ms/DIV
VIN = 12V
VOUT = 4V
Figure9. LED current sharing during start-up IOUT = 54A
fSW = 400kHz
100% DUTY CYCLE
controllers in this design produces 27A inductor, Q1 and Q3 are the switching
for a total of 54A at 6V. By tying the power FETs, R5 is the inductor current
CHANNEL 1
9A/DIV corresponding compensation outputs sense resistor, R32 is the LED current
CHANNEL 2
9A/DIV together, both controllers behave in sense resistor, and U1 is the LT3744.
unison to provide a smooth, well behaved
In this application, two independent LED
start-up and accurate DC regulation.
strings can be PWM dimmed at the full
Figure 9 shows the LED current start-up 54A. When PWM dimming, Figure 12
20s/DIV behavior of each board. Note that the shows that the LED current is completely
regulated current provided by each board shared between the two drivers. In this
Figure10. DC LED current sharing at full load
showing very little variation between the two parallel
is identical throughout the entire start- test, the rise time of the current in the LED
drivers up sequence. In DC regulation, without from 0A to 54A is 6.6s. The electrical
PWM dimming, Figure 10 shows excel- connection from the output of each driver
in any particular component. All compen- lent current sharing between the two to the LED must be carefully balanced to
sation outputs should be paralleled, allow- application boards (the waveforms are avoid added inductance in either path
ing current sharing between each regulator. directly on top of each other). Figure 11 which reduces the effective rise time.
shows that the temperature rise above
Figure 8 shows a 324W converter using Figure 13 shows the temperature
ambient of the board at 100% duty
two Linear DC2339A demo boards rise in each demo board with a 50%
cycle is about 55C. Component L1 is the
connected in parallel. Each of the parallel PWM-dimmed LED current of 54A. To
Figure13. Parallel board

temperatures at 50% PWM
dimming delivering 54A
INDUCTOR
PWM pulses to the LED
2V/DIV
SWITCHING
MOSFETS
CHANNEL 1 LT3744
CHANNEL 2
9A/DIV
20s/DIV
VIN = 12V
VOUT = 4V
Figure12. The LT3744 features excellent LED current IOUT = 54A
sharing between parallel drivers during PWM fSW = 400kHz
50% DUTY CYCLE
dimming.

Figure14. This parallel inverting
VIN application delivers 120W to a
1F 22F 12V chassis tied common-anode LED.
10F 56F 100k 10F
D1 2
VEE
VEE
EN/UVLO VIN INTVCC
PWM1 PWM1
PWM2
100k BOOST
PWM3
100k M1
TG
SYNC SYNC L1
0.22F
82.5k 1.3H 1m
FAULT
SW
VREF
1nF 10F
100k M2
CTRLT U1 BG
LT3744 4.02k VEE
100k VEE
CTRL1 ISP 470F
100k ISN D5
CTRL2
FB
2.2F
PWM_OUT1
PWM_OUT2 1k
1nF
1nF 1nF
VFNEG
M5
226k 226k
LED_ISP
VEE
SGND VEE RT SS VC1 LED_ISN
M6
33nF D3
143k
10nF
VEE VEE
3m
VEE
VEE
VIN
1F 22F
10F 56F 100k 10F
D2 2
VEE VEE
EN/UVLO VIN INTVCC D1, D2: NXP PMEG4002EB
PWM1 D3D6: BAT54A
L1, L2: WRTH 7443551130
PWM2
100k BOOST M1, M3: BSC026N04LS
M2, M4: BSC018N04LS
PWM3 M5M8: Si7234DP
100k M3
TG
SYNC L2
0.22F
82.5k 1.3H 1m
FAULT
SW
VREF
1nF 10F
100k M4
CTRLT U2 BG
LT3744 4.02k VEE
100k VEE
ISP 470F
CTRL1
100k ISN D6
CTRL2
FB
2.2F
PWM_OUT1
PWM_OUT2 1k
1nF
1nF 1nF
VFNEG
M7
226k 226k
LED_ISP
VEE
SGND VEE RT SS VC1 LED_ISN
M8
33nF D4
143k
10nF VEE VEE
3m
VEE
VEE

design features
By regulating the LED current directly and level-shifting all input signals, the
LT3744 is capable of producing negative voltages, allowing low voltage battery
operated systems to drive multi-LED strings with a simple 2-switch solution.
minimize the inductance from each of the Figure15. Parallel inverting

board temperatures
demo boards to the LED, the parallel LED delivering 120W to the LED
driver boards were mounted directly on INDUCTOR
top of each other. A more optimized layout
SWITCHING
would feature both drivers mounted on MOSFETS
a single board, with the driver layouts
mirroring each other, reflected across their
LT3744
mutual connection to the LED. Whenever
designing the conduction path from a
LED driver to a high current LED, careful
attention should be placed on the total
VIN = 12V
inductance. Since inductance is a func- VOUT = 4V
tion of wire length, the longer the wire, IOUT = 30A
fSW = 350kHz
the longer the current recovery in the
LEDno matter how fast the driver.
In the inverting buck-boost topology, the in a wide range of applications. The
INVERTING BUCK-BOOST, 120W
inductor current is delivered to the load LT3744 has the capability to be used as the
LED DRIVER WITH TWO PARALLEL
LT3744s
only during the synchronous FET conduc- single driver in an RGB projection system,
tion time. If the two parallel converters drastically reducing total solution space
Inverting buck-boost applications have the
are allowed to run at their free-running making it possible to produce high lumen
same thermal concerns as non-inverting
frequencies, there is noticeable beat video projection from a smartphone.
converters, with the additional design
frequency apparent in the LED current
challenge of increased inductor current. Through the use of three current regu-
ripple resulting from the slight switching
For low input voltages and high LED volt- lation states, the LT3744 gives system
frequency differences. To avoid this, each
ages, the average current in the inductor designers freedom to sculpt LED color,
converter uses the same RT resistor value,
could be very high. For example, if the producing more faithful video images. By
but they are synchronized using an exter-
input is 3.3V and the output is one green regulating the LED current directly and
nal clock. In the application in Figure 14,
LEDwhich has a forward voltage of 6V level-shifting all input signals, the LT3744
the converters are designed to run at a
at 20Athe peak inductor current is 70A. has the capability to produce negative
non-synchronized frequency of 300kHz
The inductor used in the design should voltages, allowing low voltage battery
with a 350kHz synchronizing clock.
have a saturation current at least 20% operated systems to drive multi-LED
higherin this case, greater than 80A. Figure 15 shows the component tempera- strings with a simple 2-switch solution.
ture rise when delivering 30A to the LED in The LT3744 can be easily paralleled
Since this current flows in the switching
a parallel inverting buck-boost application. with other LT3744s to efficiently deliver
MOSFETs, the MOSFETs must be rated
extremely high current to an LED, while
for greater than 80A. By placing two CONCLUSION
maintaining current accuracy and sharing
LT3744 inverting buck-boost converters With features including high current even when PWM dimming. Paralleling the
in parallel, the peak switched current is regulation accuracy, a floating PWM gate LT3744 lowers board temperatures, reduces
cut in half, reducing the requirements driver, and level shifted input signals, the inductor currents and expands supported
of the power path components. LT3744 can be configured to drive LEDs LED power to hundreds of watts. n

Multi-Output Clock Synthesizer with Integrated VCO Features
the Low Jitter Required to Drive Modern High Speed ADC
and DAC Clock Inputs
Chris Pearson
The latest high performance ADCs cannot realize their THE INNER WORKINGS OF THE
LTC6951
potential without an ultralow jitter high speed clock signal.
Referring to Figure 2, the LTC6951 features
The LTC6951 satisfies the requirements of top ADCs by
two different configurations based on the
producing a clock signal up to 2.7GHz with an impressively setting of the RAO (Reference Aligned
low wideband noise floor. Figure 1 compares the LTC6951s Output) register bit. The desired synchro-
measured ADC SNR results to other ADC clock sources. nization method determines which config-
uration is selected. The LTC6951 is divided
The quantity and performance require- The latest trend in high speed converter
into three main circuit blocks: the phase-
ments for low jitter clocks in electronic digital interfaces is the adoption of the
locked loop (PLL) and voltage controlled
systems continues to increase with system JESD204B standard. Previous generation
oscillator (VCO) section, the clock distribu-
complexity and performance. This may clocking devices are often incompatible
tion section and the digital control section.
result in a costly array of parts, including with the JESD204B standard due to differ-
VCOs, PLLs, clock distribution devices and ent synchronization and output divider The PLL section works in conjunction with
synchronization components to support requirements. The LTC6951 accounts for the external reference and the internal
the clock signals. The LTC6951, on the these differences, making it capable of 4GHz to 5.4GHz VCO to generate the
other hand, decreases complexity and cost supporting JESD204B subclass1. The desired VCO frequency (fVCO) as follows:
by integrating a high performance PLL/ LTC6951 introduces Linears unique for RAO = 0:
VCO, and distributing five ultralow jitter reference alignment synchroniza- f N (1)
fVCO = REF
clock outputs. Additionally, the LTC6951 tion method known as ParallelSync, R
supports several software-based synchroni- which allows parallel LTC6951s to
for RAO = 1:
zation methods: EZSync, ParallelSync clock multiple JESD204B devices. f N P M0
and EZ204Sync (aka EZParallelSync). fVCO = REF (2)
R
Figure1. LTC6951 performance advantage Figure2. LTC6951 block diagram
85 RAO = 0 RAO = 1
LTC6951 LTC6951
LTC6951 PFD PFD
80 REF CP REF CP
jitter = 115fsRMS R DIV R DIV
MEASURED ADC SNR (dBFS)
75
N DIV N DIV
VCO VCO
70 TUNE TUNE
P DIV P DIV
OUT0 OUT0
65 D0 DELAY M0 DIV M0 DIV
Competitors OUT1 OUT1
D1 DELAY M1 DIV D1 DELAY M1 DIV
60 jitter = 140fsRMS
jitter = 200fsRMS
OUT2 OUT2
LTC2107 AIN = 1dBFS D2 DELAY M2 DIV D2 DELAY M2 DIV
55
0 100 200 300 400 500 600 700 800 900 OUT3 OUT3
ADC INPUT FREQUENCY (MHz)
OUT4 OUT4

design features
The LTC6951 produces clock frequencies up to 2.7GHz with the lowest wideband noise
floor in the industry for a clock distribution device. This allows the LTC6951 to directly
clock high speed ADCs with very challenging SNR and clock-to-clock skew targets.
where fref is the reference input frequency, Summary of Linears clock generation and distribution devices
R is the reference input divide value, N

LTC6950 LTC6951 LTC6954 LTC6957
is the PLL feedback divide value, P is
the prescalar divide value, and M0 is the Internal PLL L L
output divider value. When RA0 = 0, N Internal VCO L

is the VCO feedback divide value. When
Output fMAX (MHz) 1400 2700 1800 300
RA0 = 1, the LTC6951 is in reference
Outputs 5 5 3 2
aligned output mode and N P M0 is
the VCO feedback divide value. Reference Max output divide ratio 63 2048 63 1
aligned output mode allows the user EZSync L L L
to align the outputs of one or multiple
ParallelSync L
LTC6951s to the reference input.
JESD204B Subclass 1 compatible L
The clock distribution section receives a
signal at fVCO /P, where P is the P-divider PC-based design, simulation and
ClockWizard LTC6951Wizard LTC6954_GUI
demo board control
value. After the P-divider, the clock signal
is distributed to five separate channels.
When RAO = 0, each of the five channels 4-wire serial interface and a pin to To determine the jitter requirement for an
can independently delay the first synchro- monitor the status of certain register bits. ideal ADC clock input, refer to Equations
nized clock edge by any integer from 0 to 3 and 4. Equation 3 calculates the total
255 P-divider clock cycles. When RAO = 1, PERFORMANCE
clock jitter required to achieve a desired
OUT0s delay option is disabled. After the There is a trade-off between using filtered SNR level at a known full scale analog
delay function, each channel can inde- ADC clocks for optimal SNR performance input frequency. Equation 4 determines
pendently divide the frequency from a or unfiltered ADC clocks for optimal the ADC clock input jitter requirement
list of divider values that range from 1 to clock-to-clock skew performance. There after removing the ADC aperture jitter
512. The output signal from the dividers are several applications with challenging from the total clock jitter. The ADC
is sent to a buffer that determines the clock jitter and clock-to-clock skew aperture jitter number is usually provided
output signal type. Four channels produce requirements. Examples include JESD204B in the ADC data sheet. Equation 3 and
an ultralow noise differential CML clock converters, and multi-arrayed systems Figure 1 highlight that as an ADCs analog
signal capable of output frequencies up such as medical scanners and smart input frequency increases, lower jitter
to 2.7GHz. The fifth channel creates a array antennas. Filtering multiple clocks clocks are required to achieve optimal
differential LVDS output that can produce for performance while accounting for SNR performance. For a more in-depth
clock frequencies up to 800MHz. variations in filter delays to meet skew discussion of clock jitter requirements for
requirements can be problematic. The ADCs refer to the LTC6951 data sheet.
The third and final section is the digital
LTC6951 addresses these design chal-
control section, which controls the SNRdB
lenges by providing multiple CML clock 10 20
various synchronization functions and is tJ(TOTAL) = (3)
outputs with 115fsRMS jitter and 20ps 2 fIN
discussed in detail in the Synchronization
clock skew. For larger arrayed clock
Methods section of this article. The
systems requiring multiple LTC6951s, tJ(CLK _IN) = tJ(TOTAL)2 tJ(APERATURE)2 (4)
digital control section includes a standard
100ps clock skew can be achieved.
fIN = ADC analog input frequency

Table1. Synchronization selection table SYNCHRONIZATION METHODS
EZSync EZSync EZ204Sync The LTC6951 provides three synchroni-

Standalone Multichip ParallelSync (EZParallelSync) zation methods: EZSync, ParallelSync
Clock Reference Reference Divide and EZ204Sync (or EZParallelSync).
Architecture Standalone
Distribution Distribution and Distribution The advantages and disadvantages
Jitter Ultralow Low Ultralow Ultralow of each method are summarized in
Table 1 and in the descriptions below.
Timing requirements Easy Easy Moderate Easy
Phase alignment Yes, Yes, Yes, Yes, phases aligned EZSync Standalone (Figure 3) synchronizes
(all outputs) at Time 0* at Time 0* at Time 0* per LTC6951 sync the LTC6951s five outputs after toggling
*Time 0 alignment implies all outputs requiring synchronization are phase aligned on the same sync event.
the LTC6951s sync pin or the SPI regis-
ter SSYNC bit. This method showcases
the best jitter, clock skew performance
Figure3. EZSync Standalone and easiest synchronization method.
EZSync CONTROLLER
EZSync Multichip (Figure 4) increases the
OUT4+
OUT4 number of synchronized clock outputs
LTC6951
OUT3+ by using the LTC6951 as an EZSync
OUT3 CONTROLLER. This method maintains the
OUT0+ ALIGNS ALL
REF CLK REF
CLOCK EDGES simple EZSync synchronization timing
OUT0 AT t0
requirements. However, for FOLLOWER
OUT1+
OUT1 devices (Figure 4), such as the LTC6950
1ms
SYNC OUT2+ and LTC6954, the clock jitter performance
OUT2
becomes additive in nature, as shown
in Equation 5 and Figure 5. Clock skew
performance depends on several factors,
Figure4. EZSync Multichip including board trace length differences
EZSync CONTROLLER between EZSync devices, FOLLOWER
OUT4+ propagation delays, and individual EZSync
OUT4
LTC6951 device skew performance. The EZSync
OUT3+
OUT3 clock skew performance can be optimized
REF CLK REF OUT0+ using the LTC6951 output delay SPI bits.
OUT0
EZSync FOLLOWER tJ(EZSyncTOTAL) =
OUT1+
OUT1
LTC6954-1
tJ(EZSyncCNTRLLR)2 + tJ(EZSyncFLLWR)2
SYNC OUT2+ OUT0+ (5)
IN+
OUT2 OUT0
1ms IN
OUT1+
OUT1
Figure5. Phase comparison
OUT2+ ALIGNS ALL
SYNC OUT2 CLOCK EDGES 100
AT t0
EZSync FOLLOWER 110
EZSync Multi-Chip
LTC6950 Follower Outputs
120
PHASE NOISE (dBc/Hz)
SYNC PULSE SKEW VCO+ LV/CM+

BETWEEN ANY TWO VCO LV/CM
SYNC PINS 130
MUST BE < 10s PECL0+
PECL0 140
PECL1+
PECL1 150
PECL2+ EZSync Standalone

160
PECL2 ParallelSync
EZ204Sync (EZParallelSync)
PECL3+ 170
SYNC PECL3 1k 10k 100k 1M 10M 40M
OFFSET FREQUENCY (Hz)

design features
ParallelSync synchronization (Figure 6) increases REFERENCE DISTRIBUTION 1F
the number of synchronized clock outputs LTC6954-4 REF+ OUT4+

REF CLK IN 100 OUT4
by distributing the reference to multiple OUT0+
VCC LTC6951
OUT0 REF OUT3+
LTC6951s. This method maintains the 10k
RAO = 1 OUT3
OUT0SEL OUT1+ 1F
LTC6951 jitter performance provided by 10k OUT1 OUT0+
OUT1SEL
the EZSync Standalone method, since OUT0
10k OUT2+
OUT2SEL OUT2 OUT1+
the out of band reference input noise is
OUT1
removed by the LTC6951 loop filter, as
SYNC OUT2+
shown in Figure 5. The synchronization OUT2
ALIGNS ALL
timing requirements are a function of CLOCK EDGES
1F
the reference frequency (refer to Figure 6 AT t0
REF+ OUT4+
for SYNC to REF timing diagram). The 100 OUT4
LTC6951
clock skew performance depends on Figure6. ParallelSync REF OUT3+
RAO = 1 OUT3
1F
board trace length differences between
OUT0+
the reference distribution circuit and OUT0
the LTC6951, reference clock skew and OUT1+
individual LTC6951 output skews. The CK CK OUT1
SYNC
D Q D Q SYNC OUT2+
clock skew performance can be optimized PULSE
OUT2
using the LTC6951 output delay SPI bits.
LTC6951
ParallelSync synchronization uses the REF INPUT
LTC6951s Reference Aligned Output tSS tSS

LTC6951 SYNC TO REF TIMING
mode (RAO = 1 in Figure 2), which SYNC PULSE SYNC HELD HIGH A MINIMUM OF 1ms
(SEE DATASHEET
provides a known latency between the FOR tSH AND tSS)
falling edge of the sync input signal and

the starting edge of all LTC6951 outputs.
Figure 8s ParallelSync timing diagram REFERENCE DISTRIBUTION 1F
explains how outputs from one or LTC6954-4 REF+ OUT4+

100 OUT4
multiple LTC6951s can be programmed OUT0+
REF CLK /2 CLOCK
OUT0 REF LTC6951 OUT3
+
to begin at a desired point in time. OUT3
OUT1+ 1F
RDIV = 1
/32
SYNC OUT1 RAO = 1 OUT0+
EZ204Sync (or EZParallelSync) (Figure 7) is PULSE OUT0
OUT2+
a simple multichip synchronization 1ms SYNC OUT2 OUT1+
method targeted at, but not limited CS OUT1
SPI
SCLK OUT2+
to, JESD204B applications requiring SYNCHRONIZATION STEPS SYNC
1) EZSyncREFERENCE DISTRIBUTION SDI OUT2
CLOCK and SYSREF signals. EZ204Sync 2) SPI SYNCLT6951s
ALIGNS ALL
1F CLOCK EDGES
maintains the jitter performance of
REF+ OUT4+
ParallelSync, but with easier implemen- OUT4
100
tation. This is accomplished by using SYSREF
Figure7. EZ204Sync (EZParallelSync) REF LTC6951 OUT3
+
an EZSync distribution device to act as 1F OUT3

RDIV = 1
an external R-divider to the PLL/VCO RAO = 1 OUT0+
OUT0
reference inputs, as shown in Figure 7.
OUT1+
CS OUT1
The outputs of all PLL/VCOs are phase SPI
SYNC
SCLK OUT2+
aligned. However, this architecture allows SDI OUT2
the phase alignment of the multiple
PLL/VCO devices to take place on any
R-divider cycle. As a result, phase align- power on and off individual LTC6951s individual LTC6951s independently is ideal
ment of each LTC6951 is performed without requiring resynchronization of for JESD204B subclass 1 applications.
independently, enabling the user to all LTC6951s. This ability to synchronize

The LTC6951s variety of synchronization methods
allows designers to optimize for ease of synchronization,
clock jitter and the number of clocks required.
JESD204B INTERFACE
Figure8. ParallelSync timing diagram
JESD204 is a serial data converter digital
SYNC TO REF
interface that has undergone two major
OUTx DELAY SETTING
INPUT
(ADDITIONAL PDIV CYCLES) revisions since its original 2006 specifica-
SETUP TIME
18 PDIV tion. The original goal of JESD204 was
1 RDIV OUTPUT CYCLE CYCLES
to simplify and lower the cost of the
digital interface by reducing the number
SYNC
of converter output pins, FGPA pins and
the board area consumed by routing
REF multiple ADCs to an FPGA. The latest
INPUT revision, JESD204B, added the ability to
establish deterministic latency between
RDIV
OUTPUT a logic device and the data converters.
(INTERNAL
SIGNAL) Over the past few years, a large percent-
age of the new converter ICs and FPGAs
OUT0 have adopted the JESD204B interface.
To enable deterministic latency,

OUT1 JESD204B added two new subclasses,
OUT1 DELAY SETTING = 22
subclass 1 and subclass 2. Subclass 1 is
the preferred method when converter
OUT2
OUT2 DELAY SETTING = 22 clocks are faster than 500Msps.
JESD204B subclass 1 added the align-

OUT3
OUT3 DELAY SETTING = 22
ment signal SYSREF. From the clock ICs
perspective, SYSREF is phase aligned to
the clock signal, and can range from a
single pulse to several pulses at an integer
multiple of the converter clock period.
NOTES:
1. SYNC RISING EDGE (NOT SHOWN) ALIGNS RDIV OUPUT TO REF INPUT As a result, many existing clock devices
2. RDIV = 2 did not have the divider range to support
3. PDIV CYCLE = 500ps (NOT SHOWN)
the JESD204B clock and SYSREF signals.

design features
Over the past few years a large percentage of the new converter ICs and FPGA
have adopted the JESD204B interface. The LTC6951 is JESD204B subclass
1 capable, due to the LTC6951 output divider ranging from 1 to 512.
SYNC SYNC
LANE0 Figure9. LTC6951 EZSync: JESD204B subclass 1 example
LTC2123
LANE1
14-BIT ADC
CLK SYSREF
OUT2
OUT3 FPGA CLK
LTC6951
REF CLK REF 1:3
OUT0 SYSREF FPGA
BUFFER
OUT4 MGMT CLK FPGA

OUT1 SYNC SYNC
CLK SYSREF LANE0
LTC2123 #2
LANE1
LTC2123 14-BIT ADC
LANE2
14-BIT ADC
LANE3 CLK SYSREF
SYNC SYNC
REF OUT0
LTC6951 OUT3
#1 OUT1 SYSREF
SYNC OUT2 FPGA CLK
OUT4 MGMT CLK
SYNC SYNC
LANE2
LTC2123 #2
The LTC6951 is JESD204B subclass 1 14-BIT ADC
LANE3
capable, due to the LTC6951 output CLK SYSREF

divider range extending from 1 to 512. REF CLK REF OUT0
In addition to Figure 7s EZ204Sync LTC6951 OUT3
#2 OUT1
example, Figure 9 provides an EZSync LTC6951 SYNC SYNC OUT2
Standalone example of a LTC6951 clock- (ALIGNED TO OUT4
REF CLK) CLK SYSREF
ing two JESD204B converters. Figure 10 LTC2123 #3
LANE4
14-BIT ADC
shows a ParallelSync example of multiple LANE5
SYNC SYNC
LTC6951s clocking several JESD converters.
REPEAT LTC6951 AND ADC SCHEMATIC
SYNC SYNC
LANE(4N 6)
LTC2123 (2N 2)
LANE(4N 5)
14-BIT ADC
CLK SYSREF
REF OUT0
LTC6951 OUT3
#N OUT1
Figure10. LTC6951 ParallelSync: JESD204B subclass 1 example SYNC OUT2
OUT4 CLK SYSREF
LTC2123 (2N 1)
LANE(4N 4)
14-BIT ADC
LANE(4N 3)
SYNC SYNC

For initial evaluation, the LTC6951Wizard provides
register settings files that are based off the LTC6951
data sheet examples and typical application circuits.
TOOLS For initial evaluation, the LTC6951Wizard CONCLUSION
The LTC6951 demo board (www.linear. provides register settings files that The LTC6951 produces clock frequencies
com/ product/LTC6951#demoboards) and are based on the LTC6951 data sheet up to 2.7GHz with the lowest wideband
the LTC6951Wizard greatly simplify examples and typical application noise floor in the industry for a clock
evaluation and design. These tools can: circuits. To evaluate a custom frequency distribution device. This allows the
plan, the LTC6951Wizard provides a LTC6951 to directly clock high speed ADCs
Read/write to the LTC6951
Help file with step-by-step examples with very challenging SNR and clock-
SPI registers (Figure 11)
using the LTC6951Wizard to calculate to-clock skew targets. The LTC6951s
Calculate registers settings and register settings, design the loop filter variety of synchronization methods
design loop filters based on a and program the LTC6951 SPI regis- allows designers to optimize for ease
frequency plan (Figure 12) ters. Download the LTC6951Wizard at of synchronization, clock jitter and the
Simulate time and frequency domain www.linear.com/LTC6951Wizard. number of clocks required. The LTC6951
response based on register settings supports JESD204B subclass 1 converter
and loop filter design (Figure 12) clock schemes. To further simplify
design, the LTC6951Wizard is provided to
guide the user through design, simula-
tion and evaluation of the LTC6951. n
Figure 11. LTC6951Wizard settings

design features
To evaluate a custom frequency plan, the LTC6951Wizard provides a Help file

with step-by-step examples using the LTC6951Wizard to calculate register
settings, design loop filter and program the LTC6951 SPI registers.
Figure12. LTC6951Wizard loop filter design and simulation

1.5A, Negative Regulator Expands Family of Current-
Reference Linear Regulators
Dawson Huang
The LT3080, introduced in 2007, represented a new linear regulator architecture featuring
a current source as reference and a voltage follower for the output amplifier. This new
architecture has a number of advantages, including easy regulator paralleling for increased
output current and operation down to zero output voltage. Since the output amplifier always
operates at unity gain without a resistor-setting divider, bandwidth and absolute regulation
are constant across the output voltage range. Transient response is independent of output
voltage and regulation can be specified in millivolts rather than as a percent of output.
Table 1 summarizes the family of devices the family, the LT3090, but with more keep it from overheating when support-
that use this architecture. The LT3091, than double the LT3090s current rating. ing loads up to 1.5A. Built-in protec-
the latest addition to this family, is a 1.5A tion includes reverse output protection,
The LT3091 is useful in high current,
low dropout negative linear regulator internal current limit with foldback and
negative voltage applications requiring
featuring adjustable current limit and thermal shutdown with hysteresis. This
low noise or precision output. It features
current monitor. The LT3091 is similar versatile negative regulator architecture
fast transient response, high PSRR and
to the other negative linear regulator in can operate down to zero volts out
low output noise. Low dropout helps
and as a negative floating regulator.
Figure 1. 1.5A, negative linear
TO ADC (IMON)
HOW IT WORKS
regulator with current limitation and RSET
0.1F RMON
49.9k
monitor
6.65k 10F The negative output voltage is set with
a 50 A precision current source driven
VOUT
SET GND IMONP OUT
LT3091 2.5V through a single resistor RSET from ground
MAX IOUT
1.5A to the SET pin. The internal follower
+
amplifier forces the output voltage to
match the negative voltage of the SET
50A
pin. With this architecture, all of the
10F
VIN IN
IMONN 3.3V
internal operating current flows in from
3V TO 10V
SHDN ILIM 0.1F the output pin. Only a 20 A load is
required to maintain regulation at all
RLIM 5k
output voltages. Figure 1 shows the basic
hookup for the LT3091. It provides 1.5A
Table1. Some of Linears regulators featuring the current reference architecture of output current, can be adjustable to
zero output voltage, and features both
LT3091 LT3090 LT3081 LT3080
positive and negative monitors for output
Output current 1.5A 600mA 1.5A 1.1A current. It is also reverse protected, when
I SET 50A 50A 50A 10A output voltage is lower than input.
Adjustable current limit/current monitor Yes/Yes Yes/Yes Yes/Yes No/No The current limit can be reduced
LDO (low dropout) Yes Yes No Yes below 1.5A by connecting an external
resistor RLIM between ILIM and IN pins,
Positive/Negative voltage Negative Negative Positive Positive

design features
This regulator is easy to parallel to increase

output current. It can be used for power supplies
capable of sinking and sourcing current.
as shown in Figure 1. This function

RSET
can effectively protect the load and 0.1F 24.9k 22F
1%
limit the temperature of the IC.
ROUT1
VOUT
LT3091 SET GND IMONN OUT 10m
2.5V
With 3.3V feeding the IMONN pin, the U1 MAX IOUT
3A
IMONP pin sources current equal to 000 +
of the output current. This current source
is measured by tying a resistor, RMON , to
ground in series with the current source 22F 50A
and reading the voltage across the resis- VIN
IN
tor. With the IMONP pin tied to VIN , the 3.3V

SHDN IMONP ILIM
IMONN pin sinks current equal to 000 of 5k
the output current. In this way, positive or
negative output current can be monitored
ROUT2
with minimal components, no additional LT3091 GND IMONN OUT 10m
sense resistors or amplifiers required. U2
SET
+
PARALLELING DEVICES FOR MORE Figure 2. 3A negative linear
CURRENT regulator with paralleled

LT3091
Paralleling LT3091s is easy with this 50A
new current source reference regulator. IN
Paralleling is useful for increasing output SHDN IMONP ILIM

current or spreading heat. Since the 5k
LT3091 is set up as a voltage follower,
tying all the SET pins together makes
the outputs the same voltage. If the Figure 3. Thermal
outputs are at the same voltage, only performance of two
paralleled LT3091s
a few milliohms of ballast, ROUT1,2 , are
required to allow them to share current.
Figure 2 shows a schematic of two

LT3091s paralleled to obtain 3A output.
The set resistor, RSET, now has twice
U1 U2
the set current flowing through it, so 52C 53C
the output is 100 A times RSET. The

10m output resistors, ROUT1,2 ensure
ballasting at full current. There is no

limit to the number of devices that
can be paralleled for higher current.

Figure 3 shows the thermal distribution and quiet solution. Figure 5 shows the of the negative rail. Figure 9 shows the
of the design of Figure 2U1 and transient response of the two output temperature of the entire system.
U2 reach similar temperatures, indi- voltages. Figure 6 shows the thermal
This setup can be used as an operational
cating equally shared current. performance of the entire system.
amplifier power supplywhere a high
LOW NOISE POSITIVE-TO-NEGATIVE LOW NOISE POSITIVE AND NEGATIVE speed operational amplifier requires a low
CONVERTER POWER SUPPLY noise, high speed 3.3V power supply.
Inverting converters generate a negative A high current positive-to-positive-and-
CONCLUSION
voltage from a positive input, and feature negative converter can be built with a
low output ripple. If combined with a positive 1.5A LT3081 linear regulator and The LT3091 is a 1.5A, low dropout, current
high bandwidth LDO such as the LT3091, its negative 1.5A linear counterpart, the reference negative linear regulator. This
the overall converter can have very high LT3091. The LT8582 is a dual-channel PWM regulator is easy to parallel to increase
transient response with even lower noise. DC/DC converter with internal switches in output current. It also features fast tran-
an available 7mm 4mm DFN package. sient response, high PSRR and low output
Figure 4 shows a low noise coupled- noise, making it ideal as a post regulator.
It can generate both a positive and a
inductor positive-to-negative converter. It can be used for power supplies capable
negative output from a single input.
The inverting converter is based on of sinking and sourcing current. n
LT3581, a PWM DC/DC converter with Figure 7 shows a 1.5A 12V-to-3.3V
built-in power switch. Its 4mm 3mm low noise power supply using
DFN package and tiny externals can be the LT8582, LT3081 and LT3091.
combined with the LT3091 in a compact Figure 8 shows the transient response
Figure 4. 1.5A low noise and fast transient

positive-to-negative converter
C2 VOUT1
L1A L1B 5V 0.1F 49.9k 10F
1F 1%
3.3H 3.3H 1.5A 1206
VIN

12V
D1
VOUT2
SW1 SW2 LT3091 SET GND IMONN OUT
2.5V
MAX IOUT
VIN LT3581 FB 1.5A
60.4k +
SHDN GATE
C1 100k C3
22F FAULT 22F
CLKOUT
RT VC
10F 50A
C1: 22F, 25V, X7R, 1210 56pF 6.8k 1206
C2: 1F, 50V, X7R, 1206 124k SYNC SS IN
C3: 22F, 16V, X7R, 1210 GND 0.1F 3.3nF
D1: CENTRAL CMSH3-40FL
L1: COILCRAFT MSD7342-332MLB SHDN IMONP ILIM
5k
Figure 5. Transient response for positive-to-negative Figure 6. Thermal image

converter for positive-to-negative
converter
VOUT1
100mV/DIV LT3581 54C
(AC COUPLED)
VOUT2 D1: 54C
100mV/DIV
(AC COUPLED) L1: 64C
LT3091 83C
IOUT
1A/DIV
100s/DIV

design features
The LT3091 is useful in high current, negative voltage applications requiring

low noise or precision output. It features fast transient response, high
PSRR and low output noise, making it ideal as a post regulator. Low
dropout helps keep it from overheating when supporting 1.5A loads.
Figure 7. 12V to 3.3V low noise power supply
10F
C1
L1A 2.2F VOUT1'
4.7H D1 IN
VIN 5V LT3081

12V
CIN1 ISET
22F 50A
SWA1 SWB1 L1B
4.7H
+
45.3k
VIN1 FBX1
COUT1
SHDN1 GATE1 22F VOUT2'
100k 2 OUT 3.3V
PG1 VC1 MAX IOUT
LT8582 SET TEMP IMON ILIM 1.5A
SYNC1 SS1 13k 47pF
CLKOUT1 RT1 0.1F
66.5k 22F
115k 0.1F
1.5nF 1%
CLKOUT2
GND
SYNC2
115k 2.2nF 66.5k
100k 0.1F
47pF 1%
PG2 RT2 0.1F 22F
18.7k
SHDN2 SS2
VOUT2
LT3091 SET GND IMONN OUT
VIN2 VC2 3.3V
COUT2 MAX IOUT
22F 1.5A
GATE2
60.4k
2 +
FBX2
SWA2 SWB2
L2A
C2
L2B
2.2F
4.7H 4.7H
50A

10F
CIN2 VOUT1
D2 IN
22F 5V
CIN1, CIN2: 22F, 25V, X7R, 1210
COUT1, COUT2: 22F, 16V, X7R, 1210
SHDN IMONP ILIM
C1, C2: 2.2F, 50V, X7R, 1206
D1, D2: CENTRAL CMSH3-40FL 5k
L1, L2: WRTH WE TDC 74489440047
Figure 8. Transient response at VOUT2 load transient Figure 9. Thermal image

for 12V to 3.3V low noise
power supply
LT3081 75C
VOUT1
100mV/DIV
(AC COUPLED)
VOUT2
100mV/DIV LT8582 81C
(AC COUPLED)
IOUT
1A/DIV
LT3091 83C
100s/DIV

Whats New with LTspice IV?
Gabino Alonso
Blog by Engineers, for Engineers

Follow @LTspice at www.twitter.com/LTspice
www.linear.com/solutions/LTspice Like us at facebook.com/LTspice
NEW VIDEO: BEHAVIORAL VOLTAGE LTM4622: Dual step-down regulator 4-Quadrant Converter
SOURCES by Simon Bramble (3.6V20V to 3.3V & 1.2V at 2.5A) LT8714: Synchronous four quadrant
Nearly all circuit simulations require www.linear.com/solutions/5847 converter with power good indication
a voltage source. This video reveals (10V14V to 5V to 5V at 5A to 5A)
LTM4675: Paralleled Module
some of the undiscovered talents of the www.linear.com/solutions/6004
buck regulator with digital
not-so-humble LTspice voltage source, interface (10V14V to 1V at 72A) Operational Amplifier
specifically exploring the power of the www.linear.com/solutions/5833 LTC6268-10: Oscilloscope differential probe
behavioral voltage source. A behavioral
www.linear.com/solutions/6058
voltage source outputs a voltage according Boost Regulators
to any number of circuit parameters, and LT3095: Dual low noise, low ripple bias SELECTED MODELS
it can be used to unleash the real math- generator (3V20V to 5V & 15V at 50m A)
To search the LTspice library for a
ematical power of LTspice. www.linear.com/solutions/6001
particular device model, press F2. Since
www.linear.com/solutions/6106 LT8331: 120V boost converter LTspice is often updated with new
(36V72V to 120V at 60m A) features and models, it is good practice to
SELECTED DEMO CIRCUITS
www.linear.com/solutions/6022 update to the current version by choosing
For a complete list of example simula-
Sync Release from the Tools menu.
tions utilizing Linear Technologys devices, SEPIC Regulator
please visit www.linear.com/democircuits. LT8331: 48V SEPIC converter Buck Regulators

(36V72V to 48V at 165m A) LT8641: 65V, 3.5A synchronous step-down
Buck Regulators www.linear.com/solutions/6019 Silent Switcher with 2.5 A quiescent
LT8602: Automotive quad buck regulator
current www.linear.com/LT8641
(5.5V42V to 5V at 1.5A, 3.3V at Buck-Boost Regulator
LTM8055: Paralleled synchronous LTM4650: Dual 25A or single 50A
2.5A, 1.8V at 1.8A, 1.25V at 1.8A)
www.linear.com/solutions/5835 buck-boost regulator with accurate DC/DC Module regulator
current limit (7V36V to 12V at 12A) www.linear.com/LTM4650
LTC3649: High voltage monolithic
synchronous buck regulator with cable Inverting Buck Regulator
drop compensation (4V60V to 5V at 4A) LTC7149: 60V, 4A synchronous step-
www.linear.com/solutions/7117 down regulator for inverting outputs
www.linear.com/LTC7149
Isolated Flyback Converter

LTM8068: 2.8V to 40V input isolated
What is LTspice IV? Module DC/DC converter with LDO

post regulator www.linear.com/LTM8068
LTspice IV is a high performance SPICE simulator, schematic capture and waveform viewer designed to speed
the process of power supply design. LTspiceIV adds enhancements and models to SPICE, significantly reducing Charge Pumps
simulation time compared to typical SPICE simulators, allowing one to view waveforms for most switching LTC3265: Low noise dual supply with
regulators in minutes compared to hours for other SPICE simulators.
boost and inverting charge pumps
LTspice IV is available free from Linear Technology at www.linear.com/LTspice. Included in the download is a
www.linear.com/LTC3265
complete working version of LTspice IV, macro models for Linear Technologys power products, over 200 op amp
models, as well as models for resistors, transistors and MOSFETs.

design ideas
Hot Swap Controller Ideal Diode-OR Controller Comparator

LTC4281: Hot swap controller LTC4371: Dual negative voltage ideal LTC6754: High speed rail-to-rail input
with I2C compatible monitoring diode-OR controller and monitor comparator with LVDS compatible
www.linear.com/LTC4281 www.linear.com/LTC4371 outputs www.linear.com/LTC6754
PoE Powered Device Op Amp Voltage Reference

LT6375: 270V common mode LT6657: 1.5ppm/C drift, low
LT4276A: LTPoE++/PoE+/PoE PD forward/
flyback controller www.linear.com/LT4276 voltage difference amplifier noise, buffered reference
www.linear.com/LT6375 www.linear.com/LT6657 n
Power User Tip

AC ANALYSIS USING THE STEP COMMAND
In LTspice, AC analysis involves computing the AC 10pF to .5nF with 30 points per octave using the .step The beauty of single frequency analysis with a .step
complex node voltages as a function of frequency directive (press S to insert a spice directive in the command is that the resulting plot shows magnitude
using an independent voltage or current source as schematic editor): and phase as a function of parameter sweep, not
the driving signal. The small signal analysis results .step oct param C 10p .5n 30 frequency. Below is the result of a simulation using
are plotted in the waveform viewer as magnitude and a single frequency analysis where the x-axis is the
The schematic for this case and its resulting waveform
phase over frequency. capacitance sweep as defined in the .step function.
are shown below.
AC analysis in LTspice has a number of settings: the
Note that using a .step command with AC analysis
x-axis scaling (linear, octave or decade), number of
can drastically increase simulation time, so carefully
simulation points and frequency range. For example, if
choose the values, ranges, increments, and frequency
you want to see how your circuit performs from 100Hz
range for each parameter sweep.
to 1MHz with 1,000 points per decade you would edit
your simulation command to the following: Single Frequency Analysis with a Swept Parameter
.ac dec 1K 100 1Meg LTspice offers an elegant solution for holding frequency
constant and performing small signal analysis over
Repeated AC Analysis with Parameter Sweeps a varying parameter. It is as simple as using the list
AC analysis usually involves using fixed parameters AC Analysis option in the simulation command, and
to calculate the small signal AC response of a circuit, specifying the frequency at which you want to perform
but you may want to refine your design by viewing the analysis, in this case, 1MHz:
the response under varying parameters. This can be
.step oct param C 10p .5n 30
accomplished by stepping the parameter of interest
.ac list 1Meg AC analysis commands can be edited using the
using a .step command. For example, you could sweep
Edit Simulation Command dialog.
a capacitance logarithmically through the range of
Happy simulations!
Repeated AC analysis with stepped capacitance
Single frequency analysis with swept capacitance
The x-axis is capacitance as

defined by the .step command.

Easy Balanced Load Sharing for Three or Four Supplies,
Even with Unequal Supply Voltages
Vladimir Ostrerov and Chris Umminger
Using multiple small power supplies is often more of the total load current equally. The
economical and more reliable than using a single large output voltage at the load is less than
the minimum of the supply voltages V1,
power supply. For instance, separate batteries can be
V2 and V3. Because there are two stages
used for higher reliability. In a multi-supply system, it of cascading, it is possible to have as
is important that the load is equally shared; otherwise, much as 1V difference between V3 and
one supply may attempt to carry the entire load. V1 or V2, if the difference between V1
This article shows how to easily load balance three and V2 is already at the 0.5V limit.
or four supplies by cascading LTC4370 circuits. BALANCING THE LOAD BETWEEN
FOUR SUPPLIES
The LTC4370 controller enables current LTC4370 can regulate its output to match
sharing between two supplies with a the lower value rail, set by adding an Cascading three LTC4370 controllers
modest difference between the output appropriate resistor on the RANGE pin. (Figure 2) allows four supplies to share
voltages, as shown in Figure 1. To perfectly the load. In the first stage, U1 and U2
BALANCING THE LOAD BETWEEN force equal sharing between a pair of
balance the current in both sides, the
THREE SUPPLIES WITH TWO
controller regulates the gate-source voltage supplies, where the output current of U1 is
CASCADED LTC4370s
of an N-channel MOSFET in whichever I12 = I1 + I2 , and the output current of U2
Figure 2 shows a 3-input, 12V system is I34 = I3 + I4 . A third LTC4370, the second
side has the higher voltage. This creates
delivering 10A. Notice that one LTC4370 stage, keeps I12 = I34 . Thus, each supply
a voltage drop across the MOSFETs
(U1) performs equal current sharing contributes one fourth of the total load
RDS(ON) plus the current sense resistor.
between supplies V1 and V2, while the current. The two stages, as above, allow
The LTC4370 can compensate for a voltage second LTC4370 (U2) implements a 2:1 the possibility of as much as 1V differ-
difference between two rails of up to relation between the output current of ence between the four supply voltages.
0.5V. If the voltage difference of the two U1 and the current of a third supply, V3.
supplies is somewhat less than 0.5V, the Thus, each supply contributes one third LIMITATIONS
The main error sources that affect

perfect current sharing are:
Figure1. The LTC4370 current- 5A
balancing controller enables balanced + 325mV LTC4370 error amplifier input
load sharing between two supplies, SUM85N03-06P
12.2V offset, 2mV (maximum)
even when their voltage outputs are 39nF*
different. Sense resistor tolerance, worst-case
EN1 CPO1 VIN1 GATE1 for 1% resistors is 2% overall.
11.875V
OUT1
VCC
2m
Sharing error attributed to the error
0.1F FETON1
GND LTC4370 10A amplifier input offset decreases with
FETON2 2m
NC RANGE 11.875V increasing sense voltage, but power
OUT2
EN2 CPO2 VIN2 GATE2 COMP dissipation increases. For the simple
39nF* 0.18F LTC4370 circuit with two supplies, this
error is expressed as an imbalance in
11.9V
SUM85N03-06P the supplies sharing of current:
+ 25mV
*OPTIONAL, FOR FAST TURN-ON
5A

design ideas
SUM85N03-06P
12.4V I = I1 I2
39nF 50V
Using the worst-case errors,

EN1 EN1 CPO1 VIN1 GATE1 above, the error is:
10k OUT1 I1 = ILOAD
FETON1 2m 2mV
VCC VCC
U1 I + 0.01 ILOAD [A]
0.1F
GND
LTC4370 FETON2 2m I12 = I1 + I2 = ILOAD
RSENSE
I2 = ILOAD
NC RANGE OUT2
For the circuit of Figure 2, where ideal
EN2 EN2 CPO2 VIN2 GATE2 COMP CCOMP
10k 39nF 50V 0.18F load sharing means the load is distrib-
RCOMP
15k uted into 13ILOAD and 23ILOAD , it is easier
12.0V
Figure2. Two LTC4370s SUM85N03-06P to estimate the worst-case imbalance
can be cascaded to
via an expression of the maximum and
enable current sharing
of three supplies. SUM85N03-06P minimum current of each supply:
39nF 50V
2mV
IMAX = 0.672 ILOAD + [A]
3.01 RSENSE
EN1 EN1 CPO1 VIN1 GATE1
10k OUT1 I12 = I1 + I2 = ILOAD 2mV
IMIN = 0.328 ILOAD + [A]
VCC VCC FETON1 2m ILOAD 3.01 RSENSE
U2
0.1F LTC4370
GND FETON2 4m
NC RANGE OUT2
I3 = ILOAD CONCLUSION
10k 0.18F By cascading the shared output of one
39nF 50V
RCOMP
15k LTC4370 with another LTC4370, three or
12.0V more supplies can be efficiently controlled
SUM85N03-06P
to provide equal current to the load. With
errors on the order of the sense resistor
tolerance, the voltage drop is minimal. n
SUM85N03-06P
V1
39nF 50V
EN1 EN1 CPO1 VIN1 GATE1

10k OUT1 I1 = ILOAD
I12 = I1 + I2 = ILOAD
VCC VCC FETON1 2m
U1
0.1F LTC4370
GND FETON2 2m SUM85N03-06P
I1 = ILOAD 39nF 50V
NC RANGE OUT2
10k 39nF 50V 0.18F
RCOMP EN1 EN1 CPO1 VIN1 GATE1
15k 10k OUT1 I12 = ILOAD
Figure3. Four supplies V2
can each support an equal SUM85N03-06P FETON1 2m ILOAD
VCC VCC
U3
share of a load by using 0.1F LTC4370
SUM85N03-06P GND FETON2 2m
three LTC4370s in a 2-stage V3
39nF 50V I34 = ILOAD
cascade. NC RANGE OUT2
10k 39nF 50V 0.18F
EN1 EN1 CPO1 VIN1 GATE1 RCOMP
10k OUT1 15k
I3 = ILOAD
VCC VCC FETON1 2m SUM85N03-06P

U2
0.1F LTC4370
GND FETON2 2m I34 = I3 + I4 = ILOAD
I4 = ILOAD
NC RANGE OUT2
10k 39nF 50V 0.18F
RCOMP
15k
V4
SUM85N03-06P

Design Once; Use Twice: Monolithic SEPIC/Boost Regulators
with Wide VIN Range Satisfy Requirements of Both Consumer
and Commercial Vehicles
Molly Zhu
Automobile manufacturers continually add electronic control units (ECUs) to support

increasing numbers of performance, comfort and safety features. ECU power either
comes from a single lead-acid battery in consumer vehicles, or from two batteries in
commercial vehicles. Ideally, an ECU can run off either, enabling a single design for
both consumer and commercial vehicles. This requires that ECU power ICs support
an input range covering both configurationsnamely 3.5V to 60V. Furthermore,
the power ICs should feature ultralow quiescent current, preserving the vehicles
battery run time when the engine is off, but always-on systems remain engaged.
The LT8495 and LT8494 are high voltage supply voltage is monitored by power- integrated power switch drivers can
switching regulators that meet these on reset, and the software/hardware operate from either of two supplies: VIN
requirements when configured as activities are supervised by watchdog or BIAS. This allows the part to optimize
SEPIC or boost converters. Both parts timers. These functions are integrated efficiency and reduces the minimum
operate over 2.5V to 60V input, and in the LT8495, simplifying designs with input voltage requirement. The LT8494/
have low quiescent current to extend enhanced safety and reliability. LT8495 automatically chooses the lower
the battery life. The quiescent current supply of the two, provided it is in the
DUAL SUPPLY PINS
of the LT8495 is 9 A, and is 7 A for the operation range. This selection is made
LT8494. The parts are available in 20-lead The input voltage of the LT8494/LT8495 on-the-fly as VIN or BIAS voltages change.
QFN and 20-lead TSSOP packages. can be as high as 60V for SEPIC topolo- After initial start-up, the part can draw
gies, and 32V for boost circuits with the current from BIAS if it is lower than VIN .
The LT8494 and LT8495 are similar, but 60V ride-through voltage. The internal
the LT8495 adds power-on reset and power switch driver must be in the A typical application of a boost converter
watchdog timers. It is designed specifically 2.4V~34V (typical) range to enable the using the LT8494 is shown in Figure 1.
for microcontrolled applications, where LT8494/LT8495, but the minimum operat- The BIAS pin is connected to ground
reliability and safety are critical. The ing VIN range can be reduced to 1V. The instead of the output since the input
Figure1. The LT8494 in a 750kHz, 48V boost converter Figure2. Efficiency of the circuit in Figure 1
100
L1
22H D1
VIN VOUT
16V TO 32V 48V 95
1M 10pF 0.5A
SW 90
EFFICIENCY (%)
VIN FB
SWEN
LT8494 25.5k
PG 85
C1 C2
2.2F RT SS GND BIAS 4.7F
2 80
93.1k 0.2F
75
C1: 2.2F, 50V, X5R, 1206

C2: 4.7F, 100V, X7R, 1210 70
D1: ONSEMI MBRA2H100 0 100 200 300 400 500
L1: WRTH LHMI 74437349220 LOAD CURRENT (mA)

design ideas
RSTIN 1.1V WDI
RST WDO
tUV tRST
tWDL< t < tWDU t < tWDL t > tWDU
tRST tRST
tUV = TIME REQUIRED TO ASSERT RST LOW AFTER RSTIN tWDU = WATCHDOG UPPER BOUNDARY PERIOD, APPROXIMATELY 31 RAMPING CYCLES ON CWDT PIN
GOES BELOW ITS THRESHOLD, APPROXIMATELY 23s tWDL = WATCHDOG LOWER BOUNDARY PERIOD, APPROXIMATELY 1 RAMPING CYCLE ON CWDT PIN
tRST = PROGRAMMED RESET PERIOD
(a) (b)
Figure3. POR (a) and watchdog (b) timing
voltage is always lower than the output. pin is released after the reset delay time. by the RSTIN pin, and the watchdog
The efficiency is given in Figure 2. At The reset delay time, tRST, is program- timer supervises the microcontroller.
very light load, the efficiency of the mable through the cap on the CPOR pin.
CONCLUSION
LT8494 is slightly higher than that of
The LT8495s watchdog timer includes The LT8494 and LT8495 are monolithic
the LT8495 because the LT8494 is not
an independent enable pin (WDE), and boost/SEPIC switching regulators with
supporting a watchdog function.
can operate without the VIN supply. If input voltage ranges of 1V to 60V after
WATCHDOG TIMER AND POR the time between the negative edges start-up. Both parts can automatically
FUNCTIONS on the WDI is too long or too short, select the lower supply pins, VIN or BIAS,
The LT8495 is similar to the LT8494, but the WDO pin is pulled low for the reset to improve efficiency. The LT8495 features
it adds integrated power-on reset (POR) delay time, tRST, before it is released. an integrated power-on reset and a watch-
and watchdog timer functions to enhance The window time of WDI can be dog timer to monitor the microcontrollers
system safety in automotive applications. programmed through the cap on CWDT activity. Their wide input voltage ranges,
The POR monitors the supply voltages, pin. The timing diagrams of the POR and high efficiency, low quiescent current and
while the watchdog timer monitors the watchdog timer are shown in Figure 3. programmable timing make them ideal for
software and hardware functions. industrial and automotive applications. n
Figure 4 shows the LT8495 configured as
The LT8495 monitors the output via the a SEPIC converter with a 3V60V input
RSTIN pin voltage. During normal opera- voltage and 5V output. The max load
tion, if the voltage of the RSTIN is below its current increases with the input voltage
threshold, the RST pin is asserted low. Once until reaching the full load current of 1A at
the RSTIN rises above its threshold, the RST 12V input. The output voltage is monitored
C3
L1 VOUT
2.2F D1
15H 5V
Figure4. The LT8495 in a 450kHz, 5V VIN 0.4A (VIN = 3V)
3V TO 60V
output SEPIC converter with POR 0.6A (VIN = 5V)
C1 L2 1M 1.0A (VIN > 12V)
and watchdog timer
2.2F 15H
4.7pF C2
47F 2
SW BIAS 8.87k
VIN RSTIN
FB
SWEN
316k
GND
CWDT LT8495
CPOR
1nF WDO
SS
WDE
C
4.7nF RT RST C1, C3: 2.2F, 100V, X5R, 1206
C2: TAIYO YUDEN, EMK325BJ476MM-T
1F 169k WDI
D1: ONSEMI MBRA2H100
L1, L2: COILTRONICS DRQ125-150-R

New Product Briefs
270V COMMON MODE DIFFERENCE and speed can be optimized for specific For noise-sensitive applications, the
AMPLIFIER FEATURES 97dB MIN input range requirements. For example, LT8602 utilizes its pulse-skipping mode
CMRR, 35PPM MAX GAIN ERROR
if the input common mode range is to minimize switching noise and meet
The LT6375 is a unity-gain difference 80V, a resistor divider ratio of seven the CISPR25, Class 5 EMI requirements.
amplifier with integrated precision can be selected to achieve lower noise, Switching frequency can be programmed
matched resistors, which precisely level lower offset and wider bandwidth than from 250kHz to 2.2MHz and is synchro-
shifts and buffers small difference signals is achievable with a ratio of 20. nizable throughout this range.
while rejecting up to 270V common
The LT6375 includes many other useful The LT8602s 60ns minimum on-time
mode. The A-grade version achieves
features, including rail-to-rail outputs, enables 16V VIN to 0.8V VOUT step-
unprecedented performance: CMRR is
low supply current and a shutdown down conversions while switching at
97dB (min), initial gain error is 35ppm
mode. It is available in a 4mm 4mm 2MHz , enabling designers to avoid
(max), gain drift is 1ppm/C (max) and
12-lead DFN and a 4mm long MSOP critical noise-sensitive frequency
gain nonlinearity is 2ppm (max) with a
package with 12 leads. Both pack- bands such as AM radio, while using
common mode divide ratio of 25:1. The
ages include skipped leads for extra a very compact solution footprint.
common mode divide ratio is selectable
spacing of high voltage input signals.
from 7:1 to 25:1, enabling the designer to Its 3V to 42V input voltage range makes
select the ratio with the best performance 42V QUAD SYNCHRONOUS it ideal for automotive applications that
for a given common mode input range. STEP-DOWN DC/DC CONVERTER must regulate through cold-crank and
DELIVERS 93% EFFICIENCY & stop-start scenarios with minimum input
At the heart of the LT6375 is a high OPERATES FROM 3V TO 42V INPUTS
voltages as low as 3V and load dump
precision Over-The-Top amplifier which
The LT8602 is a 42V input capable, high transients in excess of 40V. Each channel
operates with inputs both within and
efficiency quad output synchronous of the LT8602 maintains a minimum
above the 3.3V to 50V supply voltage.
monolithic step-down switching regula- dropout voltage of only 200mV (at 1A)
This permits the combination of a wide
tor. Its quad channel design combines under all conditions, enabling it to excel
input range and low voltage supply.
two high voltage 2.5A and 1.5A channels in scenarios such as automotive cold-
Use of a low voltage supply limits
with two lower voltage 1.8A channels crank. Programmable power-on reset
power consumption and protects down-
to provide four independent outputs, and power good indicators for each
stream circuitry from high voltage.
delivering voltages as low as 0.8V. channel ensure overall system reliability.
The LT6375 combines a high preci-
Its synchronous rectification topology The LT8602s 40-lead thermally enhanced
sion, wide voltage range Over-The-Top
delivers up to 93% efficiency while 6mm 6mm QFN package and high
amplifier with configurable precision
Burst Mode operation keeps quiescent switching frequency keep external induc-
matched resistors, says Maziar Tavakoli,
current under 30 A (all channels) in tors and capacitors small, providing a
Design Manager, Signal Conditioning
no-load standby conditions, making compact, thermally efficient footprint.
Products. With seven different divider
it ideal for always-on systems.
ratios to choose from, precision, noise

product briefs
5W AutoResonant WIRELESS POWER The LTC4125 automatically adjusts its range of transmit-to-receive coil coupling
TRANSMITTER FEATURES FOREIGN drive frequency to match the LC network factorsno complicated signal process-
OBJECT DETECTION, COMPLETES
resonant frequency. AutoResonant switching hardware and software is needed.
LINEAR CHARGING SOLUTIONS
ing enables the device to deliver maximum
The LTC4125 is a wireless power transmit- The LTC4125 includes a programmable
power from a low voltage input supply
ter that complements Linears wireless maximum current limit and an NTC input
(3V to 5.5V) to a tuned receiver such as
receiver ICs in wireless charging solutions. as additional means of foreign object
Linears LTC4120 wireless receiver and
The LTC4125 is a high performance and overload protection. Applications
battery charger via loosely coupled coils.
monolithic full bridge resonant driver, include handheld instruments, industrial/
capable of delivering up to 5W of power Wireless power receivers can also be military sensors for harsh environments,
wirelessly to a companion receiver. It func- designed with the LTC4071 shunt battery portable medical devices and electrically
tions as the transmit circuit component in charger or the LT3652HV multi-chemistry isolated devices. LTC4125-based systems
a complete wireless power transfer system battery charger. To optimize system enable robust, standalone solutions
comprised of transmit circuitry, transmit efficiency, the LTC4125 employs a periodic capable of large transmission distances
coil, receive coil and receive circuitry. transmit power search and adjusts the up to 10mm, which also tolerate poor
transmission power based on the receiver coil coupling due to misalignment.
The LTC4125 wireless power transmitter load requirements. The device stops
improves on a basic transmitter by The LTC4125 is housed in a low profile
delivering power in a fault condition, or
providing three key features: (0.75mm) 20-pin 4mm 5mm QFN
if a conductive foreign object is detected.
package with backside metal pad for
The AutoResonant function maximizes
It is surprisingly easy to design an entirely excellent thermal performance. n
available receiver power
analog wireless power system using the
The optimum power search algorithm LTC4125. The transmit power optimization
maximizes overall wireless power system and foreign object detection features in
efficiency the LTC4125 require no direct communica-
Foreign object detection (FOD) ensures tion between the transmitter and receiver
safe and reliable operation when circuits. Even without digital communica-
working in the presence of conductive tion, the LTC4125 can work over a wide
33nF DR1
foreign objects.
10F
DFLZ30 DC
4V 100m VIN DR2
TO
M1
5.5V 412k 1.4M RC
2.21k 1k
47F
1F 10k 24.9k
x2 AIR GAP
DSTAT
100k 100k 100k 3mm RUN IN DHC QR1
TO
IN STAT IN1 IN2 47F
LTX 10mm BOOST
DTH NTC 24H 10nF
FTH SW1 SW
PTHM LRX
RNTCTX LTC4120-4.2 L1
4.32k 59.0k 8.45k 47H 15H
CTX
100nF CHGSNS
LTC4125 FAULT
IS SW2 BAT
CHRG BATSNS
10nF
10.2k DFB
IS+ VIN NTC
PTH1 100k PROG GND FREQ INTVCC 10k
DC1
PTH2 100V
CFB1 6.04k SINGLE
EN FB 0.1F
2.2F
0.1F 7.68k RNTCRX + CELL

IMON CTD CTS GND Li-Ion
A complete wireless battery charging system BATTERY
PACK
using LTC4125 AutoResonant wireless power 10nF 150k 470pF 4.7nF
transmitter in combination with the LTC4120, LTX: WT505090-20K2-A10-G DR1, DR2, DR3: DFLS240L
forming a 200mA single cell Li-ion battery CTX: C3216C0G2A104J160AC DC: BZT52C13
charger. The LTC4125 drives a 24H transmit CFB1: HMK107BJ104KA-T M1: Si7308DN
DC1: CDBQR70 QR1: PMBT3904M
coil at 103kHz, with 530mA input current DSTAT: LTST-C193KGKT-5A RNTCRX: NTHS0402N02N1002F
threshold, 119kHz frequency limit and 41.5C DFB: BAS521-7 LRX: PCB COIL AND FERRITE: B67410-A0223-X195
RNTCTX: NTHS0603N02N1002J OR 760308101303
transmit coil surface temperature limit. RED INDICATES HIGH VOLTAGE PARTS L1: LPS4018-153ML

highlights from circuits.linear.com
LTC7130 HIGH EFFICIENCY, 1.5V/15A STEP-DOWN

CONVERTER WITH VERY LOW OUTPUT RIPPLE VIN 2.2
The LTC7130 is a current mode synchronous step- 5V TO
20V 10F 1F 4.7F CMDSH3
down monolithic converter that can deliver up to 220F
x2
20A continuous load current. It employs a unique
architecture which enhances the signal-to-noise SVIN INTVCC ILIM ITEMP
0.72H,
ratio of the current sense signal, allowing the use VIN BOOST DCR = 1.3m,
PINS NOT USED
IN THIS CIRCUIT: 0.22F 744325072 VOUT
of a very low DC resistance power inductor to RUN
EXTVCC SW 1.5V
maximize efficiency in high current applications. PGOOD 20A
MODE/PLLIN
This feature also reduces the switching jitter CLKOUT 2.49k COUT
SNSD+
commonly found in low DCR applications. The ITH 470F
3.3nF LTC7130 220nF 4
LTC7130 includes a high speed differential 220pF
remote sense amplifier and a programmable TK/SS SNS
26.1k
current sense limit that can be selected from 0.1F 220nF
FREQ
10mV to 30mV to set the output current limit 499
121k SNSA+
up to 20A. In addition, the DCR temperature VFB
compensation feature limits the maximum
20k 30.1k DIFFOUT SGND GND DIFFN DIFFP
output current precisely over temperature.
LTM8064
VIN VIN VOUT
8.5V VOUT STACK TWO LTM8064s TO CHARGE AND ACTIVELY
TO 58V RUN BALANCE SUPERCAPACITORS (OR BATTERIES)
OPTIONAL + 15F
INPUT 2x4.7F The LTM8064 is a 58V input, 6A, constant-voltage,
PROTECTION 100V
MODE CTRL1 constant current (CVCC), step-down Module (power
SYNC CTRL2 module) regulator. Included in the package are the
100F 2.5V
VREF SUPERCAP
switching controller, power switches, inductor and
support components. Operating over an input voltage
RT GND FB range of 6V to 58V, the LTM8064 supports an output
voltage range of 1.2V to 36V. CVCC operation allows
196k the LTM8064 to accurately regulate its output current
15.0k
225kHz
up to 7A when sourcing and 9.1A when sinking over
PINS NOT USED IN THIS CIRCUIT: the entire output range. The output current can be set
SS, IOUTMON, PGOOD
LTM8064 by a control voltage, a single resistor or a thermistor.
VIN VOUT To set the switching frequency, simply place a resistor
from the RT pin to ground. A resistor from FB to ground
+ RUN sets the output voltage. Only the bulk input and output
15F 100F 2.5V
2x4.7F SUPERCAP filter capacitors are required to finish the design.
100V
MODE CTRL1 www.linear.com/solutions/7150
SYNC CTRL2
VREF
RT GND FB
196k
15.0k
225kHz PINS NOT USED IN THIS CIRCUIT:
SS, IOUTMON, PGOOD
LTM4632 3.6V TO 15V INPUT, 1.5V/3A VDDQ, 0.75V/3A VTT AND 10mA VTTR DESIGN VDDQ
The LTM4632 is an ultrathin triple output step-down Module (power module) PGOOD1 PGOOD2 22F 1.3V, 3A
VIN 4V
regulator to provide complete power solution for DDR-QDR4 SRAM. Operating VIN VOUT1
3.6V TO 15V RAIL
from a 3.6V to 15V input voltage, the LTM4632 supports two 3A output rails, both RUN1 VTT
22F RUN2 LTM4632 VOUT2
sink and source capable, for VDDQ and VTT, plus a 10mA low noise reference 22F 0.65V, 3A
25V
INTVCC VTTR 4V
VTTR output. Both VTT and VTTR track and are equal to VDDQ/2. Housed in a
SYNC/MODE FB1
6.25mm 6.25mm 1.82mm LGA package, the LTM4632 includes the switching COMP1
VTTR
TRACK/SS1 0.65V, 10mA
controller, power FETs, inductors and support components. Alternatively, the VDDQ
VDDQIN COMP2
power module can be configured as a two phase single 6A output VTT. Only a
GND 52.3k
few ceramic input and output capacitors are needed to complete the design.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, Dust Networks, LTPoE++, LTspice, Over-the-Top, Silent Switcher and Module are registered trademarks, and AutoResonant, ClockWizard, EZParallelSync, EZSync, EZ204Sync,
LTC6951Wizard, ParallelSync and SmartMesh IP are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 2016 Linear Technology Corporation/Printed in U.S.A./68.5K
Linear Technology Corporation

1630 McCarthy Boulevard, Milpitas, CA 95035
(408) 432-1900 www.linear.com Cert no. SW-COC-001530

Linear Tech Journal2016

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May 2016

load sharing for three or

One option is to use a 4-switch positive buck-boost LED

COVER STORY SINGAPORE TEST FACILITY EXPANDS TO BOOST PRODUCTION

2 | May 2016 : LT Journal of Analog Innovation

Linears Singapore receive the highest quality products

Sensor+Test 2016, Nuremberg Exhibition Centre,

Internet of Things World 2016, Santa Clara

May 2016 : LT Journal of Analog Innovation | 3

(LT3744, continued from page 1) 300 100

tors on the heat sink, and simplifying 70

ous currents exceeding 20A. The supply 0 0

4 | May 2016 : LT Journal of Analog Innovation

Figure4. The LT3744 is capable of driving VIN

287k 287k 287k

10nF 10nF 10k

May 2016 : LT Journal of Analog Innovation | 5

Figure7. The LT3744 is capable of driving

6 | May 2016 : LT Journal of Analog Innovation

In addition, with the three independent analog control inputs, each

Summary of Linears high power LED driver-controller family

LT3741 LT3743 LT3744 LT3763 LT3791

V IN range 6V36V 6V36V 3.3V36V 6V60V 4.7V60V

LED output range 0V34V 0V34V 20V36V 0V55V 0V52V

buck and inverting

LED current regulation accuracy 6% 6% 3% 6% 6%

Full-scale LED current sense 50mV 50mV 60mV 50mV 100mV

Common anode connection for LEDs L

LED fault indication L L L

Low side LED PWM gate driver(s) 0 2 3 1 1

Individual LED current states 1 2 3 1 1

An efficient high current LED driver-

May 2016 : LT Journal of Analog Innovation | 7

EN/UVLO VIN INTVCC

226k 226k 10nF 10nF

Figure8. A 57A/324W 2-LED driver

8 | May 2016 : LT Journal of Analog Innovation

Figure11. Parallel board

Figure13. Parallel board

May 2016 : LT Journal of Analog Innovation | 9

10 | May 2016 : LT Journal of Analog Innovation

minimize the inductance from each of the Figure15. Parallel inverting

May 2016 : LT Journal of Analog Innovation | 11

Figure1. LTC6951 performance advantage Figure2. LTC6951 block diagram

12 | May 2016 : LT Journal of Analog Innovation

R is the reference input divide value, N

output divider value. When RA0 = 0, N Internal VCO L

May 2016 : LT Journal of Analog Innovation | 13

EZSync EZSync EZ204Sync The LTC6951 provides three synchroni-

SYNC PULSE SKEW VCO+ LV/CM+

PECL2+ EZSync Standalone

14 | May 2016 : LT Journal of Analog Innovation

ParallelSync synchronization (Figure 6) increases REFERENCE DISTRIBUTION 1F

the number of synchronized clock outputs LTC6954-4 REF+ OUT4+

LTC6951s Reference Aligned Output tSS tSS

falling edge of the sync input signal and

explains how outputs from one or LTC6954-4 REF+ OUT4+

an EZSync distribution device to act as 1F OUT3

May 2016 : LT Journal of Analog Innovation | 15

To enable deterministic latency,

JESD204B subclass 1 added the align-

16 | May 2016 : LT Journal of Analog Innovation

OUT4 MGMT CLK FPGA

capable, due to the LTC6951 output CLK SYSREF