Asynchronous Distributed Generation System Based
on Asymmetrical Cascaded Multilevel Inverter
Srgio Pires Pimentel
School of Electrical and Computer Engineering
University of Campinas - UNICAMP
13083-852, Campinas, SP, Brazil
Email: sergio@dsce.fee.unicamp.br
AbstractAn asynchronous distributed generation (DG)
single-phase system is proposed. It is based on an asymmetrical
cascaded multilevel inverter with 19 levels and it is supplied by
asynchronous voltage sources. It is possible to operate contin-
uously the proposed GD system during the grid-connected or
the stand-alone modes. Details about its operation modes are
presented. A prototype of the proposed GD system has been
implemented on a fixed-point DSP TMS320F2812. An injection
of only active power into the grid utility and an uninterrupted
load supply have been pursued. Simulation and experimental
results presents the performance of the proposed GD system.
I. I NTRODUCTION
The attention and researches on distributed generation (DG)
systems have been increasing lately and this situation tends to
rise more and more. The main reasons for it are the growth of
the discussions about environmental issues, the development
of renewable energy sources technologies and the imminent
possibility of an energy crisis. Power electronics devices are
an useful alternative to DG systems. They can improve its
dynamic response, increase its global efficiency and allow the
operation of a large number of systems based on photovoltaic
cells, fuel cells or any other asynchronous electrical source.
Besides, these DG systems can be also an alternative UPS
system if they were not connected to the grid utility.
Generally low power DG systems are connected to the grid
utility at low voltage levels (13.8kV), which are considerably
affected by the presence of nonlinear loads. It means that
these DG systems must be controlled considering harmonics,
resonances and other power quality issues. In case of single-
phase DG systems (residential power generation) the attention
on those disturbances must be bigger. According to [1], only
a few number of single-phase DG systems that operates
connected (or not) to grid utility have been studied. There
are five possible obstacles for it. First of all, the main control
systems from three-phase systems based on dq0 transformation
can not be applied directly in single-phase systems. Second,
if they could be applied after some modifications, the dq0
components would not be equal to constant values for situ-
ations involving harmonics, resonances or unbalance. Third,
the control of exchange power by changes on angle phase
and on amplitude voltage is based on sinusoidal steady-state
equations. Fourth, the use of a reactive power control assumes
that the reactive power concept has already been defined. And
k,((( 
Jos Antenor Pomilio
School of Electrical and Computer Engineering
University of Campinas - UNICAMP
13083-852, Campinas, SP, Brazil
Email: antenor@dsce.fee.unicamp.br
S PCC Lf ic
Ls Rd Ld is
vc
Icc = 10 kA S1
13.8 kV #1/0 CAA 0.5 km iL
60 Hz 150 kVA (0.6960 + j 0.5182) /km Load
13.8 / 0.22 kV Multilevel
X = 3.5 % Inverter
Fig. 1. Grid connection diagram of DG system.
fifth, high costs of inverters and renewable energy technologies
disable a expansion of small GD systems, mainly on single-
phase applications.
The proposed GD system is connected to a single-phase
grid utility and it is supplied by asynchronous DC voltage
sources. Details about it and its operation modes are presented.
Simulation and experimental results are also presented. Finally
the conclusions about the effectiveness of the proposed GD
system are drawn above.
II. D ISTRIBUTED G ENERATION S YSTEM
The structure of the proposed DG system consists of an
inverter connected to the PCC (Point of Common Coupling) by
an inductance (see Fig. 1). The inductance Lf could represent
a power transformer element or just a first order low pass
filter element. Besides, it is responsible for injecting current
into PCC and also for attenuating the impact of high frequency
components from the inverter output voltage vc on the inverter
current ic (WTHD factor).
The main purpose of the DG system is to supply load contin-
uously even if there was a grid failure or an islanding situation
has occurred. At this point, DG system has similarities with
on-line UPS systems. When there is not an islanding situation
occurring, DG system operates at the grid-connected mode.
During the grid-connected mode DG system could supply all
the load power (active and nonactive), only a part of it (in
addiction to the grid utility supply) or supply all the nonactive
power of load (like an active power filter would do). However,
this last possibility does not represent exactly a DG system.
Considering that all the load power is supplied by the DG
system, the inverter current ic should be the same as load
current iL and the source current is should be null. Except
when a high rate of change of the load current (i.e., a fast
diL
dt ) occurs and it demands energy rapidly from the grid utility.
 S PCC Lf ic vC
Req Leq is
S1 vc
(0.3480 + j 0.2706)
127 V iL
60 Hz Load
Multilevel
Inverter
1V1 2V1 6V1

Fig. 2. Grid connection diagram of DG system to an equivalent circuit of

the Area EPS. Fig. 3. Asymmetrical cascaded multilevel inverter with 19 levels.

Islanding
Detection
It happens mainly for nonlinear loads due to the inductance
Lf and to the dynamic response limitations of the inverter. If Grid-Connected Stand-Alone
the inverter maximum power is higher than load power, DG Mode Mode

system could use this spare power for delivering active power
Synchronization
to the grid utility. This situation represent a DG scheme and
that is why it is not an UPS system. Fig. 4. State machine diagram with the operation modes of DG system.
The DC-links of the inverter could be supplied by an amount
of fuel cells, photovoltaic (or solar) cells or both. There is iC* ec vC v*C vC vf 1 iC
+
also the possibility of wind turbines supply them by energy PIc
+
1 + sLf + RLf
_ + _

storaged in batteries. The energy from those elements should Current

be conditioned by an isolated DC/DC converter before being
stored in batteries, capacitors or another storage element. As
the main energy used for DG comes from DC voltage sources
or from DC switching power supplies, the proposed system is
called an asynchronous (or nonrotational) DG system.
A. Grid Connection
According to [2], the complex formed by the load (or an
amount of loads), by the inverter and by the PCC bar is called
Local EPS (Electric Power System). The Local EPS stood
out in Fig. 1. The utility grid that is away from switch S1
is called Area EPS [2]. The Area EPS presented in Fig. 1
could be reduced and replaced by its equivalent circuit per
phase. Considering a short circuit current equals 10kA at the
high voltage bus (13.8kV), the calculated equivalent circuit of
Area EPS is presented in Fig. 2.
B. Multilevel Inverter
The inverter of the DG system consists of a multilevel
structure with 19 levels produced by an asymmetrical cascaded
topology [3], [4]. Fig. 3 shows this structure. Although it
uses more semiconductors switching devices and it has some
disadvantages, this structure has been chosen because it pro-
duces an output voltage waveform with lower THD than the
standard inverter with traditional PWM and it can operates
at low switching frequency. These advantages may eliminate
the second order (or higher) low pass filters. The multilevel
inverter can achieve high voltage levels using a lot of H-bridge
cells that operates at low voltage levels. This characteristic
could allow a direct connection of the inverter to high voltage
buses without using power transformers [3] and it would be
an example of high power application.
III. O PERATION M ODES
The state of switch S1 determines which mode of operation
is responsible for controlling the proposed DG system: grid-
connected mode or stand-alone mode. However it is necessary
two auxiliary control systems for determining the state of
Controller
Multilevel
Inverter
Filter
vd vPCC
Fig. 5. Inverter current control diagram during grid-connected mode.
this switch and its transitions. The auxiliary systems are: an
islanding detection scheme; and a procedure for grid synchro-
nization before reconnection. These modes of operation and
their transitions are represented as a state machine in Fig. 4.
A. Grid-Connected Mode
During the grid-connected mode, DG system is able to
deliver active power from the Local EPS to the Area EPS
and supply the active and the nonactive power to the load.
A suitable inverter current control is very important because
DG system operates as a controlled current source. Besides,
the active power exchange between Local EPS and Area EPS
should result in a source power factor closed to unity. This is
achieved by the source average power control.
1) Current Control: The inverter current control diagram
is shown in Fig. 5. It is very similar to those used in active
power filters. A PI controller with a high time constant is used
to guarantee that current error ec be null at 60Hz. The output of
the PI controller vc is added to the voltage vd (a feed-forward
action) to elaborate the reference signal of the inverter output
voltage vc . This signal is used by the modulation strategy
to create the real inverter output voltage vc . From variations
on vc it is possible to control the inverter current ic by the
inductance Lf . The voltage vd could be equal to the PCC
voltage or to a sinusoidal signal waveform which frequency is
determined by the islanding detection scheme. The reference
signal waveform to the inverter current ic comes from the
source average power control.
2) Average Power Control: The source average power
control diagram is shown in Fig. 6. The average value of
the source instantaneous power ps is equal to source active
power (i.e., ps = Ps ). That is why the control is based
on ps . The source average power control is responsible for

k,((( 
 0 PCC Islanding
i*S _ iC* iC _ iS pS PLL
ISD
RLS
vPCC fPCC
P*S +
eP k
C(s)
&
Situation
PIp + +
Detection
vd
_ Current VPCC
FWD 1
Control Loop vPCC
Average Power iL iL Scheme
Controller vPCC
1 T

T 0
Fig. 7. Data flux of the islanding detection scheme.

Fig. 6. Source average power control diagram during grid-connected mode.

regulating Ps and for defining the reference signal waveform
to the inverter current ic . If none active power is delivered to
the Area EPS (i.e., is = 0), the signal ic will be equal
to the load current iL and DG system will supply all the
active and nonactive load powers. If an amount of active
power could is available to be delivered to the Area EPS,
the signal ic will be equal to the sum of the load current iL
with the reference signal waveform of the source current is .
The reference signal is is obtained from the multiplication
of the PCC voltage vP CC with the output average power PI
controller k. This multiplication represents a technique called
Resistive Load Synthesis (RLS) [5], [6]. Delivering only
active power to the Area EPS is possible because current and
voltage have the same waveform in the RLS technique, just
like in a resistor. A PI controller with a very low time constant
and a low proportional gain is used to guarantee that average
power error ep be null at 0Hz. It is important to notice that
the reference source average power Ps must assume negative
values to allow a correct delivery of active power to the Area
EPS (e.g., Ps = 500W).
B. Islanding Detection
The main islanding situations are grid failure, under/over
voltage and under/over frequency. During the grid-connected
mode the voltage at PCC is held by the grid utility. If
an islanding situation happens the voltage vP CC would be
uncontrolled, the load current would follow these unintentional
changes, the Local EPS could supply wrongly some loads from
Area EPS and the inverter current control could be unstable.
Besides, DG system should not be controlled at the grid-
connected mode anymore, it should be controlled at the stand-
alone mode. The proposed DG system uses an active islanding
detection based on a technique called Active Frequency Drift
with Positive Feedback (AFDPF) [7].
The basic concept of active islanding detection techniques
is to modulate a power system parameter and to measure its
corresponding system response [7]. Passive islanding detection
techniques could failure if there is no power exchange between
Local EPS and Area EPS or could generate unintentional is-
landing situations. Originally the AFDPF technique presented
in [7] introduces small perturbations at the inverter output
current by modulating its frequency. The proposed islanding
detection scheme modulates also the frequency but introduces
these perturbations at the inverter output voltage by the voltage
signal vd . The signal vd is produced from data collected by
a PLL and a FWD (Fundamental Wave Detector) that are
pursuing the PCC voltage (see Fig. 7). The PLL and the FWD
are presented in [8]. Fig. 7 shows also a logical signal called
ISD that means Islanding Situation Detected. This logical
signal is low when an islanding situation has not been yet
detected.
The frequency of the PCC voltage fP CC is used to calculate
the chopping factor cf as in (1). The initial chopping factor
cf0 is equal 0.0083264 and it represents the chopping factor
when there is no frequency error. The initial frequency fP CC0
is equal 60Hz and the gain kf is equal 1.0.
cf = cf0 + kf (fP CC fP CC0 ) (1)
The chopping factor cf is used to determine the distortion
factor d as in (2). The factor d represents how higher the
frequency distortion fd is than fP CC and it is very important
to the positive feedback. If there is a frequency error, the
factor d would tend to increase this error and to destabilize the
frequency at PCC. It happens continuously and the islanding
situation could be detected if the values of under/over voltage
and under/over frequency were reached. When there is no
frequency error, fd is equal 60.05Hz by the chosen value for
cf0 .
fd 1
d= = (2)
fP CC0 (1 cf )
The factor d is used to create the distortion angle (d ) from
the phase angle of the voltage at PCC (P CC ) as in (3). The
angle P CC is manipulated by scaling its range during each
half period of fP CC . It results in a change of the rise time of
the angle P CC as it is shown in Fig. 8(a). If fd is higher than
fP CC , d would rise faster (frequency drift up) than P CC
during each half period. Otherwise, it rises slower (frequency
drift down).

d P CC , if (0 < P CC )
d = (3)
+ [d (P CC )] , if ( < P CC 2)
The distortion angle d and the peak value of the fun-
damental voltage at PCC (VP CC1 ) are used to compose the
distortion voltage vd as in (4). Therefore, vd receives all the
modifications made by the d at P CC . It results in changes on
the distortion voltage waveform as it is shown in Fig. 8(b). The
distortion voltage vd is added to the output current controller
(vc ) to create the reference signal of the inverter output
voltage. This action qualifies the DG system for detecting
islanding situations even when there is a minimal power
exchange between Local EPS and Area EPS.
vd = VP CC1 sin (d ) (4)

k,((( 
 d S
vS PLL
2
1
& VS Synchronization
SyA
FWD 1

fd > fPCC vPCC Method

v*PCC
Scheme
ISD

sin()
0

fd < fPCC
PCC Fig. 10. Data flux of the SM scheme.
0 2 1
0 1.5708 3.1416
(rad)
4.7124 6.2832
Table I
PARAMETERS OF THE S IMULATION M ODEL
(a) (b)

Fig. 8. AFDPF angle (a) and waveform (b) modifications with frequency Parameter Value Units

drift up (blue) and frequency drift down (red). Maximum Output Inverter Voltage vcmax 1.15 127 2 V
Filter Inductance Lf 3.85 mH
v*C Lf
PCC
Grid Equivalent Inductance Leq 0.70 mH
+
1 AC Input Rectifier Inductance Lac 4
v*PCC + ev + iC=iL mH
_ s
Load DC Output Rectifier Capacitance Cdc 470 F
179.605Vpeak 1 2
127Vrms
60Hz
s + 12 Multilevel
Inverter DC Output Rectifier Resistance Rdc 100 200
P + Ress vPCC

Fig. 9. PCC voltage control diagram during stand-alone mode. is necessary to adjust the PCC voltage with the purpose of
decreasing these differences and reconnecting the Local EPS
to Area EPS. The scheme of the used synchronization method
C. Stand-Alone Mode is shown in Fig. 10. It is noticed that the SM receives data from
During the stand-alone mode the Local EPS is disconnected the voltage vS by a PLL (S and VS1 ), from the PCC voltage
from the Area EPS and DG system becomes an controlled vP CC and from the islanding detection method (ISD). The SM
voltage source that supplies the load. At this operation mode process all of these collected data and provides two output
the main purpose is to keep voltage at the PCC closed signals: the logical signal (SyA) that means Synchronism
to
a sinusoidal waveform with peak voltage equals 127 2V Achieved; and the reference signal of the PCC voltage vP CC .
(179.605V), frequency equals 60Hz and an initial phase The signal SyA is high if the error voltage were below an
angle equals the grid phase angle before islanding. The inverter acceptable level for some cycles of the PCC voltage and if
must provide an output voltage that contains the desired the signal ISD were high. If error voltage is above it or if the
voltage to PCC and a compensation for the voltage drop across ISD is low, the signal SyA will be low. An association of both
the inductance Lf caused by the load current. logical signals, ISD and SyA, could be used to determine the
1) Voltage Control: It is possible to achieve the purpose state of switch S1 .
of the stand-alone operation mode using a control system that The elaboration of the reference signal vP CC is based on a
regulates the inverter output voltage based on the feedback PLL which is similar to that used by the islanding detection
of the PCC voltage. The voltage control system diagram is mode. When the logical signal ISD is low, the phase angle
shown in Fig. 9. It can be noticed that the control system uses of vP CC (P CC ) is equal S and the peak voltage of vP CC
a proportional and resonant controller (P+Ress) instead of a (VPCC1 ) is equal VS1 . After ISD had become high, P CC
traditional PI compensator for annulling the voltage error ev varies cyclically (60Hz) from 0 to 2 with an initial value

at 60Hz. It is because the P+Ress controller has a high gain at on S just before ISD became high, and VP CC1 is equal
based
0Hz and at 60Hz, while the PI controller has only at 0Hz [9]. It 127 2V. If a stable and nominal voltage has been checked at
means that voltage error ev at 60Hz could be null if a P+Ress the S bar during the stand-alone mode, the SM will start up.
controller was used. This is an attractive characteristic because The SM adjusts slowly (for a few cycles of 60Hz) the peak
the reference signal of PCC voltage vP CC is a sinusoidal voltage VPCC1 and the phase angle P CC for equalling them
waveform. Other control schemes have been tested to regulate to VS1 and S , respectively.
the peak value or the RMS value of the PCC voltage using PI
IV. S IMULATION R ESULTS
controllers, but they were not so suitable as the control scheme
shown in Fig. 9 was. A model of the proposed DG system has been simulated
using the software PSIM. An uncontrolled bridge rectifier with
D. Synchronization an DC output capacitor supplying a resistor was considered as
During the stand-alone mode, the voltage at the PCC bar is the load connected to PCC. Because of it, the performance of
controlled by the DG system and the voltage at the S bar is DG system has been tested considering nonlinear loads. Tab.
controlled by the Area EPS operator and it could not be exactly I presents the main parameters used by the simulation model.
equal the PCC voltage (see Fig. 2). If they were not equal in The normal operation (without islanding situations) of DG
amplitude, in phase angle or in frequency, the switch S1 should system during the grid-connected is presented in Fig. 11.
not be closed. That is why a synchronization method (SM) The DG system is connected to PCC at t=0.3s and supplies

k,((( 
 (a) (a)
10 62
is fs
i 61.5 fPCC
5 c
i 61
L
(A)
0 60.5
(Hz)60
5
59.5

10 59
0.25 0.3 0.35 0.4 0.45 0.5 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08

(b) (b)
800 200
644 Ps vs
Pc vPCC
100
400 PL v*PCC
(W) 144 (V) v
0
0
200 100
400
500
200
0.25 0.3 0.35 0.4 0.45 0.5 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08
Time (s) Time (s)

Fig. 11. Current waveforms (a) and active power waveforms (b) during a Fig. 13. After t = 1.0s, the SM adjusts fP CC (a) for equalling P CC and
normal operation of the grid-connected mode. S (b).

(a)
200 62
(a) fs
61.5 fPCC
(V) 0 v 61
PCC
v*
PCC 60.5
S1
(Hz)60
200
0.45 0.5 0.5316 0.55 0.6 0.65
59.5
61
(b) f
60.5 d 59
f 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5
PCC
(Hz) 60
(b)
200
59.3 vs
59 *
vPCC
0.45 0.5 0.5316 0.55 0.6 0.65 100
v
188.5854
(c) (V)
179.6051 0
170.6249
100
(V) 160
VPCC
150 1
200
0.45 0.5 0.5316 0.55 0.6 0.65 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5
Time (s) Time (s)

Fig. 12. Islanding detection and stand-alone mode: (a) vP CC (blue), vpcc Fig. 14. Behavior of fP CC (a) and v (b) during the synchronization
(black) and S1 gate signal scaled by 100 (red); (b) fd (red) and fP CC (blue); adjustments after t = 1.0s
(c) VP CC1 .

phase angles P CC and S , as it is shown in Fig. 13. It is

immediately all the load current iL . At t=0.4s DG system
started delivering active power to the Area EPS in addition
with the load current supply. A reference source active power
Ps of 500W is achieved after t=0.45s. The phase angle of
the source current is proves the injecting of that active power
into the Area EPS.
The islanding detection scheme was also tested by the
simulation model and its results are shown in Fig. 12. Consid-
ering that there was no exchange power between Local EPS
and Area EPS, an islanding situation has occurred at t=0.5s.
From this point, the PCC voltage waveform vP CC contains
all the output inverter voltage harmonics attenuated by the
filter inductance. The islanding is detected at t=0.5316s by an
under frequency protection. After detecting the islanding, the
switch S1 is open at t=0.5316s and the DG system started
operating at the stand-alone mode. This procedure guarantees
a uninterrupted load supply.
The grid utility supply could be available for a few cycles
after the failure or it could take a long time. While it does
not happen, DG system operates at the stand-alone mode
continuously. During the simulation, the availability of grid
utility at the S bar was reestablished at t=0.8s but with
another phase angle. At t=1.0s the SM started running and
adjusts the frequency of the PCC voltage for equalling both
noticed that fP CC and VP CC1 vary slowly along the time. The
signal v represents the difference between vS and vP CC .
Fig. 14 shows the behavior of the v and of the frequency
fP CC during the SM adjustments. If they were lower than
predetermined levels for five consecutive cycles of 60Hz, the
SM permits the reconnection of Local EPS and Area EPS
by setting the SyA signal. It happens at t=1.559s and the
switch S1 is closed at this time, as it is shown in Fig. 15.
After the reconnection, DG system operation returns to the
grid-connected mode and the islanding detection scheme is
reactivated.
V. E XPERIMENTAL R ESULTS
A multilevel inverter supplied by isolated DC voltage
sources was used to compose a prototype of 1kW for vali-
dating the proposed DG system. DG system prototype is im-
plemented with integrated power modules IRAMX16UP60A
as the semiconductor devices and is controlled by a fixed-point
DSP TMS320F2812. The prototype parameters are similar to
those simulation model parameters presented in Tab. I.
Fig. 16 shows the connection between DG system and PCC
and its performance for supplying all the load current during
the grid-connected mode. Differently from the simulation
model, DG system prototype does not supply immediately all

k,((( 
 (a)
6

2
(A) 0

2 i
s
i
4 c
i
L
6
1.5 1.53 1.559 1.6 1.65

(b)
200

100

(V)
0
v
s
100 vPCC
100S1
200
1.5 1.53 1.559 1.6 1.65
Time (s)

Fig. 15. Reconnection at t = 1.559s: (a) current waveforms; (b) voltage Fig. 17. From top to bottom: vP CC (Ch2, 200V/div); ic (Ch4, 2A/div), iL
waveforms and S1 gate signal scaled by 100 (magenta). (Ch4, 2A/div) and is (Ch1, 2A/div).

schemes used by DG system have been discussed. Simulation

Fig. 16. From top to bottom: vc (Ch4, 250V/div), vP CC (Ch2, 200V/div),
is (Ch1, 2A/div) and ic (Ch3, 2A/div).
the load power. It happens gradually for one cycle of 60Hz and
facilitates the stability of the prototype operation. However it
happens just at the initialization of the prototype. Future load
changes must be supplied immediately by the DG system.
After the stabilization of the DG system operation and the
current controller, the prototype is able to provide active power
to the Area EPS. Fig. 17 shows the behavior of the current and
voltage waveforms after this active power injection has been
started. After that DG system supplies the load power and
the source active power. The source average power controller
achieves a stable operation point after two cycles of 60Hz and
the source active power is similar with its predetermined refer-
ence. Besides, the load power supply has not been interrupted
and the load current has not been changed. It could be noticed
from Fig. 17 that source current has the same waveform of the
PCC voltage. This similarity validates the RLS technique and
the only active power exchange between Local EPS and Area
EPS.
VI. C ONCLUSIONS
A proposal single-phase distributed generation system sup-
plied by asynchronous power sources with the ability to
handle linear and nonlinear loads is presented. Details about
the multilevel inverter, grid connection, voltage levels and
operation modes have been described. Concepts of the control
results have been presented for illustrating those concepts and
facilitating a prototype model design.
A prototype of the proposed DG system has been im-
plemented and its validity during the grid-connected mode
has been proved by the experimental results presented. The
current controller of the grid-connected mode is based on a
PI compensator. During the experimental tests, it was noticed
that this type of controller has not a wide range of possible
operation points and it could not be efficient even if it was
stable. The initialization issue could be solved using another
type of current controller, probably a nonlinear type. The
authors are still working on this issue.
ACKNOWLEDGMENT
The authors would like to thank CAPES and FAPESP (both
from Brazil) for their financial support. The authors would
also like to thank M.Sc. Rodolfo Martinez and Mr. Rodrigo
Taparelli for their valuable contributions.
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k,(((