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How Computers Work

Lecture 3

A Direct Execution RISC Processor:

The Unpipelined BETA

How Computers Work Lecture 3 Page 1

What you can do with very little:

Each instruction class can be implemented using a few
simple components.

Components:

A
Instruction
A B Memory
D
ALU

WD
A Data
RA1 RA2 Memory
RD
0 1 WA R/W
Register
WE File
WD (2-port)

RD1 RD2

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Review: Model of
Computation Fetch/Execute
Processor State Instruction Memory Loop:
PC Fetch <PC>
PC <pc> + 1
r0 Execute fetched
instruction
r1 32 bits
r2 (4 bytes) Repeat!

32 bits
next instr

r31 always 0

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Review: BETA Instructions

Two 32-bit Instruction Formats:

OPCODE Ra Unused Rb Rc

OPCODE Ra 16 bit Constant Rc

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Review: ALU Operations SIMILARLY FOR:

What the machine sees (32-bit instruction word):
SUB, SUBC
(optional)
OPCODE Ra Unused Rb Rc MUL, MULC
DIV, DIVC
What we prefer to see: symbolic ASSEMBLY LANGUAGE
BITWISE LOGIC:
ADD(ra, rb, rc) rc <ra> + <rb> AND, ANDC
Add the contents of ra to the contents of OR, ORC
rb; store the result in rc
XOR, XORC

Alternative instruction format: SHIFTS:

SHL, SHR, SAR
(shift left, right;
OPCODE Ra 16 bit Constant shift arith right)
Rc
COMPARES
CMPEQ, CMPLT,
ADDC(ra, const, rc) rc <ra> + sext(const) CMPLE

Add the contents of ra to const; store the result in rc

How Computers Work Lecture 3 Page 5

A Descending Data Flow View of the Beta

PC
Q
Operate class: Rc <- <Ra> op <Rb>

XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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Combinational Read Port on

Memory

Address
A
Memory
Q

<Address>

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Data Register
Works like a camera
D = image
D Q
Q = picture
E = On/Off Switch
E
clock = shutter release button
Clock

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D Register w/ Enable
D Q
E

clk

clk clk

Q Q

D D

E E
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2-Port Register File

(independent Read addresses)
RA A

RD <A>
RA1 RA2
5
Write Address WA
Register CLK
Write Enable WE File
WE
Write Data WD (2-port)
32
WA A
CLK
RD1 RD2
WD new <A>
32 32

(Independent Read Data)

Note:
<R31>
Always What if (say) WA=RA1???
ZERO!
RD1 reads value from last cycle!

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Selector (a.k.a. Multiplexor / MUX)

Output Q is selected to be 1 of N inputs
N is a power of 2
K select inputs, K = log2(n)
May be ganged to select one W-bit word out of N multi-bit
words
DN-1 D2 D1 D0 DN-1 D2 D1 D0
. . . . . . W

S S
K K
W

Q = Ds Q = Ds

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A Descending Data Flow View of the Beta

PC
Q
Operate class: Rc <- <Ra> op <Rb>

XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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A Descending Data Flow View of the Beta

PC
Q Operate class: Rc <- <Ra> op C

XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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Review: Branches
Conditional: rc = <PC>+1; then
BRNZ(ra, label, rc) if <ra> nonzero then
PC <- <PC> + displacement
BRZ(ra, label, rc) if <ra> zero then
PC <- <PC> + displacement

Unconditional: rc = <PC>+1; then

BRZ(r31, label, rc) PC <- <PC> + displacement
Note:
Indirect: rc = <PC>+1; then displacement
is coded as a
JMP(ra, rc) PC <- <ra> CONSTANT in
a field of the
instruction!

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A Descending Data Flow View of the Beta

PC
Q Rc <- <PC>+1; if <Ra>=0 then PC <- <PC>+C

XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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A Descending Data Flow View of the Beta

PC
Q
JMP: Rc <- <PC>+1; PC <- <Ra> + C

XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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Review: Loads & Stores

LD(ra, C, rc) rc < Mem[<ra> + sext(C)] >

Old ST(rc, C, ra) Mem[<ra> + sext(C)] <rc>

New ST(ra, C, rc) Mem[<rc> + sext(C)] <ra>

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Straightening Out Store

Old Format: ST(Rc, C, Ra)
Mem[<Ra> + C] <- <Rc>
ST(R1, 2, R3) means Mem[<R3> + 2] <- <R1>
New Format: ST(Ra, C, Rc)
Mem[<Rc> + C] <- <Ra>
ST(R1, 2, R3) means Mem[<R3> + 2] <- <R1>
Both versions of Store work from left to right in
assembly language.
Difference is only in the binary encoding of the
instruction, and the hardware implementations
decoding of the binary encoding.

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A Descending Data Flow View of the Beta

PC
Q
LD: Rc <- Mem[<Ra>+C]
XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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A Descending Data Flow View of the Beta

PC
Q ST: Mem[<Rc>+C] <- <Ra>

XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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LDR
Load Relative
Used for loading large (32 bit) constants with data from the instruction
stream.
Depends on the fact data and instruction memory are ports of one main
memory.
Use: LDR (label, Rc)
RTL Description: Rc <- <Mem[<NextPC> + Offset]>
Note that Ra is ignored, Offset is calculated from label

LDR (label, R1)
BR (label + 1)
label: 123456789

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A Descending Data Flow View of the Beta

PC
Q
LDR: Rc <- Mem[<PC>+1+C]
XADDR
RA1
Memory
RD1 BRZ(R31,XADDR,XP)

ISEL 0 1

31:26 25:21 20:5 9:5 4:0

OPCODE RA C RB RC

+1 0 1

OPCODE RA1 RA2

Register File SEXT Register File
RD1 RD2

ASEL BSEL
0 1 2 1 0

A B
ALUFN ALU
A op B
Z

RA2
Memory
RD2

PCSEL 0 1 0 1 2 WDSEL

D WD WA WD WA RC
PC Memory Register File
WE WEMEM WE WERF

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Control Logic Truth Table

We can specify it via a table of the form ...

Control Logic Inputs:

OPCODE OP OPC LD ST BRZ BRNZ JMP LDR (Illegal)

Z 0 1 0 1

Control Logic Outputs:

PCSEL
RA2SEL
ASEL
BSEL
WDSEL
ALUFN
Wr
WERF
WASEL

YOU should be able to fill in this table!

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Next Time - How to Add

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