Chapter 4: Memory Built-In

Built In
Self Test
Self-Test

Jin Fu Li
Jin-Fu
Dept. of Electrical Engineering
National Central University
Jhongli, Taiwan
 Outline
ROM BIST
RAM BIST
Serial BIST for RAMs
Processor
Processor-Based
Based RAM BIST
RAM BISTs in SOCs
References

EE, National Central University Jin-Fu Li 2

 Introduction
Characteristics of todays SOC designs
Typically more than 30 embedded memories on a
chip
hi
Memories scattered around the device rather than
concentrated in one location
Different types and sizes of memories
Memories doubly embedded inside embedded cores
Test access to these memories from only a few chip
I/O pins
p
Built-in self-test (BIST) is considered the best
solution for testing embedded memories within
SOCs
It offers a simple and low-cost
low cost means without
significantly impacting performance
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 General BIST Architecture

Test Circuit Under Test Response

Generator (CUT) Verification

Test Controller

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 ROM Functional Block Diagram
Inputs

Buffer

NOR/NAND
Decoder
(ROM Array)

Buffer

Outputs
O t t
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 An Example of ROM BIST

Counter
ROM

Controller MISR

Go/No-Go Status

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 Typical RAM BIST Architecture

Normal I/Os

T t Controller
Test C t ll

Test Collar
C
RAM
Test Pattern
Generator

Go/No-Go
Comparator

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 RAM BIST
In general, two BIST approaches have been
proposed for the RAMs
FSM-based RAM BIST
ROM-based RAM BIST

Controller
Generate control signals to the test pattern
generator & the memory under test
Test pattern generator (TPG)
Generate the required test patterns and Read/Write
signals
g
Comparator
Evaluate the response
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 ROM-Based RAM BIST
The features of ROM-based BIST scheme
The ROM stores test procedures for generating test
patterns
Self-test is executed by using BIST circuits controlled
by the microprogram ROM
A wide range of test capabilities due to ROM
programming
p g g flexibility
y
The BIST circuits consists of the following
functional blocks
Microprogram ROM to store the test procedure
Program counter which controls the microprogram
ROM
TPG
Comparator
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 ROM-Based RAM BIST Architecture

Normal I/Os

E d
End Mi
Microprogram

Test Collar
ROM

RAM
TPG

Go/No-Go
Comparator

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 March-9N Test Procedure & Microcodes
M h 9N
March-9N:
STEP OPERATION MICROCODE
CLEAR 0000000010
WRITE(D), INC AC, IF AC=MAX THEN INC PC 1010000100
READ(D) 0000000100
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC 1110010100
READ(D))
READ(D 0000011000
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC 1110000100
DEC AC 0001000000
READ(D) 0000001000
WRITE(D) DEC AC
WRITE(D), AC, IF AC=0 THEN INC PC ELSE DEC PC 1101010100
READ(D) 0000011000
WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC 1101000100
STOP 0000000001

IF AC=MAX/0
ELSE DEC PC
INCREMENT AC
DECREMENT AC
EXCLUSIVE OR
INVERT/NORMAL
COMPARE/MASK
WRITE/READ
CLEAR
TEST END
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 FSM-Based RAM BIST

Normal I/Os

E d
End
FSM

Test Collar
RAM
TPG

Go/No-Go
Comparator

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 FSM-Based RAM BIST
A example
An l off the
h state di
diagram off controller
ll
W0 S0 NOT last address?

R0 S1
NOT last address?

W1 S2

R1 S3
NOT last address?

W0 S4

R0 S5
NOT last address?

W1 S4

End S4
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 Programmable RAM BIST
A example
An l off the
h programmable
bl RAM BIST

Normal I/Os

CMD

T
TPG
BSI

Test Collar
Con
TGO

& Compar
BSC RAM

C
ntroller

C
ENA
BRS

rator
DONE
BGO

CLK
BNS

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 FSM State Diagram of the Controller

Idle BRS=1

BSC=1
DONE=1 Shift
Shift_cmd
d

BSC=0

Get_cmd

Apply ENA=1

DONE=0

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 Programmability
The programmability
Th bili can b
be achieved
hi dbby using
i
test command
The test command format
U/D OP Data background
U/D: ascending/descending address
sequence
OP: test operations
For
o example,
e a p e, wa,
a, rawa,
a a , rawara,
a a a, warawara,
a a a a , etc.
Data backgrounds
The width
Th idth off each
h field
fi ld affects
ff t the
th
programmability of the BIST design
For
F example,
l if 4 bit
bits are used
d ffor OP
OP, th
then only
l 16
possible test operations
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can be generated
Jin-Fu Li 16
 FSM State Diagram of the TPG

Idle ENA=0

ENA=1

Init DONE/GO
Null=1
Null=0

Ifetch

Exec

Dfetch

Error=1 Error=0
No-Go Compare

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 Serial BIST
Todays telecommunication ICs often have a
variety if multiport memories on one chip
Typical RAM BISTs evaluate all the bits of a
memory word in parallel as it is read
We can encounter significant problems when
applying these BIST schemes to chips that have
multiple embedded RAMs of varying sizes and
port configurations
The area cost of these BIST designs would be
unacceptably high
One better solution is a serial BIST technique
To
T share
h BIST d
design
i among severall RAM
RAMs
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 Benefits of Serial BIST
Only a small amount of additional circuitry is
required
Only a few lines are needed to connect the RAM
to the test controller
Several RAM blocks easilyy share the BIST
controller hardware
The serial
serial-access
access mode does not compromise
the RAM cycle time
Existing
E i ti memory d
designs
i d
do nott need
d any
modification to use the serial interface

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 Serial-Data-Path Connection

Row de
Ci Ci+1

ecoder
Column decoder

Latch Latch
Write
Read
BIST on
To next test input
From previous output or serial input
or serial input
Ii Oi Ii+1 Oi+1
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 Serial Shift Operation
An example of serial shift operations for the
match element (R0W1)
Time Operation Serial Word Serial
in content out

0 X 0 0 0 0 X
1 R0 X 0 0 0 0 0

0
11 00 00 00 2 W1 1 1 0 0 0 0
3 R0 1 1 0 0 0 0
4 W1 1 1 1 0 0 0
5 R0 1 1 1 0 0 0
010 000 000 000
6 W1 1 1 1 1 0 0
7 R0 1 1 1 1 0 0
1
X
1 0
X
8 W1 1 1 1 1 1 0

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 Serial March (SMarch)
Assume that a RAM has W words, and each
word contains C bits
A Read operation is denoted by R0, R1, or Rx,
depending on the expected value at the serial
output (x=dot care)
For a write operation
operation, the terms W0 or W1 are
used and only the serial input is forced to the
value indicated
The SMarch modified from March C- is as
f llc ( RxW 0 ) C ( R 0, W 0 ) C ; ( R 0, W 1) C ( R1, W 1) C
follows
( R1, W 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 1) C ( R1, W 1) C
( R1, W 0 ) C ( R 0 , W 0 ) C ; ( R 0 , W 0 ) C ( R 0 , W 0 ) C
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 Serial BIST Architecture
BIST GO Done

Controller Timing
Counters
generator
SO SI
Control
lsb msb
Data out
Data in
Address C-1

Multiplexer Multiplexer Multiplexer

C C

Address Data in Data out Control

RAM (W words of C bits)

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 Sharing BIST in Daisy-Chain Style
BIST GO Done

Controller Timing
Counters
generator
g
SO SI

Add
Address R d/W it
Read/Write

Test Collar Test Collar Test Collar

RAM1 RAM2 RAM3

Serial Interface Serial Interface Serial Interface

SI SO SI SO SI SO

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 Sharing BIST in Parallel Style
GO
BIST Done
DeMux

SO SI Timing
g
C
Counters
t Controller generator

Address Read/Write

Test Collar Test Collar Test Collar

RAM1 RAM2 RAM3

Serial Interface Serial Interface Serial Interface

SI SO SI SO SI SO

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 BIST Using Data Decoding/Encoding

n
m wire
n

n
e
m wire

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 Processor-Based RAM BIST

Normal I/Os

Processor

Test Collar
RAM
TPG

Go/No-Go
Comparator

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 NTHU Processor-Programmable BIST

ADDR_cpu
ADDR
ADDR_bist

DATAO
DATAO_sys
DATAO
DATAO_bist
Embedded On-chip Embedded
CPU
Clock_cpu
BIST core Mux_sel
bus Memory

Ctrl_bist control
Ctrl_cpu

DATAI_bist DATAI_sys DATAI

DATAI_cpu

Source: Prof. C. W. Wu, NTHU

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 NTHU Processor-Programmable BIST
BIST core
DATAO_cpu
DATAO_bist
RBG

RAL L
Lowest/highest
t/hi h t addr
dd ADDR_bist
Address
ADDR_cpu Address counter
RAH REA
decorder Up/down
RME RFLAG Read/Write
Control
RIR RED Controller

Match/unmatch
DATAI_bist
DATAI sys
DATAI_sys
Comparator
Data background

Source: Prof. C. W. Wu, NTHU

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 NTHU Processor-Programmable BIST
Data registers

Register Function
RBG Store background data
RAL Store lowest address
RAH Store highest address
RME Store current March element
RIR Instruction register of BIST circuit
RFLAG Status register of BIST circuit
RED Erroneous response of defective cell
REA Address of defective cell

Source: Prof. C. W. Wu, NTHU

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 NTHU Processor-Programmable BIST
BIST procedure Source: Prof. C. W. Wu, NTHU

Test program write data background to RBG

Test program write lowest/highest address to RAL/RAH
Performed by
test program

Test program write March instructions to RME

Test program write START to RIR

(Wa) (Ra,Wa) (Ra,Wa) (Ra,Wa) (Ra,Wa) (Ra)

Compare yes Write ERROR to RFLAG

Data error Write error response to RED
Performed by Write faulty addr to REA
BIST circuit No
No March element
complete

yes
Test program
Write FINISH to RFLAG
take over
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 SOC Testing
A typical SOC chip
ADC FPGA
Flash Memoryy
Wrapper
CPU UDL
DSP
Sink
TAM
Source Test Access Mechanism (TAM)

DRAM
MPEG SRAM SRAM

Source: Y. Zorian, et al.-ITC98

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 SOC Test Access
ADC FPGA
Flash
Off-chip Source/Sink
Wrapper Memory 1. Pins determine bandwidth
CPU UDL DSP 2. More TAM area
Sink
TAM TAM 3. Requires expensive ATE
Source

DRAM
MPEG SRAM SRAM

ADC FPGA
Flash
Wrapper Memory
On chip Source/Sink
On-chip UDL
CPU DSP
1. Close to Core-under-test Sink Sink
2 Less TAM area
2. Source Source

3. BIST IP area DRAM

MPEG SRAM SRAM
4. Requires lightweight ATE

Source: Y. Zorian and E.J. Marinissen

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 1500 Scalable Test Architecture

Source User Defined Parallel TAM Sink

TAM-in TAM-out TAM-in TAM-out

1500 Wrapper
W 1500 Wrapper
W

Fin Fout Fin Fout

Core1 CoreN

WSI WIR WSO WSI WIR WSO

WIP

User-Defined
Test Controller

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 1500 Test Wrapper

Test stimuli WPI WPO Test response

W
WBR

W
WBR
Core
Functional Functional
data data

WBY
WSO
WSI WIR

WSC

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 Memories in SOCs

ADC FPGA
Flash Memory

CPU UDL DSP

DRAM
SRAM SRAM SRAM
BIST
BIST

DRAM
MPEG SRAM SRAM
BIST BIST

N BIST memory cores

Non-BIST BIST
BIST-ready
d memory cores

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 RAM BIST in SOCs
Memory cores in an SOC can be categorized
into two types in term of testability
BIST-ready memory cores
Non-BIST memory cores

An SOC can contain tens or even hundreds of

memory
e o y cores
co es
Although a BIST usually have only about 8
controlling pins
The total BIST controlling pins is huge if each BIST-
ready memory cores has its own BIST controlling pins
The BIST controlling pins should be shared
One solution is using
g memory
y BIST interface

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 Sharing BIST Controlling Pins

ADC FPGA
Flash Memory

CPU UDL
DSP

DRAM
SRAM SRAM SRAM BIST
BIST MBI
MBI MBI
BIST
MBI
BIST
MPEG SRAM DRAM
SRAM

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 Memory BIST Interface (MBI)

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 Memory BIST Interface (MBI)
Instruction Register
Store the instructions
RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL

Bypass
yp Register
g
It is selected if the corresponding memory core is not
tested
Monitor Register
Monitor
o to the
t e error
e o flag
ag ((indicating
d cat g whether
et e a memory
e oy
fault is detected or not)
Status Register
Record the key status values, such as Fail output from
the BIST

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 Testing Multiple Memories with MBI

Using RUN_BIST instruction, we can test multiple

memory cores concurrently
When one or more BIST circuits detect faults, the primary
MSO_N will be high after N-K clock cycles if the concurrent
output of the (K+1) through the N memory cores are fault free

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 Sharing BIST Hardware
BIST controlling signals

TPG &
BIST Controller Comparator

BIST C ll
Collar BIST C
Collar
ll BIST C ll
Collar

RAM 1 RAM 2 RAM N

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 RAM BIST Compiler

S
Source: P
Prof.
f C.
C W
W. Wu,
W NTHU

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 1500-Compilant BIST

T
TAP

Wrapper
Con
TAP

ntroller
P

BIST RAM

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Programmable BISD for RAMs in SOCs
General test architecture

ATE

SOC TAP controller

TAM
Wrapper

Processor + Test Program Memory

Embedded Memory Core

S
Source: A
Appello
ll DD., et. al.l ITC03

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Programmable BISD for RAMs in SOCs
Test Processor

Processor
Wrapper
Control
P1500 Test Program
Instructions Unit

P1500 Address Bus

Memory
Output Data Data Bus
Adapter g
Control Signals

S
Source: A
Appello
ll DD., et. al.l ITC03

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Programmable BISD for RAMs in SOCs
Control Unit
Manage the test program execution
Include an Instruction Register (IR) and
Program Counter (PC)
The control unit allows the correct update of
some registers located in Memory Adapter
This part simplifies the processor reuse in
different applications without the need for any
re-design

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Programmable BISD for RAMs in SOCs
Memory Adapter
Control Address registers
g (Current
( _address))
Control Memory registers
Current_data
Received_data
R i d d t
Control Test registers
Dbg
g_index,, Step,
p, Direction flag,
g, and Timer registers
g
Result registers
Status, Error, and Result registers
Some constant value registers
Add_Max, Add_Min, DataBackGround, Dbg_max

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Programmable BISD for RAMs in SOCs
Processor instruction set

I t ti
Instruction M
Meaning
i
Current_address Add_Max
SET_ADD
Direction flag BACKWARD
Current_address Add_Min
RST_ADD
g FORWARD
Direction flag
Current_data DataBackGround[Dbg_index]
STORE_DBG
Dbg_index Dbg_index+1
INV_DBG Current_data NOT (Current_data)

READ Current data Memory[Current_address]

Current_data Memory[Current address]

WRITE Memory[Current_address] Current_data

Source: Appello D., et. al. ITC03

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Programmable BISD for RAMs in SOCs
Wrapper

WSI

WRCK W
WRSTN C
TAP controller

D
W W

Me
ShiftWR W R

emory
D
c

UpdateWR I Processor B
R R R
CaptureWR
W
SelectWIR B Test
Y Program CORE

WSO

Wrapper

Source: Appello D., et. al. ITC03

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 Summary

ROM BIST has been presented

p
ROM-based and FSM-based RAM BIST have
been introduced
Serial BIST methodology for embedded
memories
i h has also
l presented
t d
BIST approaches
pp for testing
g multiple
p RAMs in an
SOC have also been addressed

EE, National Central University Jin-Fu Li 51

 References
[1] A. K. Sharma,Semiconductor memories technology, testing, and
reliability,
li bilit IEEE P
Press, 1997
1997.
[2] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal,Serial interfacing for
embedded-memory testing, IEEE D&T, pp.52-63, apr. 1990.
[3] C. W. Wu,VLSI testing & design for testability II: Memory built-in self-
test, http://larc.ee.nthu.edu.tw/~cww/
[4]C. H. Tsai and C.-W.
[4]C.-H. C. W. Wu, ``Processor-programmable
Processor programmable memory BIST for
bus-connected embedded memories'', in Proc. Asia and South Pacific
Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325-330
[5]C.-W
[5]C W. Wang,
Wang C C.-F
F. Wu,
Wu JJ.-F
F. Li,
Li CC.-W
W. Wu,
Wu TT. Teng,
Teng KK. Chiu,
Chiu and H.
H -P
P. Lin
Lin, ``A
A
built-in self-test and self-diagnosis scheme for embedded SRAM'', in Proc.
9th IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp. 45-50
[6]D. Appello,
[6]D Appello FF. Corno
Corno, M.
M Giovinetto,
Giovinetto M
M. Rebaudengo
Rebaudengo, and M
M. S
S. Reorda
Reorda,A
A
P1500 compliant BIST-Based approach ro embedded RAM diagnosis,
pp.97-102, MTDT, 2001.
[7]J. F
[7]J F. Li
Li, H
H. JJ. H
Huang, JJ. B
B. Ch
Chen, C.
C P.
P Su,
S C.C W.
W Wu,
W C.
C Cheng,
Ch S.
S I.
I Chen,
Ch C.
C Y.
Y
Hwang, and H. P. Lin,A hierarchical test methodology for systems on chip,
IEEE Micro, pp. 69-81, Sep./Oct., 2002.
[8]S. Mourad and Y. Zorian,Principles off Testing Electronic Systems, John
Wiley & Sons, 2000.
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