Pipelining

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Parallel processing

Provide simultaneous data processing

Concurrent data processing

Increase computational speed of computer system

Faster execution time

Increase throughput

Speed up computer processing capability

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Parallel processing under

pipelining
Pipelining
Implementation technique in which multiple
instructions are overlapped in execution to make
processors fast

Tasks operate concurrently

Take less time

Improves throughput
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Pipeline processing
Any operation that can be decomposed into a
sequence of sub operations

In a pipelined processor, different sections of the

processor perform different steps of the
instruction cycle for different instructions at a
given time.

Application
Repeat same task many times
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General structure of a four

segment pipeline

latch
latch

latch
latch
Segment 1 Segment 2 Segment 3 Segment 4

input
H1 H2 H3 H4

clock

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Operands pass through all 4 segments in a fixed

sequence

Each segment consist of a combinational circuit Si

performs a sub-operation over the data stream

Segments separated by registers Ri

Hold the intermediate results between the stages

Task total operation performed in the pipeline

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Assume task T:perform 4 operations

A1,A2,A3,A4

4 tasks executed in 4 segments

To complete 4 instructions
Non pipelined processor (4 x 4)= 16 clock cycles
Pipelined processor = 7 clock cycles =
4 (segment ) + 4(task) -1
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Overlapped execution of
four tasks using a pipeline

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For example:

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Let
Ti - propagation delays of segment i
TL - propagation delay of latch
T- pipeline clock period

T = max(T1,T2,Tn)+ TL
The segment with max delay(bottleneck) decides
pipeline clock period T

Pipeline clock frequency = reciprocal of T

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Consider
the execution of m tasks
using an n-segment pipeline

Ist task will be completed after n clock cycles

m-1 tasks are shipped out at the rate of one task per
pipeline clock

n+m-1 clock cycle periods are required to complete m

tasks using an n- segment pipeline

If all m tasks are executed without any overlap, mn clock

periods are needed. eee/dsdca/sv
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Speed, gained by n segment pipeline

Speed up= = p(n)
+

/
=

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p(n)n when m is very large

lim = lim = =n
+1

For large number of tasks performed in a

pipeline ,the speed of processing increases n
times as compared to the conventional
sequential machine
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Throughput

Throughput of an n segment pipeline,u(n) =

number of tasks computed per unit time

= =
+

For large value of m, u(n) approaches 1/T,

pipeline frequency

Throughput of an ideal pipeline = reciprocal

of its clock period eee/dsdca/sv
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Efficiency of an n segment pipeline = E(n)

()
= =

When m is large E(n) approaches 1

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Example
For a 4 segment floating point pipeline the
propagation delays of the segments are given
below.
Assume T1= 40ns, T2= 100ns, T3=180ns, T4=60ns, Tl
=20ns
a) Determine the pipeline clock rate
b) Find the time taken to add 1000 pairs of floating
numbers using this pipeline
c) What is the efficiency of the pipeline when 2000
pairs of numbers are added?
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a) Determine the pipeline

clock rate
pipeline clock period
= max(T) + Tlatch
= 180ns + 20ns = 200ns

Pipeline clock rate = 1/T = 1/200ns =5MHz

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b)Find the time taken to add

1000 pairs of floating
numbers using this pipeline

(4 segments + 1000 -1)200ns = 200.6sec

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c)What is the efficiency of

the pipeline when 2000
pairs of numbers are added?

() 2000 4
+1
= = =0.998 = 99.8%
4+20001

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Thank you

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