IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO.
4, AUGUST 2015
Advanced Features and Industrial Applications
of FPGAsA Review
Juan J. Rodrguez-Andina, Senior Member, IEEE, Mara D. Valds-Pea, Member, IEEE,
and Mara J. Moure, Member, IEEE
AbstractField programmable gate arrays (FPGAs) have
established themselves as one of the preferred digital implementa-
tion platforms in a plethora of current industrial applications, and
extensions and improvements are still continuously being included
in the devices. This paper reviews recent advancements in FPGA
technology, emphasizing the novel features that may significantly
contribute to the development of more efficient digital systems
for industrial applications. Special attention is paid to the design
paradigm shift caused by the availability of increasingly power-
ful embedded (and soft) processors, which transformed FPGAs
from hardware accelerators to very powerful system-on-chip
(SoC) platforms. New analog resources, floating-point operators,
and hard memory controllers are also described, because of the
great advantages they provide to designers. Software tools are
being strongly influenced by the design paradigm shift, which
requires from them a much better support for software developers.
Focusing mainly on this issue, recent advancements in software
resources [intellectual property (IP) cores and design tools] are
also reviewed. The impact of new FPGA features in industrial
applications is analyzed in detail in three main areas, namely
digital real-time simulation, advanced control techniques, and
electronic instrumentation, with focus on mechatronics, robotics,
and power systems design. The way digital systems are being cur-
rently designed in these areas is comprehensively reviewed, and a
critical analysis of how they could significantly benefit from new
FPGA features is presented.
Index TermsAdvanced control, digital real-time simu-
lation, electronic instrumentation, embedded systems, field
programmable gate arrays (FPGAs), hardware-in-the-loop.
I. I NTRODUCTION
A DVANCEMENTS in field programmable gate array
(FPGA) technology are continuously being reported.
High speed and flexibility, possibility of taking advantage
of the inherent parallelism of many systems and algorithms,
short time-to-market, good cost-performance tradeoff, large
amount of embedded resources, and availability of special-
ized intellectual property (IP) cores make FPGAs the preferred
implementation platform in many industrial applications.
Until a relatively recent time, there were two separate
approaches to design digital systems for industrial con-
trol applications: a sequential (software) approach based on
either microcontrollers or digital signal processors (DSPs) and
Manuscript received January 30, 2015; revised April 08, 2015; accepted
April 30, 2015. Date of publication May 07, 2015; date of current version July
31, 2015. Paper no. TII-15-0148.
The authors are with the Department of Electronic Technology, University
of Vigo, Vigo 36310, Spain (e-mail: jjrdguez@uvigo.es; mvaldes@uvigo.es;
mjmoure@uvigo.es).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TII.2015.2431223
1551-3203 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
853
associated embedded peripherals, and a parallel (hardware)
approach, usually restricted to solve specific parts of problems
requiring high-performance solutions. Industrial penetration of
this second approach was conditioned by the limited knowledge
of the technology and the design tools, lack of maturity of these
tools, price, and lack of some specialized hardware function-
alities. One of the major impediments to a wider adoption of
reconfigurable computing as a new paradigm is the complexity
of programming FPGAs and the need for some hardware design
expertise to tame them [1].
As FPGAs evolved taking advantage of fabrication technol-
ogy scaling down, vendors started to develop soft processor
cores that may be implemented from standard FPGA resources,
as well as to integrate embedded (hard) processors in their
devices. This trend has seen a tremendous continuous devel-
opment, to the extent that current solutions are countless.
Because of this, the past dichotomy of design approaches
resulted in a paradigm shift that constitutes the major cur-
rent asset of FPGAs, which cannot be just seen as hardware
accelerators anymore, but as very powerful system-on-chip
(SoC) platforms. The combination in a single chip of embedded
(or soft) processors with custom optimized, high-performance
hardware peripherals has open the door for the unlimited appli-
cation of FPGAs in all areas of digital design for industrial
applications.
Not surprisingly, the characteristics, design tools and method-
ologies, and application areas of these devices have been
extensively analyzed over the past years [2][9], just to mention
the works specifically focused on industrial systems. However,
being a relatively mature but also still young area, new features
are continuously being developed. Therefore, in the authors
opinion, a review of the most recent advancements in FPGA
technology will be useful for the industrial informatics research
community. Thus, the aim of this paper is to provide such
review together with an analysis of the impact the new features
of current devices may have in the design of digital systems
for industrial applications. The analysis is mainly carried out
in three areas, namely digital real-time simulation, advanced
control techniques, and electronic instrumentation, with focus
on mechatronics, robotics, and power systems design.
This paper is structured as follows. Novel hardware resources
currently available in FPGAs are described in Section II.
Section III deals with recent advancements in software
resources (IP cores and design tools). Industrial applications
where the new hardware resources are being, or expected to be
soon, used are analyzed in Section IV. Finally, conclusions are
summarized in Section V.
854 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015

Fig. 1. fPLL block (adapted from [11]).

II. H ARDWARE R ESOURCES

Hardware resources in FPGAs greatly differ among manu-
facturers and devices. The resources providing most advantages
to designers were analyzed in [2]: integrated functional blocks,
I/O signal conditioning, partial reconfiguration, IP protection,
and special (e.g., radiation-tolerant) devices. State-of-the-art
fabrication technologies (14-nm, 3-D tri-gate transistors) are
enabling the integration of even more advanced features in
todays FPGAs, which in some cases account for more than Fig. 2. XADC application to motor control (adapted from [14]).
50 million equivalent logic gates and may achieve operat-
ing frequencies in excess of 500 MHz while keeping power
consumption within reasonable limits. In fact, although one
of the problems traditionally associated with FPGAs is their
high power consumption compared to that of microcontrollers,
in complex applications where multiple devices need to be
used, the power consumption of FPGAs may be comparable
to that of the microcontrollers required to implement the same
processing [10].
Among those features, this section focuses on the ones
allowing modern efficient digital systems for industrial applica-
tions (often based in complex algorithms) to be implemented,
because of the high computing power they provide and/or the
low execution time they achieve.

A. Analog Resources
One of the main past limitations of FPGAs was related to
the lack of analog resources, in particular analog-to-digital and
digital-to-analog converters (ADCs and DACs). The main new
analog resources in current FPGAs are as follows.
1) Fractional phase-locked loops (fPLLs) from Altera allow
fractional frequency synthesis to be implemented. As
shown in Fig. 1, this feature is achieved by placing
a deltasigma modulator in the feedback loop, which
allows the dividing factor to be dynamically modified
cycle by cycle, so the resulting equivalent (average) value
is not integer. The deltasigma modulator can be con-
trolled by external signals, adding further flexibility. With
this structure, the performance of reference oscillators
for digital communications is improved. In many current
industrial systems, high-speed, reliable communication
interfaces are required, e.g., for control or monitoring
purposes [12] or in digital real-time simulation [13].
2) Analog-to-digital conversion. Xilinx 7 series analog
mixed signal (AMS) technology provides high-quality
analog-to-digital conversion and customizable signal con-
ditioning through the XADC block, which includes two
12-bit, 1-Msps ADCs, two track-and-hold amplifiers
allowing differential sampling, a multiplexer allowing up
Fig. 3. SmartFusion ACE block (adapted from [15]).
to 17 input channels to be accessed, as well as power sup-
ply and temperature sensors. A sample application of the
XADC block to motor control is depicted in Fig. 2.
3) Analog compute engine (ACE). Microsemi SmartFusion
FPGAs include a so-called ACE block, capable of con-
trolling up to three 12-bit, 600-ksps ADCs with sample
and hold, as well as three 24-bit DACs. As shown in
Fig. 3, ACE consists of two functional blocks, similar
to simple custom microcontrollers: sample sequencing
engine (SSE) and postprocessing engine (PPE). Among
other functionalities, SSE allows ADC resolution and
sampling period to be configured, as well as an external
start signal to be used. PPE allows different filters or lin-
ear transforms to be applied to input signals. This block
can be advantageously used for power converters control,
like in [16], where the direct power control of a three-
phase PWM (Pulse Width Modulator) boost rectifier is
described.
RODRGUEZ-ANDINA et al.: ADVANCED FEATURES AND INDUSTRIAL APPLICATIONS OF FPGAs 855

Fig. 4. Arria 10 FPGA variable-precision DSP block for floating-point arith-

metic operations (adapted from [11]).

B. Floating Point Arithmetic

Another important past limitation of FPGAs was related to
the very limited amount of resources available to implement
floating-point operations. As a consequence, many designs
were adapted to work in fixed point. Mantissa alignment and Fig. 5. SmartFusion architecture (adapted from [17]).
normalization consume a huge amount of resources in tra-
ditional devices, thus also resulting in slow operation. This
problem is overcome by the availability of new DSP blocks sup-
porting both IEEE 754 single-precision and double-precision
formats, as Altera variable precision (Fig. 4) DSP blocks. IEEE
754-compliant DSP blocks include adders and multipliers capa-
ble of operating at the same (high) clock frequency as their
fixed-point counterparts. Other features of these blocks are
internal registers for coefficients and systolic registers, which
allow vector-based functions (such as Fast Fourier Transforms
or Finite Impulse Response filters) to be implemented by
interconnecting several floating-point DSP blocks that operate
concurrently. Vendors provide sets of floating-point mathematic
functions (many of which comply with specifications such
as OpenCL 1.2) optimized for their implementation in these
blocks.

C. Embedded Processors Fig. 6. Arria 10 hard processor system (adapted from [18]).

FPGA-based SoC design (resulting in the so-called Field

Programmable SoCs, FPSoCs) has experienced an extraordi-
nary growth over recent years. Vendors have developed specific
FPSoC architectures that optimize the connection of either
soft or embedded processors with hardware peripherals and
distributed logic.
Soft processors are discussed in Section III-A. Regarding
embedded processors, Altera, Xilinx, and Microsemi currently
offer FPSoC solutions including hardware implementations of
different ARM processors. Microsemi SmartFusion devices
include a Cortex-M3 processor, as shown in Fig. 5, whereas
Altera and Xilinx opted for dual-core Cortex-A9 processors for
their most recent FPSoC families, Arria 10 (Fig. 6), Arria V,
Cyclone V, and Zynq-7000. The dual-core approach is partic-
ularly suitable for real-time applications, where the operating
system and the main program may run in one of the cores,
whereas the other is devoted to time-critical functions. In both
Altera and Xilinx devices, the processor and the FPGA fabric
are supplied independently, and it is possible to turn the lat-
ter off to reduce power consumption. In addition, logic can be
fully or partially reconfigured from the processor, as reported
in [19]. Xilinx went recently one step beyond by introduc-
ing UltraScale+ devices, featuring a quad-core ARM Cortex
A53 and dual-core ARM Cortex R5 processing system, also
including an ARM Mali-400 MP2 graphics processor unit.
An application example of embedded processor-based solu-
tions is presented in [20], where a fuzzy controller for perma-
nent magnet synchronous machines (PMSMs) is implemented
in a SmartFusion device by combining the Cortex-M3 processor
with distributed logic in the FPGA fabric.
D. Hard Memory Controllers
Arria V and 10 families from Altera include dedicated
hardware for access control to external DDR/DDR2/DDR3/
DDR4 memories (Fig. 7). Spartan-6 and Virtex-6 families
from Xilinx also include DDR3 hard memory controllers,
enhanced in series 7 families of devices and extended in the
Ultrascale family to support DDR4 memories. Two types of
hard DDR/DDR2/DDR3 memory controllers are available in
Microsemi SmartFusion2 devices (Fig. 5): the MSS controller
856 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015
Fig. 7. Arria 10 hard memory controller (adapted from [21]).
allows memory to be accessed from the ARM Cortex-M3 core,
whereas the Fabric controller allows memory to be accessed
from logic implemented in the FPGA fabric. Compared to IP
core-based soft solutions, hard controllers achieve lower laten-
cies and higher access frequencies. They support different data
widths, reordering of instructions and data for out-of-order exe-
cution, definition of priorities for reduced latency, streaming
read or write operations for massive data transfer, operation
modes for continuous access to random sequences of memory
addresses, multiport interfaces, low power consumption modes,
user-controlled partial refresh cycles for reduced consumption,
or error-correcting algorithms.
The implementation in Virtex-6 and Virtex-7 of a vision sys-
tem for moving object detection is reported in [22], where
images are stored in DDR3 memory, which is accessed from
the FPGAs through a hard controller.
E. Application-Specific Devices
Differently from vendors targeting application domains as
wide as possible with their devices, some companies have
specialized in application-specific solutions. These are not cur-
rently focused on industrial applications, but are mentioned
here as a prospect of what the future may bring in this regard to
industrial systems.
Tabula proposes a novel configurable architecture called
Spacetime in its ABAX2 3PLD family. The concept is based
on the ability of these devices to be reconfigured at frequencies
in the GHz range. In this way, resources can be utilized sev-
eral times for different purposes during each cycle of the main
system clock. The target system is divided in subsystems that
are actually present in the device only during a fraction of the
main clock cycle. The process is transparent for the user, who
is serviced as if all logic had been implemented in the device all
the time. The main advantage of this approach is that systems
can be implemented with less resources and shorter connec-
tions, resulting in shorter delays and, as a consequence, higher
effective operating frequencies. Design is carried out through
Stylus, a tool following the usual configurable system design
flow, which makes transparent to the user the process of fit-
ting the system into the Spacetime architecture. The limited
amount of currently available embedded hardware resources
restricts application fields mainly to high-speed communication
systems, such as routers and switches.
Fast dynamic reconfiguration can provide significant advan-
tages in some industrial applications, for instance to apply
different control strategies optimized for different plant oper-
ating conditions, as in [23] for the case of electric motors,
whose operating conditions may be subject to large variability
Fig. 8. Estimated FPGA design cost versus scale of integration (data from
[24]).
in an industrial facility. In this case, transitions between dif-
ferent control strategies (open-loop voltage/frequency control,
field-oriented control, direct torque control), associated with
different FPGA configurations that are dynamically changed,
must be smooth enough to guarantee a stable behavior of the
motor.
Quicklogic focuses on mobile applications with its customer-
specific standard product (CSSP) solution, supported by the
PolarPro and ArticLink nonvolatile (antifuse) families of
devices. CSSP is based on the combination in a single chip
of hardware functional blocks widely used in mobile systems
with configurable logic. Hardware functional blocks are also
configurable, allowing services to be customized according to
different regulations or user preferences. PolarPro devices are
intended to provide connectivity solutions, whereas ArticLink
is oriented to displays and visualization functions.
III. S OFTWARE R ESOURCES
Specific powerful software tools are needed to take advan-
tage of the many different complex hardware features available
in FPGAs [2]. The increasing amount of hardware resources
included in current FPGAs results in more and more complex
systems. As a consequence, increasing design and verification
efforts are required. Thus, it is usually difficult to take the most
advantage of available resources. The significant increase in
design cost as technology scales down is highlighted in Fig. 8.
The most significant recent advancements in terms of FPGA
software, namely IP cores and design tools, are analyzed in
Sections III-A and III-B, respectively.
A. IP Cores
The availability of suitable IP cores can dramatically sim-
plify the design of complex systems. The importance of IP cores
in modern design can be clearly noticed from the fact that the
semiconductor IP market grows two times faster than the over-
all semiconductor market [25]. The FPGA design composition
trends from 2012 to 2014 are shown in Fig. 9, where it can be
clearly noticed that the relative amount of newly designed logic
decreases, whereas IP core usage increases, the trend being the
latter becomes dominant.
RODRGUEZ-ANDINA et al.: ADVANCED FEATURES AND INDUSTRIAL APPLICATIONS OF FPGAs
Fig. 9. FPGA design composition trends in 20122014 (data from [26]).
The most widely used IPs for FPGAs are soft proces-
sors. Although other soft processors are available, from the
comprehensive literature analysis carried out by the authors,
it can be clearly concluded that Xilinx MicroBlaze and Altera
Nios II continue to be the most widely used soft processors
in the application domains considered. No major changes have
occurred to them recently, but they have been improved by the
addition of new peripherals and instructions. More important,
memory access has been optimized, e.g., using the advanced
eXtensible interface (AXI). For instance, the latest MicroBlaze
versions come with new general purpose input (GPI) interrupts,
improved latency in interrupt routine calls, or programmable
baud rate universal asynchronous receiver/transmitter (UART).
They also include an AXI System Cache soft-peripheral that
can be used in any design based on a memory controller and
works as a level 2 cache, improving system performance.
In spite of the widespread use of these FPGA-vendor-
specific soft processors, there is a current trend in industry
toward the utilization of standard processors. Soft ver-
sions of commercial (non-FPGA-vendor-specific) microcon-
trollers have been developed for instantiation in FPGA designs.
Examples include ARM Cortex-M1, Freescale ColdFire V1,
or MIPS Technologies MP32. For instance, in [27], an ARM
Cortex-M1 hard processor was implemented in both Xilinx and
Altera FPGAs to provide designs with an IEEE 754-compatible
floating point unit.
As discussed in Section II-C, currently FPGA vendors also
include hardware implementations of different ARM proces-
sors in their devices, reinforcing the trend toward the use of
standard processors instead of specific ones. These solutions
(either hard or soft) have the advantages of being FPGA-
technology-independent, low-cost, well-known architectures,
supported by many programming tools, compatible with many
operating systems, and allowing code reuse.
An issue of increasing importance in this context is the con-
nectivity of IP cores with the other elements of a design. This is
a critical aspect in complex systems, because the advantages
of using IP cores can be compromised by poor connectiv-
ity. Therefore, current IP cores usually come with standard
interfaces (such as AXI), which ease integration and avoid con-
nectivity errors. An example of such solution is AXI CAN from
Xilinx.
857
The application domains where IP cores are most widely
used are automotive and transportation, consumer electronics,
cryptography, communications, and medical and healthcare.
Examples of commercially available IPs for industrial applica-
tions are as follows:
1) IP cores for power control (space-vector PWM, unipo-
lar H-bridge PWM, or AC drivers, among others) from
ELMG;
2) PROFINET switch from SoC-e, targeting industrial
automation solutions;
3) SpectraChip from RFEL Ltd., a frequency spectrum ana-
lyzer oriented to low-cost FPGAs;
4) LogicBRICKS from Xylon, which ease the development
of complex video processing systems, such as for video
surveillance multi-head 360 view cameras.
Last but not least, it is worth mentioning organizations aimed
at promoting open IP cores, such as Free IP Project or Open
Cores.
B. Design Tools
FPGA vendors usually provide proprietary software tools
allowing designs to be synthesized and implemented in their
devices. Current vendor-specific design tools are mostly based
on the same core functionalities described in [2], with the addi-
tions required to support the new hardware resources analyzed
in Section II. For instance, the LogiCORE IP XADC is avail-
able in Xilinx tools to automate the configuration of the XADC
block described in Section II-A, and Altera provides IP cores
and DSP Builder (Simulink) models supporting floating-point
operations based on the DSP blocks described in Section II-B.
The main evolution of design tools comes from the needs
arising from the integration of complex processors in FPGA
devices to create powerful FPSoC platforms. The two areas
where software tools currently focus in this regard are system-
level design specification and validation.
Traditionally, hardware designers used a combination of
high-level synthesis (HLS) tools with IP cores to generate their
circuits. Embedded and soft processors came with the need for
specific tools to support them, such as Xilinx SDK (formerly
EDK), Altera SOPC Builder, Cypress PSoC, Microsemi Libero
SoC, or Lattice LatticeMico System.
Because of the paradigm shift caused by the tremendous
development of FPSoC platforms, described in Section I, soft-
ware now plays a major role in FPGA-based design, and
designers profile changed accordingly. Software designers are
generally not familiarized with hardware description languages
and HLS tools. As a consequence, FPGA vendors are reori-
enting their tools to work at higher abstraction levels (using
C, C++ or, more recently, OpenCL), therefore making it eas-
ier for software developers to design, debug, and use hardware
components. Vivado HLS from Xilinx allows direct implemen-
tation of a C description without the need for an intermediate
structural description. However, being a HLS-oriented tool, it
is more advantageous for hardware designers, capable of ana-
lyzing the result of the synthesis of a behavioral description in
a parallel structure. In contrast, SDSoC (also from Xilinx) is
totally oriented to programmers, allowing not only the software
858 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015

to be executed by the processor (ARM Cortex or NEON) but

also hardware components and interfaces between both parts to
be fully specified in C/C++. SDK for OpenCL from Altera is
based on the free programming model OpenCL. It allows hard-
ware components to be described in C language. In addition,
it includes a set of tools to emulate C code, extract information
about the parallel structure that will be generated from this code
(in the case of hardware components), as well as to compile
the code and to generate the hardware structures. Among other
options, several CPUs (ARM Cortex-A9, IBM Power Series,
x86) and memories (DDR SDRAM, QDR SRAM, FPGA inter-
nal memory) are supported, as well as fixed- and floating-point
operations. The limitations of using OpenCL in FPGA design
are analyzed in [28], where authors evaluate the SDK for
OpenCL tool through the implementation of a multi-FPGA
architecture oriented to high-performance computing. Although
they conclude that the tool allows a significant part of the design
process to be automated, thus greatly reducing design time, they
also identify generic problems related to the translation of C
code to HDL and the integration of the generated HDL code
with other hardware parts of the system.
There also exist a lot of third-party FPGA design tools.
Cadence Design Systems, Mentor Graphics, and Synopsys are
the three main partners of FPGA vendors in the software arena,
providing tools for system-level design (Cadence C-to-Silicon
Compiler, Mentor Graphics HDL Designer, and Synopsys
Model Compiler) and simulation (Cadence Incisive Enterprise
Simulator, Mentor Graphics ModelSim, and Synopsys VCS).
Other third party tools are Riviera-PRO (simulation) and
Active-HDL (verification) from Aldec, Analyze RTL (verifi-
cation) and Create Timing Constraints (constraints generation)
from Blue Pearl, and SpyGlass (RTL verification) and SpyGlass Fig. 10. Traditional versus FPSoC-based digital systems.
Constraints (constraints generation) from Atrenta.
Last but not least, the design of SoCs based on the Cortex many recently published works based on the combination of
family of processors is supported by ARM Development Studio separate digital processing and configurable logic chips [29]
5 (DS-5). [34], as analyzed in detail in the following sections. Migration
It is important to note that FPGA design tools are often a from digital processor-based solutions to FPGA-based ones
source of strong controversy between companies and users, can be done in a relatively easy way by taking advantage of
because there is usually a significant gap between the features embedded or soft processors, where code already validated in
and advantages claimed by companies and the users experi- the previous platforms can be reused. At the same time, time-
ence. By just having a look at the many users forums available critical functionalities can be moved to hardware. When huge
on the web, this fact can be clearly ascertained, being one of amounts of data have to be managed, external DDR or Flash
the main limiting factors for an even more widespread use of memories are required, as described in [35] for a robot audi-
FPGAs. tion application. The hard memory controllers described in
Section II-D can obviously provide significant advantages in
this type of systems. The availability of DSP blocks capable
IV. I NDUSTRIAL A PPLICATIONS
of efficiently implementing floating point operations, as well as
This section analyzes the impact the new hardware features of embedded ADCs and DACs, can also boost applicability of
of current devices may have in the design of digital systems the new FPGA devices in many industrial informatics domains.
for industrial applications. Three main areas are considered, All these features are highlighted in Fig. 10, where the gen-
namely digital real-time simulation, advanced control tech- eral structure of traditional (DSP and/or microcontroller-based)
niques, and electronic instrumentation, applied to mechatron- digital systems can be compared to that of currently available
ics, robotics, and power systems design. This choice is based FPSoCs.
on the fact that in these application domains, there is a current
demand for systems capable of providing fast digital implemen-
A. Digital Real-Time Simulation
tations of complex algorithms, e.g., for switching purposes.
As mentioned in Section I, the major asset of FPGAs is their Hardware-in-the-loop simulation (HILS) has become a very
capability as powerful SoC platforms. However, there are still popular technology, particularly for real-time simulation of
RODRGUEZ-ANDINA et al.: ADVANCED FEATURES AND INDUSTRIAL APPLICATIONS OF FPGAs
(complex) power systems, where it allows development time,
cost, and time to market to be reduced [36]. On one hand, sim-
ulations are much shorter than when using software tools like
MATLAB/Simulink. On the other hand, it is possible to check
the behavior of some components of the system under faulty
[37] or extreme operating conditions without actually compro-
mising system integrity. HILS requires very accurate hardware
models of the target (parts of the) system to be available, as
well as suitable algorithms (that may be quite complex) to be
used. In many cases, the limiting factor is the simulation time
step, which must be short enough (even below 1 s) to allow
transients to be accurately modeled, especially when dealing
with high-speed power switches. In this context, the ability
of FPGAs to provide simulation time steps in the ns range,
together with the availability of memory blocks and complex
arithmetic blocks, as well as their parallelism and reconfigura-
bility, make them very suitable for the development of HILS
platforms.
A hardware platform for digital real-time simulation and con-
trol applications, based on DSPs and FPGAs, is introduced
in [13]. The DSPs are used as main processing elements
(in charge, among others, of floating-point calculations),
whereas the FPGAs act as communication links and copro-
cessors. External ADCs and DACs are used to implement
analog I/O channels. In spite of the good results, authors
state as one limiting factor of their approach the slow
access from the DSP to the FPGA. Another similar DSP-
FPGA platform for digital real-time simulation, targeting in
this case the analysis of a permanent magnet synchronous
generator, is described in [29]. Real-time digital simula-
tion of PMSMs is also addressed in [38], whereas modular
multilevel converters are targeted in [37] and [39]. These
solutions, based on system-level modeling, are mostly ori-
ented to a behavioral analysis (waveforms, harmonics, and
the like) and use ideal models of switching devices. Going
one step beyond in terms of the large computational power
required, device-level modeling is necessary when addressing
the analysis of high frequency effects (device stresses, para-
sitics, or electromagnetic interference noise issues) and their
suppression [40].
An HILS platform to simulate resonant inverters for induc-
tion heating appliances is proposed in [41]. It consists of an
FPSoC based on the MicroBlaze soft processor, which is in
charge of nontime-critical tasks. The design was carried out
in C language and translated into HDL language using the
high-level synthesis tool Vivado from Xilinx, described in
Section III-B. In [42], two FPGAs are used to build an HILS
system to validate the controller of a three-phase PWM recti-
fier. The rectifier is emulated in real time with a pure hardware
implementation in one of the devices, whereas the controller
is implemented in the other as an FPSoC based on an ARM
Cortex-M3 core.
HILS platforms are also used in other areas. For instance, the
one presented in [43] addresses Computer Numerical Control
machines. It consists of a host PC, whose main tasks are those
associated with a graphical user interface for the design, imple-
mentation, and execution of the HILS, a DSP that acts as main
computing engine for the numerical solving of the differential
859
equations describing the target plant, and an FPGA interfacing
the HILS with the controller hardware under test.
One important issue in FPGA-based HILS is the choice
between using fixed- or floating-point arithmetic, which have
opposite effects on accuracy and latency. One such analysis
in the case of modeling of electric machines is carried out
in [44], where floating-point operators are implemented using
distributed logic and basic embedded arithmetic blocks (multi-
pliers or DSP blocks). The use of the new IEEE 754-compatible
DSP blocks would make floating-point implementations much
faster and more efficient, eliminating the need for using fixed-
point arithmetic to avoid latency problems.
Two models to determine the optimal resolution to be used
in the representation of state variables of power converters for
FPGA-based HILS are proposed in [45], where they are val-
idated for the case of a boost converter. The resolution used
for state variables has a direct impact on both complexity
and clock frequency, and hence the importance of an opti-
mal choice. In this work, authors use fixed-point arithmetic,
since floating-point operators would consume a huge amount
of logic resources in the device used, also impacting operating
frequency. This limitation could be avoided by taking advan-
tage of the DSP blocks with double-precision floating-point
capabilities available in current devices.
In spite of the clear advantages of FPGA-based HILS, effi-
cient modeling may be too complicated for nonexperienced
designers. Because of this, some works have been devoted
to the development of platforms including graphic interfaces
aimed at simplifying the process and making FPGA design
and implementation details transparent to users. An ultra-low
latency digital processor core for simulation of power systems
is proposed in [46] and used in [47] to verify the operation of
two control algorithms for a voltage source converter (VSC)
connected to a smart grid. An electric circuit solver tool that
allows simulating in an FPGA any RLC circuit with ideal
power switches (IGBTs, MOSFETs, GTOs, SCRs, or diodes)
is proposed in [48]. The tool includes specialized modules for
modeling motors and inverters.
B. Advanced Control Techniques
Digital control of power systems is one of the most interest-
ing current research topics in industrial electronics. Although
most digital controllers in this area are still based nowadays
on microcontrollers or DSPs, these solutions have two main
drawbacks, related to the execution times of control algorithms
and the lack of flexibility to interface with the analog environ-
ment (ADCs and DACs). Both drawbacks can be dramatically
mitigated by the use of modern FPSoCs, which, on the other
hand, require for this kind of applications a careful partitioning
of tasks between hardware and software components. Generic
partitioning methods are usually based on optimizing area,
processing time, or power consumption. When dealing with
power systems, however, other important control parameters
must be taken into account, such as bandwidth [49], stability
margin [50], or disturbance rejection [51]. Limited amounts
of specialized embedded resources (such as memory blocks,
complex arithmetic operators, or DSP blocks) may also be a
860 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015
problem. In [52], authors propose a hardware/software codesign
method (considering both control and resource restrictions),
which is validated in the design of a speed controller for a syn-
chronous motor [based on an extended Kalman filter (EKF)]
implemented using a MicroBlaze soft processor and FPGA
fabric.
Accurate identification of the parameters of the target sys-
tem is of paramount importance for the development of suitable
control algorithms. The FPGA implementation of an observer
for the state-of-charge estimation in lithium-polymer batteries
is presented in [53] aiming at achieving real-time operation
while taking advantage of FPGA parallelism to manage indi-
vidual cells or modules in a battery pack. A system combining
a microcontroller and an FPGA for measuring stator induc-
tance and resistance in PMSMs is presented in [30]. The (inner)
current control loop is fully implemented in the FPGA, to
ensure minimum delays and thus good control performance.
The required ADC interface is also implemented in the FPGA.
The less time-sensitive, higher level control loops (speed and
position) are implemented in the microcontroller. This sys-
tem would greatly benefit from FPSoC architectures and the
availability of embedded ADCs.
Important issues in the implementation of digital controllers
for power systems are also analyzed in [5]. Not surprisingly,
the hardware implementation of relatively complex arithmetic
operations (e.g., divisions) is preferred to software solutions.
Authors conclude that for systems with strong timing require-
ments (e.g., switching frequency above 1 MHz), hardware
solutions are the only ones viable in practice. The use of over-
sampling techniques (taking advantage of reduced processing
times) allows a single controller to be used for several subsys-
tems and a better synchronization among them to be achieved.
Hardware parallelism is required in high-performance power
segmentation applications, where multiple power channels
must be concurrently controlled. Very interestingly, some of the
most challenging needs identified by the authors of that paper
(efficient floating point computations and analog/digital inter-
faces) can now be addressed with the new features available in
current FPGAs.
A DSP-based algorithm for computing the voltage unbalance
factor (VUF) in three-phase systems is presented in [31], clearly
outperforming the standard method IEC 61000-4-27. In spite of
the good results obtained, authors state that, although VUF tests
should be run in continuous mode, because of the limitations of
the DSP in terms of both speed and processing power, they can
only be run at time intervals between 0.1 s and 3 min. This prob-
lem could be alleviated by the use of FPGAs to concurrently run
some parts of the algorithm.
Current control of three-phase VSCs is addressed in [54],
where the grid synchronization PLL is implemented in a DSP
and the current control in an FPGA. In [32], the use of moving
average filters implemented in a DSP is proposed for har-
monic elimination in H-bridge cascaded STATic synchronous
COMPensators (STATCOMs). The use of FPGAs is restricted
in this case to the generation of 72 PWM signals, whereas fil-
tering stages could have also been easily implemented on them.
A scheme for balancing the series capacitor voltages in a three-
phase cascaded five-level inverter feeding an induction motor is
proposed in [55]. In this work, the control algorithm is executed
in a DSP and an FPGA is used to generate the 48 PWM sig-
nals required to act on the multilevel inverter. Similar solutions
in terms of DSP-FPGA task distribution is proposed in [56] for
the proportional resonant control of primary voltage-source rec-
tifiers in traction systems, in [57] for distributed control of a
three-stage solid-state transformer, in [33] for controlling mul-
tilevel modular matrix converters, or in [58] for predictive direct
torque control of PMSMs. In [59], some of the PWM signals for
controlling a two-level cascaded three-phase bridge inverter are
generated in a DSP, whereas the required delayed versions of
these are obtained with an FPGA. Aiming at achieving higher
sampling/switching frequencies in matrix converters, in [60], a
DSP is in charge of the PLL function, the control algorithm, and
the initial steps of the modulation strategy, whose remaining
steps are accelerated by means of their FPGA implementa-
tion. In [61], sensorless control of a PMSM is performed by
a DSP, and an FPGA is used as a coprocessor to accelerate
execution of a marginalized particle filter (a combination of
Kalman and particle filters) for estimating rotor position in the
full speed range. All these systems could be advantageously
implemented as FPSoCs, in some cases also benefitting from
the use of embedded ADCs or of embedded hardware arith-
metic blocks (to perform some of tasks currently executed in
DSPs, for instance for filtering purposes).
Hard real-time capabilities are a fundamental requirement in
many robotics applications, where control loops must exhibit
high operating frequency and low latency, while executing
high-complexity algorithms. DSPs, alone or combined with
FPGAs, have been extensively used in this area. However, their
inherent sequential processing results in high latency when exe-
cuting complex algorithms. Moreover, system scalability (to
include additional sensors or actuators) is very limited. In this
context, the use of current FPGAs allows better performance
and accuracy, as well as real-time or fault-tolerant operation,
to be achieved [62][64]. Fault tolerance is also a fundamental
requirement of those power systems that must guarantee con-
tinuous operation. In [65], an FPGA-based system is used for
both control and online fault detection in a power converter. In
the absence of faults, it operates as a conventional back-to-back
six-leg converter. If a fault is detected, the controller is recon-
figured for the converter to operate as five leg. The faster the
fault detection and reconfiguration, the safer the operation of
the system is. Faster operation could be achieved by replacing
the FPGA used in that work with a more current one including
advanced computation resources.
Modular robotics (e.g., for humanoid robots), where the
dynamics of each module are managed by a local embedded
controller, can increasingly take advantage of the capabilities
of current FPGA devices, as in [66], to achieve higher sampling
frequencies (and, in turn, better performance) than centralized
systems. The flexibility of FPSoC-based solutions adds to that
of these modular systems, allowing robot structure to be eas-
ily modified, extended, or repaired, even in the field. In this
context, the availability of FPGAs including two ARM pro-
cessors contributes to reduced size and weight, as well as
lower processor intercommunication latency. For instance, in
[67], the central processing node in a humanoid robot system
RODRGUEZ-ANDINA et al.: ADVANCED FEATURES AND INDUSTRIAL APPLICATIONS OF FPGAs
is implemented in a Zynq-7000 FPGA, which acts as global
hub for the remaining FPGA processing nodes, each one con-
nected to a set of sensors and actuators. In that work, one of
the ARM cores runs a real-time operating system and executes
time-critical tasks, whereas the other core runs a general pur-
pose operating system and is in charge of tasks for which longer
latencies are acceptable, such as the user interface.
The ability to perform floating-point operations is a funda-
mental requirement for improved performance in some appli-
cations, such as in [57], [68], and [69]. Because of the limited
amount of resources to perform floating-point operations avail-
able in the FPGA used, a nonstandard format (simpler than
IEEE 754) is implemented in [61], at the expense of accuracy
and dynamic range. As indicated in Section II-B, up to recently
resources for floating-point operation were scarcely available in
FPGAs. In current advanced FPSoCs, it is possible to imple-
ment such operations either in embedded or soft processors,
or in dedicated specialized hardware blocks. In [70], the use
of software-implemented floating point operations for identifi-
cation of the resonant tank impedance of domestic induction
heating systems is presented. Since impedance computation is
not a time-critical task in this case, a MicroBlaze soft processor
is used for this purpose. In [71], a linear generalized propor-
tional integral output feedback control scheme is proposed for
load current disturbance attenuation in a multilevel buck con-
verter system acting as an inverter. In [72], a real-time nonlinear
hysteretic power transformer model on FPGA is proposed. In
these two last works, pipeline architectures are implemented to
optimize system latency, and pure hardware floating-point oper-
ators (embedded multipliers and distributed logic in the first
case; basic DSP blocks in the second) are used to ensure a suit-
able dynamic range for signals. Better results could be achieved
by using the new IEEE 754-compatible DSP blocks.
The application of FPGAs in automotive systems is an area
of increasing interest. In [73], the use of an EKF for vehi-
cle velocity estimation is proposed. Since EKF requires matrix
multiplications and inversions to be computed in each iteration,
a high processing power is necessary to comply with the latency
requirements imposed by the antilock breaking system and the
electronic stability program. In this case, the EKF algorithm is
implemented in software, using a Nios II soft processor run-
ning at 100 MHz, and a custom hardware accelerator is used
for single-precision floating-point matrix operations. Also in
the automotive area, similar problems regarding the efficient
implementation of matrix operations are addressed in [74] for
the design of a predictive speed controller in dual-clutch trans-
mission gearshifts. Much better performance could be obtained
in both cases by using current devices, with more powerful
embedded processors and DSP blocks.
C. Electronic Instrumentation
The lack of embedded ADCs and DACs affected the features
and performance, as well as the complexity, of FPGA-based
industrial systems proposed in recent years, as in the afore-
mentioned [13], [57], or in [75]. Vector control of PMSMs is
addressed in [76], where frequency domain multiplexing is used
to reduce the number of required (external) ADCs. The ADCs
861
and DACs available in some current devices open the door
for the development of single-chip controllers. For instance, in
[16], the DACs included in the ACE block of a SmartFusion
device are used for the generation of the analog waveform of
the estimated angular position of the voltage vector. In this same
work, the embedded ARM core is used for the implementation
of the control algorithm. Using these advanced resources, the
performance of the resulting system is greatly improved.
The use of FPGAs in micro-electro-mechanical systems
(MEMs)-based gyroscopes is proposed in [77]. Common tasks
in this kind of applications require the use of ADCs and DACs,
as well as PLLs (for frequency tracking). In the aforementioned
work, all these elements are external to the FPGA, so perfor-
mance could be improved (and chip count reduced) by using the
embedded resources of these types available in current devices.
This is generally true for many instrumentation and measure-
ment circuits using FPGAs (like the ones proposed in [78] for
the characterization of inductive microsensors, in [79] for dc
leakage current sensors, in [80] for frequency measurement in
MEMs accelerometers, or in [81] and [82] for microgripper
control) as long as the resolution, sampling rate, etc. of the
embedded analog blocks are enough for the target applications.
On the other hand, vision algorithms can be very effi-
ciently implemented in FPGAs, which allow excellent per-
formance to be achieved in applications such as intelligent
spaces or unmanned ground or (micro) aerial vehicles (UGVs,
UAVs, or MAVs). Current intelligent space applications are
usually addressed by using multiple cameras, each of them
equipped with an associated distributed processing node [83].
In UAV/MAV applications, huge amounts of data must be pro-
cessed in real time with low latency, for instance for flight
control, real-time mapping, or obstacle avoidance purposes.
One such application where FPGAs are used as processing ele-
ments is described in [62]. Reduced size and weight are also
fundamental requirements of these aerial systems. The use of
FPSoCs allows chip (or board) count to be reduced, there-
fore contributing to the fulfillment of those requirements. For
instance, a hardware/software system to process depth images
and estimate ego-motion through the combination of visual
odometry and an inertial measurement unit (IMU) is presented
in [34]. The system consists of two cameras, an Intel Core2Duo
processor board, a Spartan 6 FPGA board, an ARM processor
board, and an IMU. Computation of depth images is carried out
in the FPGA, whereas all remaining functionalities are imple-
mented in software, nontime-critical ones in the Core2Duo and
time-critical ones in the ARM. Using one of the new FPGA
devices including ARM Cortex-A9 processors, the number of
required boards (and thus the size and weight of the system)
can be reduced. An additional advantage may be increased pro-
cessing speed, resulting in better accuracy. In [84], the use of a
Zynq-7000 FPGA is proposed for robust and accurate real-time
simultaneous localization and mapping (SLAM). The system
mainly consists of the FPSoC, four cameras, and an IMU. The
Zynq-7000 device replaces the combination of an FPGA and an
Intel ATOM processor used in previous prototypes. The hard-
ware part interfaces with the inertial and the image sensors
(however, resource usage for image processing is reported in
this paper for the Spartan 6 device used in the earlier prototype,
862 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015
which may explain why fixed-point versions of the algorithms
were used), whereas the ARM core running Linux is in charge
of processes such as the SLAM framework or host communi-
cation. A similar FPSoC including an embedded ARM Cortex
processor, from Altera in this case, is proposed in [85] to
perform stereo visual odometry for localization of low-cost
MAVs in global positioning system (GPS)-denied environ-
ments. The system includes two cameras and an IMU. While
most of the tasks are implemented in the hardware part, the
used platform would allow the extension of the functionality to
include complex high-level tasks executed in the ARM proces-
sor. This is also the case of the work presented in [86], where a
configurable hardware system for traffic sign recognition is pro-
posed, achieving 60 frames per second with 1280 720 pixel
images.
Improved control performance in industrial laser cladding
processes has been demonstrated to be achieved by the sys-
tem presented in [87]. This work proposes an adaptive fuzzy
PI controller that works with data extracted from a real-time
image-processing system (achieving 100-Hz sampling rate for
800 600 -pixel images). The whole monitoring and control
system is implemented in an FPGA, combining a Nios II soft
processor with high-performance custom hardware peripherals.
Since the board used does not include a DAC, the analog sig-
nal required to adjust the power of the laser bean is obtained
by applying a PWM signal to an external low-pass filter. This
could be simplified by using a device with an embedded DAC.
In a similar application domain, the computer-based image
processing part of the system proposed in [88] for monitor-
ing a laser-welding process could be simplified by using an
FPGA-based system.
V. C ONCLUSION
New features are continuously being added by FPGA ven-
dors to their devices, targeting ever wider application domains.
Some of them are advanced extensions or improvements to
previously available resources (e.g., embedded and soft proces-
sors), whereas others are new ones aimed at mitigating tradi-
tional limitations (e.g., related to interfacing with the analog
world or to the ability to efficiently perform floating-point oper-
ations) or at improving performance (e.g., regarding memory
controllers).
These new features, as well as recent advancements in soft-
ware resourcesIP cores and design toolsare reviewed in the
first part of this paper. The second part is devoted to analyze the
impact of new features in current industrial application domains
where FPGAs are already being used. From this analysis, it can
be clearly concluded that, although many industrial applications
could greatly benefit from them, they are very scarcely used
by designers. For instance, the use of the new FPGA+ARM
architectures is reported in very few works.
In the authors opinion, there are two main reasons for
this. On one hand, the characteristics of these architectures
require from designers good knowledge and expertise in both
the hardware and software domains, as well as in the effi-
cient integration of both sides, and the partitioning of tasks
between them. The development of new design tools in this
area would definitely boost acceptance of the new devices
among designers, with the corresponding benefit for the result-
ing systems. On the other hand, industrial electronics designers
are often (and understandably) mainly focused on the details
of their specific applications, rather than in the implementation
platforms, so they tend to keep using the same digital devices.
In this sense, this paper can motivate them to evaluate the ben-
efits of upgrading their systems by taking advantage of the new
FPSoC architectures.
R EFERENCES
[1] W. A. Najjar and P. Ienne, Reconfigurable computing, IEEE Micro,
vol. 34, no. 1, pp. 46, Jan./Feb. 2014.
[2] J. J. Rodrguez-Andina, M. J. Moure, and M. D. Valds, Features, design
tools, and application domains of FPGAs, IEEE Trans. Ind. Electron.,
vol. 54, no. 4, pp. 18101823, Aug. 2007.
[3] E. Monmasson and M. N. Cirstea, FPGA design methodology for indus-
trial control systemsA review, IEEE Trans. Ind. Electron., vol. 54, no. 4,
pp. 18241842, Aug. 2007.
[4] M.-W. Naouar, E. Monmasson, A. A. Naassani, I. Slama-Belkhodja, and
N. Patin, FPGA-based current controllers for AC machine drivesA
review, IEEE Trans. Ind. Electron., vol. 54, no. 4, pp. 19071925, Aug.
2007.
[5] E. Monmasson, L. Idkhajine, and M. W. Naouar, FPGA-based con-
trollers, IEEE Ind. Electron. Mag., vol. 5, no. 1, pp. 1426, Mar.
2011.
[6] E. Monmasson et al., FPGAs in industrial control applications, IEEE
Trans. Ind. Informat., vol. 7, no. 2, pp. 224243, May 2011.
[7] E. Monmasson and M. Cirstea, Guest editorial special section on indus-
trial control applications of FPGAs, IEEE Trans. Ind. Informat., vol. 9,
no. 3, pp. 12501252, Aug. 2013.
[8] L. Gomes and J. J. Rodrguez-Andina, Guest editorial special section
on embedded and reconfigurable systems, IEEE Trans. Ind. Informat.,
vol. 9, no. 3, pp. 15881590, Aug. 2013.
[9] L. Gomes, E. Monmasson, M. Cirstea, and J. J. Rodrguez-Andina,
Industrial electronic control: FPGAs and embedded systems solutions,
in Proc. 39th Annu. Conf. IEEE Ind. Electron. Soc. (IECON13), 2013,
pp. 6065.
[10] M. Henrey, S. Edmond, L. Shannon, and C. Menon, Bio-inspired walk-
ing: A FPGA multicore system for a legged robot, in Proc. 22nd Int.
Conf. Field Programm. Logic Appl. (FPL12), 2012, pp. 105111.
[11] Altera Corporation. (2015). Arria 10 Core Fabric and General Purpose
I/Os Handbook [Online]. Available: https://www.altera.com/en_US/pdfs/
literature/hb/arria-10/a10_handbook.pdf
[12] D. Vila, M. Pozo, M. Pacas, and J. J. Rodrguez-Andina, FPGA-
based communication module for control of power inverters and
drives, in Proc. IEEE 15th Workshop Control Model. Power Electron.
(COMPEL14), 2014, pp. 16.
[13] F. Adler, A. Benigni, H. Stagge, A. Monti, and R. W. De Doncker, A new
versatile hardware platform for digital real-time simulation: Verification
and evaluation, in Proc. IEEE 13th Workshop Control Model. Power
Electron. (COMPEL12), 2012, pp. 18.
[14] [Online]. Available: http://www.xilinx.com/products/technology/analog-
mixed-signal/modals/motor-control.html
[15] [Online]. Available: http://www.microsemi.com/products/fpga-soc/soc-
fpga/smartfusion#ds
[16] M. Ben Sad et al., Full System on Programmable Chip solution for DPC
control of three phase PWM boost rectifier, in Proc. 38th Annu. Conf.
IEEE Ind. Electron. Soc. (IECON12), 2012, pp. 30673072.
[17] Microsemi Corporation. (2015). SmartFusion2 System-
on-Chip FPGAs Product Brief [Online]. Available:
http://www.microsemi.com/products/fpga-soc/soc-fpga/sf2docs#ds
[18] [Online]. Available: https://www.altera.com/products/soc/portfolio/arria-
10-soc/arria10-soc-hps.html
[19] M. Al Kadi, P. Rudolph, D. Ghringer, and M. Hbner, Dynamic and
partial reconfiguration of Zynq 7000 under Linux, in Proc. Int. Conf.
Reconfig. Comput. FPGAs (ReConFig13), 2013, pp. 15.
[20] M. Ashwin and U. Madhava Rao, Performance evaluation of fuzzy
logic speed controller for permanent magnet synchronous motor drives
on a SoC platform, in Proc. 39th Annu. Conf. IEEE Ind. Electron. Soc.
(IECON13), 2013, pp. 30423047.
RODRGUEZ-ANDINA et al.: ADVANCED FEATURES AND INDUSTRIAL APPLICATIONS OF FPGAs
[21] [Online]. Available: http://wl.altera.com/technology/memory/controller/
hard-memory/mem-controllers.html
[22] T. Kryjak and M. Gorgon, Real-time implementation of the ViBe fore-
ground object segmentation algorithm, in Proc. Fed. Conf. Comput. Sci.
Inf. Syst. (FedCSIS13), 2013, pp. 591596.
[23] O. Buchholz and J. Boecker, FPGA-based dynamically reconfigurable
control of induction motor drives, in Proc. 39th Annu. Conf. IEEE Ind.
Electron. Soc. (IECON13), 2013, pp. 35433548.
[24] Z. Or-Bach. (2014). FPGAs as ASIC Alternatives: Past and Future
[Online]. Available: http://www.eetimes.com/author.asp?doc_id=1322021
[25] [Online]. Available: http://www.marketsandmarkets.com/Market-Re-
ports/semiconductor-silicon-intellectual-property-ip-market-651.html
[26] [Online]. Available: http://blogs.mentor.com/verificationhorizons/blog/
2015/02/08/ part-1-the-2014-wilson-research-group-functional-verifica-
tion-study/
[27] J. Joven et al., HW-SW implementation of a decoupled FPU for ARM-
based Cortex-M1 SoCs in FPGAs, in Proc. 6th IEEE Int. Symp. Ind.
Embedded Syst. (SIES11), 2011, pp. 18.
[28] S. Gao and J. Chritz, Characterization of OpenCL on a scalable
FPGA architecture, in Proc. Int. Conf. Reconfig. Comput. FPGAs
(ReConFig14), 2014, pp. 16.
[29] A. Hasanzadeh, C. S. Edrington, N. Stroupe, and T. Bevis, Real-time
emulation of a high-speed microturbine permanent-magnet synchronous
generator using multiplatform hardware-in-the-loop realization, IEEE
Trans. Ind. Electron., vol. 61, no. 6, pp. 31093118, Jun. 2014.
[30] F. Senicar, M. Dopker, A. Bartsch, B. Kruger, and S. Soter, Inverter
based method for measurement of PMSM machine parameters based on
the elimination of power stage characteristics, in Proc. 40th Annu. Conf.
IEEE Ind. Electron. Soc. (IECON14), 2014, pp. 702708.
[31] H. Wen, D. Cheng, Z. Teng, S. Guo, and F. Li, Approximate algorithm
for fast calculating voltage unbalance factor of three-phase power sys-
tem, IEEE Trans. Ind. Informat., vol. 10, no. 3, pp. 17991805, Aug.
2014.
[32] Y. Wang, K. Yang, C. He, and G. Chen, A harmonic elimination
approach based on moving average filter for cascaded DSTATCOM,
in Proc. 40th Annu. Conf. IEEE Ind. Electron. Soc. (IECON14), 2014,
pp. 45084513.
[33] Y. Miura, K. Inubushi, M. Ito, and T. Ise, Multilevel modular matrix
converter for high voltage applications. Control, design and experimen-
tal characteristics, in Proc. 40th Annu. Conf. IEEE Ind. Electron. Soc.
(IECON14), 2014, pp. 46904696.
[34] K. Schmid and H. Hirschmller, Stereo vision and IMU based real-time
ego-motion and depth image computation on a handheld device, in Proc.
IEEE Int. Conf. Robot. Autom. (ICRA13), 2013, pp. 46714678.
[35] V. Lunati, J. Manhes, and P. Danes, A versatile System-on-a-
Programmable-Chip for array processing and binaural robot audition,
in Proc. IEEE/RSJ Int. Conf. Intell. Robots. Syst. (IROS12), 2012,
pp. 9981003.
[36] C. Buccella, C. Cecati, and H. Latafat, Digital control of power convert-
ers A survey, IEEE Trans. Ind. Informat., vol. 8, no. 3, pp. 437447,
Aug. 2012.
[37] Z. Zhu, X. Li, H. Rao, W. Wang, and W. Li, Testing a complete con-
trol and protection system for multi-terminal MMC HVDC links using
hardware-in-the-loop simulation, in Proc. 40th Annu. Conf. IEEE Ind.
Electron. Soc. (IECON14), 2014, pp. 44024408.
[38] A. Schmitt, J. Richter, U. Jurkewitz, and M. Braun, FPGA-based
real-time simulation of nonlinear permanent magnet synchronous
machines for power hardware-in-the-loop emulation systems, in Proc.
40th Annu. Conf. IEEE Ind. Electron. Soc. (IECON14), 2014,
pp. 37633769.
[39] C. Wang, W. Li, and J. Blanger, Real-time and faster-than-real-time
simulation of modular multilevel converters using standard multi-core
CPU and FPGA chips, in Proc. 39th Annu. Conf. IEEE Ind. Electron.
Soc. (IECON13), 2013, pp. 54055411.
[40] W. Wang, Z. Shen, and V. Dinavahi, Physics-based device-level power
electronic circuit hardware emulation on FPGA, IEEE Trans. Ind.
Informat., vol. 10, no. 4, pp. 21662179, Nov. 2014.
[41] . Jimnez et al., Implementation of an FPGA-based on-line hardware-
in-the-loop emulator using high-level synthesis tools for resonant power
converters applied to induction heating appliances, IEEE Trans. Ind.
Electron., vol. 62, no. 4, pp. 22062214, Apr. 2015.
[42] M. Dagbagi et al., FPGA-based real-time hardware-in-the-loop valida-
tion of a 3-phase PWM rectifier controller, in Proc. 39th Annu. Conf.
IEEE Ind. Electron. Soc. (IECON13), 2013, pp. 53745379.
[43] S. Usenmez et al., A new hardware-in-the-loop simulator for CNC
machine applications, in Proc. IEEE Int. Conf. Mechatron. (ICM13),
2013, pp. 658663.
863
[44] N. R. Tavana and V. Dinavahi, A general framework for FPGA-
based real-time emulation of electrical machines for HIL applica-
tions, IEEE Trans. Ind. Electron., vol. 62, no. 4, pp. 20412053, Apr.
2015.
[45] O. Goi, A. Snchez, E. Todorovich, and . de Castro, Resolution analy-
sis of switching converter models for hardware-in-the-loop, IEEE Trans.
Ind. Informat., vol. 10, no. 2, pp. 11621170, May 2014.
[46] D. Majstorovic, I. Celanovic, N. D. Teslic, N. Celanovic, and V. A. Katic,
Ultralow-latency hardware-in-the-loop platform for rapid validation of
power electronics designs, IEEE Trans. Ind. Electron., vol. 58, no. 10,
pp. 47084716, Oct. 2011.
[47] Z. R. Ivanovic et al., HIL evaluation of power flow control strategies
for energy storage connected to smart grid under unbalanced condi-
tions, IEEE Trans. Power Electron., vol. 27, no. 11, pp. 46994710, Nov.
2012.
[48] C. Dufour, S. Cense, T. Ould-Bachir, L.-A. Grgoire, and J. Blanger,
General-purpose reconfigurable low-latency electric circuit and motor
drive solver on FPGA, in Proc. 38th Annu. Conf. IEEE Ind. Electron.
Soc. (IECON12), 2012, pp. 30733081.
[49] S. Buso and T. Caldognetto, A non-linear wide bandwidth digital current
controller for DC-DC and DC-AC converters, in Proc. 40th Annu. Conf.
IEEE Ind. Electron. Soc. (IECON14), 2014, pp. 10901096.
[50] H. Youness, M. Moness, and M. Khaled, MPSoCs and multicore micro-
controllers for embedded PID control: A detailed study, IEEE Trans. Ind.
Informat., vol. 10, no. 4, pp. 21222134, Nov. 2014.
[51] M. C. Di Piazza, M. Luna, and G. Vitale, Design and FPGA implemen-
tation of an all-digital two-quadrant general pulse-width modulator, in
Proc. Int. Symp. Ind. Electron. (ISIE14), 2014, pp. 13281335.
[52] I. Bahri, L. Idkhajine, E. Monmasson, and M. El Amine Benkhelifa,
Hardware/software codesign guidelines for System on Chip FPGA-
based sensorless AC drive applications, IEEE Trans. Ind. Informat.,
vol. 9, no. 4, pp. 21652176, Nov. 2013.
[53] N. Otero, H. Rahimi-Eichi, J. J. Rodrguez-Andina, and M.-Y. Chow,
FPGA implementation of an observer for state of charge estimation
in lithium-polymer batteries, in Proc. Int. Conf. Mechatron. Control
(ICMC14), 2014, pp. 16461651.
[54] V. A. Prabhala, M. Cspedes, and J. Sun, Implementation of DQ domain
control in DSP and FPGA, in Proc. 27th Annu. IEEE Appl. Power
Electron. Conf. Expo. (APEC12), 2012, pp. 14391444.
[55] T. W. Chun, Q. V. Tran, H. H. Lee, H. G. Kim, and E. C. Nho, A simple
capacitor voltage balancing scheme for the cascaded five-level inverter
fed AC machine drive, in Proc. 6th IET Int. Conf. Power Electron. Mach.
Drives (PEMD12), pp. 15, 2012.
[56] D. Janik, Z. Peroutka, J. Molnar, T. Komrska, and J. Zak, Control
of primary voltage-source active rectifiers of traction converter with
medium-frequency transformer: Advantages of control unit combining
DSP and FPGA, in Proc. 15th Int. Power Electron. Motion Control Conf.
(EPE/PEMC12), 2012, pp. LS4a.2-1LS4a.2-7.
[57] S.-H. Hwang, X. Liu, J.-M. Kim, and H. Li, Distributed digital control of
modular-based solid-state transformer using DSP+FPGA, IEEE Trans.
Ind. Electron., vol. 60, no. 2, pp. 670680, Feb. 2013.
[58] R. Morales-Caporal, E. Bonilla-Huerta, C. Hernndez, M. A. Arjona, and
M. Pacas, Transducerless acquisition of the rotor position for predictive
torque controlled PM synchronous machines based on a DSP-FPGA dig-
ital system, IEEE Trans. Ind. Informat., vol. 9, no. 2, pp. 799807, May
2013.
[59] Z.-G. Lu, L.-L. Zhao, W.-P. Zhu, C.-J. Wu, and Y.-S. Qin, Research on
cascaded three-phase-bridge multilevel converter based on CPS-PWM,
IET Power Electron., vol. 6, no. 6, pp. 10881099, Jul. 2013.
[60] K. Kobravi, R. Iravani, and H. A. Kojori, Three-leg/four-leg matrix
converter generalized modulation strategyPart II: Implementation and
verification, IEEE Trans. Ind. Electron., vol. 60, no. 3, pp. 860872, Mar.
2013.
[61] V. Smidl, R. Nevdev, T. Kosan, and Z. Peroutka, FPGA implementation
of marginalized particle filter for sensorless control of PMSM drives,
in Proc. 39th Annu. Conf. IEEE Ind. Electron. Soc. (IECON13), 2013,
pp. 82278232.
[62] K. May and N. K. Krougjicof, Moving target detection for sense and
avoid using regional phase correlation, in Proc. IEEE Int. Conf. Robot.
Autom. (ICRA13), 2013, pp. 47674772.
[63] T. T. Phuong, K. Ohishi, Y. Yokokura, and C. Mitsantisuk, FPGA-based
high-performance force control system with friction-free and noise-free
force observation, IEEE Trans. Ind. Electron., vol. 61, no. 2, pp. 994
1008, Feb. 2014.
[64] A. Hace and M. Franc, FPGA implementation of sliding-mode-control
algorithm for scaled bilateral teleoperation, IEEE Trans. Ind. Informat.,
vol. 9, no. 3, pp. 12911300, Aug. 2013.
864
[65] M. Shahbazi, P. Poure, S. Saadate, and M. R. Zolghadri, FPGA-based
reconfigurable control for fault-tolerant back-to-back converter without
redundancy, IEEE Trans. Ind. Electron., vol. 60, no. 8, pp. 33603371,
Aug. 2013.
[66] W. Zhu et al., Precision control of modular robot manipulators: The
VDC approach with embedded FPGA, IEEE Trans. Robot., vol. 29,
no. 5, pp. 11621179, Oct. 2013.
[67] B. Pierce and G. Cheng, Versatile modular electronics for rapid design
and development of humanoid robotic subsystems, in Proc. IEEE/ASME
Int. Conf. Adv. Intell. Mechatron. (AIM14), 2014, pp. 735741.
[68] C. A. Seplveda, J. A. Muoz, J. R. Espinoza, M. E. Figueroa, and
C. R. Baier, FPGA v/s DSP performance comparison for a VSC-based
STATCOM control application, IEEE Trans. Ind. Informat., vol. 9, no. 3,
pp. 13511360, Aug. 2013.
[69] F. Barranco, J. Daz, B. Pino, and E. Ros, Real-time visual saliency
architecture for FPGA with top-down attention modulation, IEEE Trans.
Ind. Informat., vol. 10, no. 3, pp. 17261735, Aug. 2014.
[70] . Jimnez, . Luca, I. Urriza, L. A. Barragn, and D. Navarro,
Analysis and implementation of FPGA-based online parametric iden-
tification algorithms for resonant power converters, IEEE Trans. Ind.
Informat., vol. 10, no. 2, pp. 11441153, May 2014.
[71] J. A. Jurez-Abad, J. Linares-Flores, E. Guzmn-Ramrez, and H. Sira-
Ramrez, Generalized proportional integral tracking controller for a
single-phase multilevel cascade inverter: An FPGA implementation,
IEEE Trans. Ind. Informat., vol. 10, no. 1, pp. 256266, Feb. 2014.
[72] J. Liu and V. Dinavahi, A real-time nonlinear hysteretic power trans-
former transient model on FPGA, IEEE Trans. Ind. Electron., vol. 61,
no. 7, pp. 35873597, Jul. 2014.
[73] H. Guo, H. Chen, F. Xu, F. Wang, and G. Lu, Implementation of EKF
for vehicle velocities estimation on FPGA, IEEE Trans. Ind. Electron.,
vol. 60, no. 9, pp. 38233835, Sept. 2013.
[74] X. Lu, H. Chen, B. Gao, Z. Zhang, and W. Jin, Data-driven predictive
gearshift control for dual-clutch transmissions and FPGA implemen-
tation, IEEE Trans. Ind. Electron., vol. 62, no. 1, pp. 599610, Jan.
2015.
[75] J. Guzinski and H. Abu-Rub, Speed sensorless induction motor drive
with predictive current controller, IEEE Trans. Ind. Electron., vol. 60,
no. 2, pp. 699709, Feb. 2013.
[76] R. Cordero, W. I. Suemitsu, J. O. P. Pinto, A. M. Soares, and
R. A. Capitanio, Application of frequency domain multiplexing for the
reduction of ADCs in vector control of PMSM, in Proc. 38th Annu. Conf.
IEEE Ind. Electron. Soc. (IECON12), 2012, pp. 16901695.
[77] X. Wang, H. Li, B. Yang, L. Huang, and S. Wang, A prototype of MEMs
gyroscope based on digital control, in Proc. Int. Conf. Autom. Control
Artif. Intell. (ACAI2012), 2012, pp. 275278.
[78] P. Kchert, J. Flgge, D. Miletic, and H. H. Gatzen, Investigation of an
advanced micro-inductive sensor, in Proc. IEEE Sensors, 2012, pp. 14.
[79] C.-F. Cheng, R.-S. Li, and J.-R. Chen, Design of the DC leakage cur-
rent sensor with magnetic modulation-based scheme, in Proc. IEEE Int.
Symp. Ind. Electron. (ISIE13), 2013, pp. 16.
[80] G.-M. Xia, A.-P. Qiu, Q. Shi, and S. Yan, Test and evaluation of a silicon
resonant accelerometer implemented in SOI technology, in Proc. IEEE
Sensors, 2013, pp. 14.
[81] Q. Xu, Design and smooth position/force switching control of a minia-
ture gripper for automated microhandling, IEEE Trans. Ind. Informat.,
vol. 10, no. 2, pp. 10231032, May 2014.
[82] Q. Xu, Robust impedance control of a compliant microgripper for high-
speed position/force regulation, IEEE Trans. Ind. Electron., vol. 62,
no. 2, pp. 12011209, Feb. 2015.
[83] J. Rodrguez-Arajo, J. J. Rodrguez-Andina, J. Faria, and M.-Y. Chow,
Field-programmable System-on-Chip for localization of UGVs in an
indoor iSpace, IEEE Trans. Ind. Informat., vol. 10, no. 2, pp. 10331043,
May 2014.
[84] J. Nikolic et al., A synchronized visual-inertial sensor system with
FPGA pre-processing for accurate real-time SLAM, in Proc. IEEE Int.
Conf. Robot. Autom. (ICRA13), 2014, pp. 431437.
[85] G. Zhou, J. Ye, W. Ren, T. Wang, and Z. Li, On-board inertial-assisted
visual odometer on an embedded system, in Proc. IEEE Int. Conf. Robot.
Autom. (ICRA13), 2014, pp. 26022608.
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 11, NO. 4, AUGUST 2015
[86] N. Aguirre-Dobernack, H. Guzmn-Miranda, and M. A. Aguirre,
Implementation of a machine vision system for real-time traffic sign
recognition on FPGA, in Proc. 39th Annu. Conf. IEEE Ind. Electron.
Soc. (IECON13), 2013, pp. 22852290.
[87] J. Rodrguez-Arajo et al., Industrial laser cladding systems: FPGA-
based adaptive control, IEEE Ind. Electron. Mag., vol. 6, no. 4,
pp. 3546, Dec. 2012.
[88] D. You, X. Gao, and S. Katayama, Multisensor fusion system for mon-
itoring high-power disk laser welding using support vector machine,
IEEE Trans. Ind. Informat., vol. 10, no. 2, pp. 12851295, May 2014.
Juan J. Rodrguez-Andina (M00SM04) received
the M.Sc. degree from the Technical University of
Madrid, Madrid, Spain, in 1990, and the Ph.D. degree
from the University of Vigo, Vigo, Spain, in 1996,
both in electrical engineering.
He is an Associate Professor with the Department
of Electronic Technology, University of Vigo. From
2010 to 2011, he was on sabbatical leave as
a Visiting Professor at the Advanced Diagnosis,
Automation, and Control Laboratory, Electrical and
Computer Engineering Department, North Carolina
State University, Raleigh, NC, USA. He has authored over 130 journal and
conference articles, and holds several Spanish, European, and U.S. patents.
His research interests include implementation of complex control and process-
ing algorithms in field programmable gate arrays, and concurrent testing of
complex systems, from digital to industrial electronics.
Dr. Rodrguez-Andina is currently serving as the Editor-in-Chief for the
IEEE I NDUSTRIAL E LECTRONICS M AGAZINE, and as an Associate Editor
for the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS and the IEEE
T RANSACTIONS ON I NDUSTRIAL I NFORMATICS .
Mara D. Valds-Pea (M05) received the M.Sc.
degree from the Universidad Central de Las Villas,
Santa Clara, Cuba, in 1990, and the Ph.D. degree
from the University of Vigo, Vigo, Spain, in 1997,
both in electrical engineering.
She is an Associate Professor with the Department
of Electronic Technology, University of Vigo. Her
research interests include the design of system-on-
chip systems based on field programmable gate
arrays, signal acquisition and conditioning, signal
processing, and wireless sensors networks for indus-
trial applications.
Mara J. Moure (M99) received the Ph.D. degree
in electrical engineering from the University of Vigo,
Vigo, Spain, in 1999.
She is an Associate Professor with the Department
of Electronic Technology, University of Vigo. Her
research interests include the design of system-on-
chip systems based on field programmable gate
arrays, signal acquisition and conditioning, signal
processing, and wireless sensors networks for indus-
trial applications.