2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
MACRON: The NoC-based Many-Core Parallel Processing Platform and its
Applications in 4G Communication Systems
Xiang Ling, Yiou Chen, Zhiliang Yu, Shihua Chen, Xiaodong Wang, Gui Liang
National Key Laboratory of Science and Technology on Communications
University of Electronic Science and Technology of China
Chengdu, China
{xiangling, chenyiou}@uestc.edu.cn
AbstractThe increasing demand of computation capacity
has made many-core parallel processing (MPP) a compelling
choice for computation-intensive applications. The networks-on-
chip (NoC) architecture is an effective way to interconnect dozens
of processing cores, while the logic circuits and the actual
performance need to be verified in specific platform. We
proposed and implemented the MACRON platform to provide
verification for complicated applications based on NoC
architecture by coordinating the software tool and the hardware
devices closely. In MACRON, the virtual output queue with look-
ahead routing is proposed to reduce the transmission delay
through the NoC router. The heterogeneous processing elements:
vector processor core, scalar processor core and accelerator core
are designed, thus a thorough soft signal processing can be
approached. A real-time 4G wireless communication system
based on NoC is demonstrated on this MACRON platform.
Keywordsnetworks-on-chip; many-core architecture; FPGA;
digital signal process; wireless communications; vector processor
I. INTRODUCTION
Along with the development in decades of years, the
wireless communication systems has evolved from the 2nd
Generation (e,g. GSM) to the 3rd Generation (e.g. CDMA,
WiMax), and to the 4th Generation (e.g. LTE) in recent years.
Meanwhile the techniques of the 5th Generation have already
been put on the agenda [1]. This evolution has led to the
coexistence of a variety of communication standards, and
multi-modes operation will become an important trend in the
global wireless communications market. In this case, the
traditional way that radio defined by hardware cannot satisfy
the demand any more. Thus the so-called software defined
radio (SDR) emerges, in which the signal processing is mostly
implemented by software, so the signal processing requires
more powerful computing abilities. The traditional uni-
processor, or even the multi-processors with a few processing
cores, cannot meet the demand of massive computing. In
addition, since it is difficult to keep shortening the feature size
of semiconductor continuously, it becomes more difficult to
achieve higher computing performance by accelerating clock
speed. As a result, multi-processor parallel processing, which
makes use of several processors to process data concurrently,
becomes an inevitable trend in future. This method can greatly
boost the computing performance. Particularly, the
heterogeneous multi-processors can cooperate to fulfill
different types of tasks [2]. In general, multi-core is named if
several up to more than a dozen cores are organized, which is
1066-6192/15 $31.00 2015 IEEE
DOI 10.1109/PDP.2015.86
often connected by bus. If dozens or even hundreds cores are
grouped together, we call it many-core. The many-core
parallel processing (MPP) architecture is a prominent solution
for heavy load computation in digital signal processing (DSP)
[3,4]. In MPP architecture, the traditional bus-based
interconnection shows the shortcoming of low bandwidth.
Assume one processor obtains the bus token; other dozens of
cores are excluded from bus usage, which leads to the inter-
core communication to be the bottleneck of the many-core
scenario. Therefore how to organize, connect and schedule a
large number of processing cores to meet the computation
requirements is an urgent problem in digital signal processing
of wireless communications.
Since the beginning of this century, several research
groups proposed new integrated circuit architecture, called
network-on-chip (NoC), which applies computer network
techniques into chip design and thoroughly solves the problem
in the traditional bus-based SoC architecture [5]. NoC makes
full use of the communication mode in the distributed
computer networks; the bus-based operation is replaced by
routing and packet switching techniques. NoC provides a new
design methodology and will become a promising prospect in
MPP applications.
In this paper, we propose a NoC based architecture for the
MPP platform, called MACRON (MAny-Core paRallel On
Noc). The main novelties of MACRON are: (1) combine a
large number of processor-cores with the NoC architecture to
provide flexible solutions; (2) integrate the hardware platform
with the software tool to verify the signal processing
applications. The rest of the paper is organized as follows.
Section II reviews some related works. Section III discusses
the hardware architecture and its critical circuits. Section IV
introduces the software tool. Section V describes the
processing elements for parallel processing. Section VI
provides some numerical analysis. Section VII verifies the
NoC-based MPP platform with a 4G Long Term Evolution
(LTE) wireless communication system. Finally, Section VIII
concludes the paper.
II. RELEATED WORKS
With the success of MPP technique in high performance
computers, the idea of MPP is also adopted in microprocessor
design. PC20x from Picochip, Tile64 from Tilera and Fermi
from NVIDIA are some typical commercial chips integrated
dozens of processing units.
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 The combination of many-core architecture and NoC
infrastructure has been proposed and studied recently. In [6],
the topology virtualization techniques are proposed for NoC-
based many-core processors with core-level redundancy to
isolate hardware changes caused by on-chip defective cores. In
[7], the problem of how to tolerate run-time core failures on
homogeneous many-core platform through system
reconfigurations for real-time embedded applications is
discussed. Zhang et al. [8] addresses the fault tolerance in
NoC and presents an on-the-field test and configuration
infrastructure for a 2D-mesh NoC, which can be used in many
generic shared-memory many-core tiled architectures and
MPSoCs. Ebrahimi et al. [9] tried to maintain the performance
of NoC in the presence of faults by taking advantage of a fully
adaptive routing algorithm using one and two virtual channels
along the X and Y dimensions. Kumar and Lipari [10]
provided an approach to analyze the communication latency
on NoC with wormhole switching and credit-based virtual
channel flow control.
Some hardware platforms are designed and implemented
to verify the algorithms and circuits in NoC architecture, in
which Field Programmable Gate Array (FPGA) are widely
used to prototype or emulate the NoC circuits and
performance [11,12]. Wang et al. [13] introduced a fast and
flexible FPGA-based NoC simulation architecture, which
virtualizes the NoC by mapping its components to a generic
NoC simulation engine and is composed of a fully connected
collection of fundamental components. Mohamed and Vaughn
[14] verified the interconnection, area and power consumption
of NoC solutions on FPGAs.
Besides the existed platforms, our MACRON platform co-
ordinates the software tools and hardware devices closely to
provide verification for complicated applications based on
NoC architecture. The virtual output queue (VOQ) with look-
ahead routing is proposed to reduce the transmission delay
through the NoC router. The processing elements (PE) in
MACRON can be homogeneous or heterogeneous. Vector
processor core, scalar processor core and accelerator core are
designed, thus a thorough soft signal processing can be
executed. And a complicated real-time 4G wireless
communication system is demonstrated on this MACRON
platform.
III. MACRON HARDWARE IMPLEMENTATION
A. FPGA Array
MACRON hardware platform is composed of the
baseband board and the radio frequency (RF) board. The
baseband board consists of four XC7K325T FPGA chips and
one CPU chip, shown in Fig.1. The processing cores we
designed are placed on the four FPGAs to take charge of
baseband signal processing; and the CPU is responsible for
handling high-level protocol stacks. There are three kinds of
interconnections among these FPGAs listed as follows: (i)
4.9Gbps high-speed serial giga-bit transceiver (GTX) channels
among FPGAs; (ii) a sRIO switch CPS1432 provides 10Gbps
sRIO channel connecting to each FPGA; (iii) a GE (gigabit
Ethernet) switch BCM5396 is placed to connect every FPGA
and provide 1Gbps GE ports. Abundant interconnection
guarantees a fast data switch capability, which can satisfy the
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Fig. 1. The interconnection among FPGAs, front panel and backplane. (For
concision, partial GTX channels between FPGAs on the diagonal are not
shown.)
demand of a large amount of data transmission among
processing cores. Moreover, several high speed ports are
expanded to the front panel and the backplane, by which two
or more baseband boards can be cascaded to form a larger
scale of FPGA array. The NoC architecture and the many-core
parallel processing will be implemented in this FPGA array.
B. NoC Architecture
The NoC architecture mainly consists of processing
elements (PE), network interfaces (NI), routers and links.
Routers are connected by links to form specific topologies.
The function of NI is to accomplish data transfer between the
router and the PE, thus data packets can be transmitted and
received by PEs. After a PE finishes its own task, it sends the
generated data in packets to the next PE for the subsequent
processing. So the router connected to the local PE via NI
stores the data packets in the buffer and then triggers the
forward procedure. During the forward procedure, the router
determines the routing direction, allocates the queuing
resource and switches the data to the output port. Then the
data packets will be sent to next router and the same routing
procedure will be repeated until they reach the target PE.
C. Switch and Queuing
(i) Switch architecture
Aiming at solving the head-of-line (HOL) blocking
problem [7] in the router design, we take advantage of the idea
of virtual output queue (VOQ) [15], and propose a router
architecture in which the HOL blocking problem is addressed
and the processing delay is minimized. As shown in Fig.2,
there are four VOQ queues located at each input port
corresponding to different output ports in four directions.
VOQ(i,j) stores the flit from input port i to output port j. Note
that i j , because the data packet from a port wont be sent
back to the same port. When a flit arrives at the input queue,
the queue requests for a corresponding output port; and the
switch allocator (SA) of each output port arbitrates all the
requests received. If one request is approved, the flit in this
input queue will be sent out immediately. Compared with the
virtual channel (VC) switching, processing delay of VOQ is
decreased, because no virtual channel allocation is needed.

Fig. 2. The infrastructure of VOQ router.
(a) Packets request for the same output port in the next router
(b) Packets request for the different output ports in the next router
Fig. 3. The packets transmission between VOQ routers. (The output ports in
the current router and in the next router are considered jointly during
arbitration. H: Head Flit, B: Body Flit, T: Tail Flit)
Meanwhile the HOL problem is resolved because the data
packets arriving at each input port for different output port
will be assigned to different queues naturally.
When VOQ is applied with wormhole routing, the flits in
the same packet will move consecutively in order to improve
the utilization of storage resources, shown in Fig.3(a). In our
design, look-ahead route calculation is adopted, where the
output ports in the current router and the next router are
considered jointly. More details will be discussed in the
subsequent sections. When flits in different VOQs request for
the same output port in the current router and different output
ports in the next router, the flits are sent to the next router by
polling, shown in Fig.3(b).
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Fig. 4. The infrastructure of the switch allocator (SA).
(ii) Look-ahead Routing
In order to reduce the delay for a packet goes through the
router, the look-ahead routing is designed in our VOQ
architecture to decrease the progressing stages compared with
the VC architecture. In the VC switching structure, the route
decision unit of the present router determines the output port
(East, South, West, North or PE). Suppose the source and the
destination of the data transmission are node 31 (in row 3 and
column 1) and node36 (in row 3 and column 6). In the VC
switching structure, when the head flit arrives at node 33, its
route decision unit calculates the output port (which is East in
this case) and sends it to node 34. However in the VOQ
switching structure, the queue VOQ(i,j) of each input port i is
fixed to particular output port j. When the data packet arrives
at node 33, the output port marker at node 34 is needed for
arbitration, which is previously determined at node 32 by
look-ahead routing calculation. Therefore look-ahead routing
minimizes the processing pipeline from five stages to four
stages by small complicity overhead.
(iii) Switch Allocator
According to the above analysis, we propose a switch
allocator (SA) structure based on wormhole routing. Each
output port has its own SA, shown in Fig.2. The requests for
output port j with the look-ahead information are given to the
SA j by the look-ahead route decision units. And credits from
the next router are also fed back into the SA j to notice the
empty/full states of VOQs of the next router. The SA outputs
the grant signals to control the crossbar. Fig.4 shows the
infrastructure of a SA. The requests with the same output port
in the current router and the same output port in the next
router will enter a 1st-stage arbiter. When one of the requests
gets admission in the 1st-stage arbiter, the admission keeps
valid. When the tail flit of a data packet leaves the router, a
corresponding signal will trigger a next round of arbitration.
So the flits from different data packets wont overlap at the
output port of the next node. After the 1st-stage arbitration, the
packets enter the 2nd-stage arbitration. In the 2nd-stage
arbitration, if the data packets from different input port request
the same output port in the current router, the packets will
share the output port and be sent out alternatively. The final
grants are sent to the crossbar after this two-stage arbitration.
D. Network Interface
The network interface (NI) plays the role of a bridge
between a PE and its corresponding rouuter. When a PE
completes its computation task, it sends thee packet from the
local processor to the router via NI. The NI is
i implemented on
the basis of processor local bus (PLB). Sincce a big gap exists
between the clock frequencies of the processor and the
underlying router, it is necessary for NI to do the speed
matching when transmitting data betweenn the PE and the
router.
IV. SOFTWARE TOOL
In MPP NoC, dozens of PEs can cooperaate for a dedicated
application, in which different tasks are maapped to different
PEs. If an unsuitable mapping solution asssigns tasks to PEs
with large transmission delay or serious poower consumption,
the potential on NoC will be restrained. So a software tool is
(a) The tasks flow graph of a 4G comm
munication transmitter. (The tasks and
developed in our MACRON platform m to provide a transmission loads among tasks are exttracted from Simulink automatically.)
recommended mapping solution.
A. Estimation Flow
This electronic design automatic (E EDA) tool is a
simulation and estimation software developeed using Microsoft
Foundation Classes (MFC). By the aid of the basic module
library and the user-defined module library, this software with
featured functions, such as delay or power consumption
statistics, user-defined modules, visual simuulation and so on,
will finally give the estimation result of NoC
N mapping and
scheduling. Fig. 5 shows the tool windows.
The operation procedures of this EDA A tool works as
follows: (i) Create a new project. The user can create a new
project through menu bar or tool bar to autom matically generate
a Simulink project folder in a specific directory, which
includes the schematic file, the configuraation file and the
relevant codes of user-defined modules. (ii) Connect the
processing modules. The ports of the modules can be
(b) A mapping solution given by the EDA tool. (Note that the bandwidths of
connected manually, or generate a script to connect these links are inconsistent, since the intra-FPGA and inter-FPGAs transmission
modules automatically. Besides, the tool can c configure the channels have different data rates.)
communication bandwidth to set differentt constraints. (iii)
Fig. 5. The graphical windows of the EDA
E tool.
Select the mapping algorithm. This tool provides
p common
mapping algorithms library and the user can choose one
algorithm to map the parallel or pipelined tasks
t to NoC PEs. V. PROCEESSING CORES
(iv) Assess the performance of the NoC under a specific
mapping solution. This EDA tool provides NoC performance To support the state-of-tthe-art software radio or soft
evaluation such as delay and power consumption;
c the baseband processing, it providdes the system great flexibility
graphical interface will intuitively show thee efficiency of the for processors take most of o the signal processing and
optimized mapping solution analyzed by the build-in tool. computation. We designed three types of PEs in the
MACRON platform: a vecttor processor core, a scalar
B. Mapping Methods processor core and an accelerattor. The vector processor core is
The mapping algorithms library in thhis software tool designed dedicated to repeatedd and compute-intensive signal
mainly includes ant colony algorithm, geneetic algorithm and processing, e.g. matrix compputations. The scalar processor
other user-defined algorithms. The parrameters of the core is designed for control annd bit level processing. And the
algorithms can be adjusted by user. For exxample, if the ant accelerator is the circuits dedicated to specific functions, e.g.
colony mapping algorithm is chosen, the user can set ant channel decoding.
colony scale and iteration times. And the optimization goal A. Vector Processor Core
can be chosen for minimizing the delay, the power
consumption or the bandwidth in order that the algorithm can The processing speed of the vector processor improves
provide different mapping solutions for users different greatly because the Very Longg Instruction Word (VLIW) and
requirements. The user-defined algorithm iss a scalable option Single Instruction Multiple Data (SIMD) techniques are
and can be added into the software in a presccribed way. applied, so that eight instructioons are executed in parallel and

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sixteen data are computed simultaneously in every instruction
slot, shown in Fig. 6. The vector processor is mainly used for
channel estimation and equalization in our LTE system
demonstration, so the instruction set is optimized dedicatedly
for baseband signal processing.
The vector processing has five pipeline stages: PF (pre-
fetch), FE (fetch), DC (decode), EXE1 (execute) and EXE2
(only for some memory access operation with double cycles).
By analyzing the channel estimation and equalization
algorithms, we group the vector processor instructions into
four categories: arithmetic logical unit (ALU) instructions,
multiplication and addition (MAC) instructions, memory
access instructions and control instructions. A VLIW gets
eight instructions in one word, where each instruction is
encoded by 24 bits. All the eight instructions are assigned to
the different decoding units and the different executing units
to be executed. At the stage of decode, the ALU instruction
will be dispatched to instruction slot 1 or slot 2, the MAC
instruction to slot 3 or slot 4, the memory access instruction to
slot 5, slot 6 or slot 7, and the control instructions will be
dispatched to slot 8.
After the analysis of the resource usage, sixteen scalar
registers and eight vector registers are designed to constitute
the register file. The scalar register is 16-bit wide and the
vector register is 256-bit wide, so the processor is able to
process sixteen data simultaneously in one instruction slot.
The vector processor can access one data memory, one
program memory and sixteen coefficient memories. The
program memory and the coefficient memory are read-only by
the vector processor core.
B. Scalar Processor core
The scalar processor is designed on the basis of reduced-
instruction-set computer (RISC) architecture with special
instructions which are dedicated to the communication signal
processing. From the perspective of application, the scalar
processor is used for light load computation or non-vector
computation such as the control operation, the bit level
operation and so on. So the instruction set of the scalar
processor is based on the RISC instruction, and some special
instructions are provided in order to meet particular
Fig. 6. The block diagram of the vector processor core.
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application functions such as division operation or convolution
operation, which are common in instruction set of DSP
processor.
The RISC processor has six pipeline stages in order to
improve the processing speed. The control instructions always
lead to a complicated program counter finite state machine
(FSM) and a complicated pipeline. The multi-stages pipeline
will cause control hazard or data hazard. The control hazard
usually means that several instructions have been pushed into
the processing pipeline before a branch instruction executed,
so NOOP instructions are inserted to solve this problem by
compiler. For data hazard that a register is read/written
incorrectly due to the register access being interfered by other
pipelined stage, by-pass circuits and NOOP instructions
insertion are adopted in our implementation.
C. Accelerator
In the baseband signal processing, some tasks are heavy-
load computations and require severe real-time constraint,
such as Turbo decoding in every 0.5ms slot. These extremely
heavy-load tasks cannot be completed by the processor core in
real-time. So hardware accelerator is also one kind of PEs in
some applications.
Turbo code is widely used in modern communication
system, so the parallel circuits of the turbo decoding is
implemented to promote the processing throughput [18]. The
turbo decoding is exploited in iterative manner and two Single
Input Single Output (SISO) decoders share the extrinsic
information to generate soft outputs in each iteration. Popular
algorithms for SISO decoding are BCJR algorithms and
forward-backward algorithm [16], such as maximum-a-
posteriori (MAP) algorithm. In Turbo codec, interleaver
scrambles data in a pseudo random order to minimize the
correlation of neighboring bits at the input of the
convolutional encoders. The quadratic permutation
polynomial (QPP) interleaver guarantees the desirable
contention-free property for parallel memory access and has
been adopted in LTE for turbo code. In our implementation,
each input frame is divided into N sub-blocks and then each
sub-block is processed on a L-BCJR decoder using adequate
initializations.
VI. NUMERICAL ANALYSIS
A. VOQ Switch Performances
We use Verilog hardware description language (HDL) to
implement the VC switching structure and the VOQ switching
structure and compare their performances in NoC. The
relevant experiment parameters are listed in Table I. In
experiment, a global clock is used to measure the transmission
delay for all packets.
The delay through the router is computed as follow:
Pall
Latency = (Te (i ) Ts (i )) Pall (1)
i =1
where Pall stands for the total number of data packets. Ts (i ) ,
i = (1, 2,..Pall ) is the moment when the head flit of packet i is
injected into the on-chip networks; and Te (i ) , i = (1, 2,..Pall )
refers to the moment when the head flit is sunk by the PE. In
the measurement, every PE injects 100000 data packets into
the on-chip networks. The injection rate Rinj and the
throughput Rthr are calculated as follows:
N Sj

Rinj = L jm NTclk (2)

j =1 m =1

N Rj

Rthr = L jn NTclk (3)

j =1 n =1

where Tclk stands for the clock period; N is the number of all
nodes; S j and R j are the numbers of injected packets and
sunk packets in node j respectively; L jm is the packet length of
the m-th packet injected by node j; and L jn is the packet
length of the n-th packet sunk by node j.
We compare the delays of the two switching structures
under the bit complement traffic pattern [17], shown in Fig. 7.
We found that if the injection rate is unsaturated, the VOQ
switching can achieve 11% delay improvement than VC
switching, because it saves one cycle for packet passing
through the VOQ switching structure. If the injection rates go
beyond 0.2 for VOQ and 0.22 for VC respectively, delays start
to deteriorate significantly due to the lack of buffer resources.
It means, if we use XY dimension-order routing, the
extraordinary heavy traffic will cause VOQ switching suffer
more performance degradation than VC switching. In the case
of XY dimension-order routing, a packet enters the router
from the southern port or northern port wont go to the eastern
port or western port. Thus VOQ(2,1), VOQ(2,3) and
VOQ(4,1), VOQ(4,3) are under-utilized, i.e. 20% buffer
resources in the VOQ switching structure are unused, which
causes VOQ to block under extreme heavy traffic. In other
words, queuing resources in VOQ can be saved further if XY
dimension-order routing is adopt. By our statistics, the
throughputs of VC and VOQ are similar. This is because the
affecting factors of throughput are the same in the two
experimental scenarios, such as the number of active links, the
average hops across the network.
B. Speedup Ratio
In order to observe the speedup ratios under parallel
TABLE I. EXPERIMENT PARAMETERS FOR SWITCH SCHEMES
Fig. 7. The processing delays of VC and VOQ router under the Bit
Complement traffic pattern.
processing on multi-cores, we tested Fast Fourier Transform
(FFT) computations under different points scenarios. To
guarantee the accuracy of the measurement, the value of
processing delay is averaged of 10 times measurements.
Firstly, we get the processing time of different points of
FFT in the condition of single core, dual cores and quad cores,
shown in table II. 1536-point FFT is tested only in the
condition of quad cores due to its particularity of parallel
method.
For those whose FFT points equal to 2M, dual cores can
achieve the speedup ratio up to 1.7, and quad cores can bring
the speedup ratio up to 3.5. But in 1536-points FFT whose
number of point does not equal to 2M, its parallel processing
procedure is quite difference. The steps of 1536-points
Discrete Fourier Transform (DFT) parallelization are: (i)
divide the input data into three 512-point sequences and
process traditional 512-points FFT computations; (ii) the
second and third sequences are multiplied by common twiddle
factors; (iii) sum the values of the three sequences together to
get the final result. Due to the increase of data exchanged
among cores in non-2M-points DFT, the efficiency of quad
cores decreased but can still provide a speedup ratio to 2.4. If
we use more than a dozen of cores in parallel FFT
computation, the system can operate at a higher processing
speed. But data traffic among cooperated cores requires
communication latency, which will decrease the processing
efficiency when overmany cores are used.

Network topology 2D 88 Mesh

Routing algorithm Dimension-order routing
TABLE II. THE STATISTICS OF THE PROCESSING TIMES OF MULTICORES
Traffic pattern Bit Complement
Processing Points of FFT
Number of ports per router 5 time
(cycles) 128 256 512 1024 1536 2048
Number of VCs/VOQs per port 4
Single core 2889 6634 15493 35377 46447 79542
Buffer length per VC/VOQ 6
Dual cores 1768 3966 9332 21601 48090
--
Flit size (bits) 32 (Speedup ration) (1.6) (1.7) (1.7) (1.6) (1.7)
Quad cores 819 1870 4380 10008 19252 22709
Packet length (flits) 10 (Speedup ration) (3.5) (3.5) (3.5) (3.5) (2.4) (3.5)

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 TABLE III. VECTOR SIGNAL PROCESS UTILIZATION estimation and equalization, etc. Since OFDM,
Vector signal Memory Control synchronization, channel estimation and equalization are
ALU MAC compute-intensive tasks, these three tasks are assigned two
processing access (Scalar)
2048-points FFT
60.6% 39.4% 99.4% 0.3% PEs for parallel processing, and each of the rest tasks is
(complex numbers) processed by one PE respectively. Fig. 8 shows the task
48-taps FIR filter partition of LTE baseband processing. The numbers next to
96.8% 97.0% 99.2% 0.3%
(real numbers)
Channel estimation the modules identify the positions of which they are mapped
28.3% 34.8% 66.1% 4.4% to.
and equalization

C. Vector Processing Utilization As shown in Fig. 9, a LTE transceiver is accommodated in

In order to save the resource area, the instruction slots in
VLIW vector processor are not all-rounders. Some slots are
dedicated for ALU, MAC, and some for memory access and
control. During vector processing, if all instruction slots are
executed, the vector processor is fully utilized. In practice,
only partial instruction slots are executed in each cycle, while
others are idle. Thus the utilizations of the instruction slots are
critical to the vector processing efficiency.
Table III summarizes the utilizations of four types of
vector instruction slots in typical signal processing. We found
that Finite Impulse Response (FIR) filter is computation-
intensive; the MAC slots are executed in 97.0% of the cycles
during FIR computation.
VII. DEMOSTRATION
The many-core platform is a flexible way for wireless
communication systems to support multiple standards, like
GSM, WCDMA, LTE, LTE-A, by only downloading the
instruction codes without circuits changing. We implement a
4*4 Mesh NoC on the MACRON platform. We divide a
complicated 4G system into several tasks and assign them
Fig. 8. The baseband tasks partition of LTE communicaiton system.
onto different PEs for parallel and pipelined processing. By
accomplishing the baseband signal processing in parallel, a
LTE communication system is carried out for demonstration.
A. LTE Demo
We take a 2*2 Multiple-Input Multiple Output (MIMO)
wireless communication system as the target application, and
implement both the transmitter and the receiver. Some system
parameters are listed in table IV.
The tasks mapping is done firstly in the MACRON EDA
tool to provide an injective function solution. The LTE
baseband processing tasks include Cyclic Redundancy Check
(CRC), Turbo codec, modulation, Orthogonal Frequency
Division Multiplexing (OFDM), synchronization, channel

TABLE IV. LTE SYSTEM PARAMETERS

Antenna 2 Tx / 2 Rx
Bandwidth 5MHz
FFT points 2048
Turbo code rate 1/3, 1/2, 2/3
Modulations QPSK, 16QAM
Channel estimation method Least square algorithm
Fig. 9. LTE baseband modules mapped onto MACRON platform. (The
Equalization method Zero force algorithm yellow blocks are the vector processor cores, the grey ones are scalar
processor cores, the blue one is the accelerator, and dashed blocks are idle. )

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(a) The visual states of PEs. (b) The visual states of links.
Fig. 10. The states of PEs and links on MACRON are monitored and
displayed.
MACRON hardware platform. The modules of transmitter are
implemented in FPGA_C. The baseband signals from OFDM
are sent to FPGA_D via GTX, and are delivered to the RF
board via HSIQ interface for wireless propagation. The
receiver modules are accommodated in other three FPGAs.
When RF board receives signals from the mobile terminal, it
sent the sampled data to the baseband board via HSIQ
interface after analog-to-digital conversion. After a series of
baseband signal processing, the voice or video stream can be
restored and sent to user via an Ethernet interface.
B. NoC States Monitoring
We can monitor the state of NoC in real-time by collecting
the states of all buffers of the router. The state of the LTE
system is also monitored. The collected state information
consists of busy/idle states of PEs and links, MIMO channel
gains, signal to noise ratio, constellation graph, and frame
error rate. The collected state information are sent to the
computer via a SFP port on the baseband board, a data
acquisition board ML605, and the PCIE interface of a
computer in turn. Finally, the states of NoC and LTE system
can be displayed on the computer.
The busy/idle statistics of PEs are shown in Fig. 10(a). A
higher bar means a busier state of PE. Compared with Fig. 10,
the bars of node 23 and 24 are the highest because OFDM
modules are executed in these two PEs, where FFT
computations lead to hotspots. The busy/idle statistics of links
are shown in Fig. 10(b). The thicker arrow means there are
more data transmitted on this link. The data flows from node
13 to 23 and from node 14 to 24 are the busiest flows, where a
large number of packets are transmitted from synchronization
modules to the OFDM modules.
VIII. CONCLUSIONS
We have presented a NoC-based platform, MACRON, for
many-core parallel processing verification. By combining the
software tool and the hardware device, MACRON can provide
estimation and verification for complicated applications. We
implemented a LTE wireless communication system in
MACRON, which proves that the proposed VOQ architecture
with look-ahead routing is competent to reduce the
transmission delay, and the designed processor cores are
effective for vector processing and scalar processing.
403
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