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Features
Operating voltage: 2.4V~12V Built-in oscillator needs only 5% resistor
Low power and high noise immunity CMOS Easy interface with an RF or an infrared
technology transmission medium
Low standby current Minimal external components
Minimum transmission word Package information: refer to Selection
- Four words for TE trigger Table
- One word for Data trigger
Applications
Burglar alarm system Security system
Smoke and fire alarm system Cordless telephones
Garage door controllers Other remote control systems
Car alarm system
General Description
The 312 encoders are a series of CMOS LSIs for programmable address/data which meet vari-
remote control system applications. They are ca- ous applications. The programmable ad-
pable of encoding 12 bits of information which dress/data is transmitted together with the header
consists of N address bits and 12-N data bits. bits via an RF or an infrared transmission medium
Each address/data input is externally trinary upon receipt of a trigger signal. A TE (HT6010) or
programmable if bonded out. They are otherwise a DATA (HT6012/HT6014) trigger can be se-
set floating internally. Various packages of the lectedforapplicationflexibility.
3 12 encoders offer flexible combinations of
Selection Table
Function Address Address/ Data LED
Oscillator Trigger Package
Part No. No. Data No. No. Indicator
18/20 DIP
HT6010 8 4 0 RC oscillator TE No
20 SOP
HT6012 10 0 2 RC oscillator D10~D11 Yes 18 DIP/20 SOP
HT6014 8 0 4 RC oscillator D8~D11 Yes 18 DIP/20 SOP
Note: Address/Data represents addressable pins or data according to the requirements of decoders.
Block Diagram
TE trigger
HT6010
O S C 2 O S C 1
O s c illa to r 3 D iv id e r D a ta S e le c t D O U T
a n d B u ffe r
T E
1 2 C o u n te r S y n c .
A 0 a n d 1 o f 1 2
C ir c u it
1 2 D e c o d e rs
T r a n s m is s io n
G a te C ir c u it
A 7 T r in a r y
D e te c to r
A D 8 A D 1 1 V D D V S S
DATA trigger
HT6012/HT6014
O S C 2 O S C 1
O s c illa to r 3 D iv id e r D a ta S e le c t D O U T
a n d B u ffe r
1 2 C o u n te r S y n c .
a n d 1 o f 1 2
1 2 D e c o d e rs C ir c u it
A d d re s s T r a n s m is s io n
G a te C ir c u it
T r in a r y L E D
L E D C ir c u it
D e te c to r
D a ta V D D V S S
Note: The address/data pins are available in various combinations (refer to the address/data table).
Pin Assignment
T E tr ig g e r ty p e
8 -A d d re s s 8 -A d d re s s
4 -A d d r e s s /D a ta 4 -A d d r e s s /D a ta
N C 1 2 0 N C
A 0 1 1 8 V D D A 0 2 1 9 V D D
A 1 2 1 7 D O U T A 1 3 1 8 D O U T
A 2 3 1 6 O S C 2 A 2 4 1 7 O S C 2
A 3 4 1 5 O S C 1 A 3 5 1 6 O S C 1
A 4 5 1 4 T E A 4 6 1 5 T E
A 5 6 1 3 A D 1 1 A 5 7 1 4 A D 1 1
A 6 7 1 2 A D 1 0 A 6 8 1 3 A D 1 0
A 7 8 1 1 A D 9 A 7 9 1 2 A D 9
V S S 9 1 0 A D 8 V S S 1 0 1 1 A D 8
H T 6 0 1 0 H T 6 0 1 0
1 8 D IP 2 0 D IP /S O P
D A T A tr ig g e r ty p e
1 0 -A d d re s s 1 0 -A d d re s s 8 -A d d re s s
2 -D a ta 2 -D a ta 4 -D a ta
N C 1 2 0 N C
A 0 1 1 8 V D D A 0 2 1 9 V D D A 0 1 1 8 V D D
A 1 2 1 7 D O U T A 1 3 1 8 D O U T A 1 2 1 7 D O U T
A 2 3 1 6 O S C 2 A 2 4 1 7 O S C 2 A 2 3 1 6 O S C 2
A 3 4 1 5 O S C 1 A 3 5 1 6 O S C 1 A 3 4 1 5 O S C 1
A 4 5 1 4 L E D A 4 6 1 5 L E D A 4 5 1 4 L E D
A 5 6 1 3 D 1 1 A 5 7 1 4 D 1 1 A 5 6 1 3 D 1 1
A 6 7 1 2 D 1 0 A 6 8 1 3 D 1 0 A 6 7 1 2 D 1 0
A 7 8 1 1 A 9 A 7 9 1 2 A 9 A 7 8 1 1 D 9
V S S 9 1 0 A 8 V S S 1 0 1 1 A 8 V S S 9 1 0 D 8
H T 6 0 1 2 H T 6 0 1 2 H T 6 0 1 4
1 8 D IP 2 0 S O P 1 8 D IP
8 -A d d re s s
4 -D a ta
N C 1 2 0 N C
A 0 2 1 9 V D D
A 1 3 1 8 D O U T
A 2 4 1 7 O S C 2
A 3 5 1 6 O S C 1
A 4 6 1 5 L E D
A 5 7 1 4 D 1 1
A 6 8 1 3 D 1 0
A 7 9 1 2 D 9
V S S 1 0 1 1 D 8
H T 6 0 1 4
2 0 S O P
Pin Description
Internal
Pin Name I/O Description
Connection
TRANSMISSION Input pins for address A0~A9 setting
A0~A9 I
GATE They can be externally set to VDD or VSS or left open.
TRANSMISSION Input pins for address/data (AD8~AD11) setting
AD8~AD11 I
GATE They can be externally set to VDD or VSS or left open.
Input pins for data (D8~D11) setting and transmission en-
CMOS IN
D8~D11 I able (active low)
Pull-high
They can be externally set to VSS or left open (see Note).
DOUT O CMOS OUT Encoder data serial transmission output
LED O NMOS OUT Transmission enable indicator, active low
CMOS IN
TE I Transmission enable, active low (see Note)
Pull-high
OSC1 I OSCILLATOR Oscillator input pin
OSC2 O OSCILLATOR Oscillator output pin
VSS Negative power supply, ground
VDD Positive power supply
Note: D8~D11 are data input and transmission enable pins of the HT6012/HT6014.
TE is the transmission enable pin of the HT6010.
T R A N S M IS S IO N C M O S IN
G A T E P u ll- h ig h C M O S O U T N M O S O U T
O S C IL L A T O R
E N
O S C 1 O S C 2
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-
mum Ratings may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage 2.4 5 12 V
3V 0.1 1 mA
ISTB Standby Current Oscillator stops
12V 2 4 mA
3V No load 250 500 mA
IDD Operating Current
12V fOSC=3kHz 600 1200 mA
ILED LED Sink Current 5V VLED=0.5V 1.5 3 mA
5V VOH=0.9VDD (Source) -0.6 -1.2 mA
IDOUT Output Drive Current
5V VOL=0.1VDD (Sink) 0.6 1.2 mA
VIH H Input Voltage 0.8VDD VDD V
VIL L Input Voltage 0 0.2VDD V
fOSC Oscillator Frequency 5V ROSC=1MW 3 kHz
RTE TE Pull-high Resistance 5V VTE=0V 1.5 3 MW
Functional Description
Operation
The 312 series of encoders begin with a four (HT6010) or a one (HT6012/HT6014) word transmission
cycle upon receipt of a transmission enable (TE for the HT6010 or D8~D11 for the HT6012/HT6014, ac-
tive low). This cycle will repeat itself as long as the transmission enable (TE or D8~D11) is held low.
Once the transmission enable returns high the encoder output completes its final cycle and then stops
as shown below.
T E o r
D 8 ~ D 1 1
< 1 w o rd
E n c o d e r
D a ta O u t
1 o r 4 w o rd s T r a n s m itte d 1 o r 4
C o n tin u o u s ly w o rd s
Transmission timing
Information word
An information word is composed of four periods as shown:
1 /6 b it s y n c . p e r io d
p ilo t p e r io d ( 6 b its ) a d d r e s s c o d e p e r io d d a ta c o d e
p e r io d
Composition of information
Address/data waveform
Each programmable address/data pin can be externally set to one of the following three logic states:
fO S C
"O n e "
"Z e ro "
"O p e n "
A d d r e s s /D a ta B it
The Open state data input is interpreted as logic high by the decoder since its output has only two
states.
Address/Data sequence
The following table provides the position of the address/data sequence for various models of the 312
series encoders. A correct device should be selected according to the requirements of the individual
address and data.
Address/Data Bits
Part No.
0 1 2 3 4 5 6 7 8 9 10 11
HT6010 A0 A1 A2 A3 A4 A5 A6 A7 AD8 AD9 AD10 AD11
HT6012 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D10 D11
HT6014 A0 A1 A2 A3 A4 A5 A6 A7 D8 D9 D10 D11
Transmission enable
For the TE trigger type of encoders, transmission is enabled by applying a low signal to the TE pin.
But for the Data trigger type, it is enabled by applying a low signal to one of the data pins D8~D11.
Flowchart
P o w e r o n
S ta n d b y m o d e
N o T r a n s m is s io n
e n a b le d ?
Y e s
C o d e w o rd
tr a n s m itte d
c o n tin u o u s ly
N o T r a n s m is s io n
s till e n a b le d ?
Y e s
C o d e w o rd
tr a n s m itte d
c o n tin u o u s ly
fO S C
(S c a le )
R O S C (W )
7 .0 0
4 7 0 k
5 1 0 k
6 .0 0
5 6 0 k
6 2 0 k
5 .0 0
6 8 0 k
7 5 0 k
4 .0 0 8 2 0 k
9 1 0 k
1 .0 M
(3 k H z )3 .0 0
1 .2 M
1 .5 M
2 .0 0
2 .0 M
1 .0 0
2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 V D D (V D C )
Application Circuits
T r a n s m itte r C ir c u it T r a n s m itte r C ir c u it
V D D V D D
1 1 8 1 1 8
A 0 V D D A 0 V D D
2 1 7 2 1 7
A 1 D O U T A 1 D O U T
3
A 2 O S C 2 1 6 3 A 2 O S C 2 1 6
4 R O S C R O S C
A 3 O S C 1 1 5 4 A 3 O S C 1 1 5
5 1 4 5 1 4 R
A 4 T E A 4 L E D
6 A 5 A D 1 1 1 3 6 A 5 D 1 1 1 3
7 A 6 A D 1 0 1 2 7 A 6 D 1 0 1 2
8 A 7 A D 9 1 1 8 A 7 A 9 1 1
9 V S S A D 8 1 0 9 V S S A 8 1 0
H T 6 0 1 0 H T 6 0 1 2
T r a n s m itte r C ir c u it
V D D
1 A 0 V D D 1 8
2 A 1 D O U T 1 7
3 A 2 O S C 2 1 6
R O S C
4 A 3 O S C 1 1 5
5 1 4 R
A 4 L E D
6 A 5 D 1 1 1 3
7 A 6 D 1 0 1 2
8 A 7 D 9 1 1
9 V S S D 8 1 0
H T 6 0 1 4