CHAPTER 3 INSTRUCTION

FORMAT
3.1 Introduction
3.2 Elements of instruction
3.3 Types of Instruction Format
3.2) Introduction
The operation of the CPU is determined by
the instructions it executes,
The instructions also referred to as machine
instruction or computer instructions
The collection of different instructions that
the CPU can execute is referred to as the
CPUs instruction set
 3.2 Element of Instruction
each instruction must contain the information
required by the CPU for execution :
Operation code
Source operand reference
Result operand reference
Next Instruction reference

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Elements in a instruction
1) Operation code :
specifies the operation to be performed
(eg: ADD, I/O)
2) Source operand reference :
the operation may involve one or more
source operands (input for the operation)
3) Result operand reference :
the operation may produce a result
4) Next Instruction reference :
to tell the CPU where to fetch the next
instruction after the execution of this
instruction is complete
Source and result operand reference can
be in one of the three areas :
1) Main or Virtual Memory
2) Register in CPU
3) I/O device
 it is not efficient to put all the information required by the
CPU in a machine instruction
within the computer, each instruction is represented by a
sequence of bits and is divided into two fields :
opcode (operation code)
Address
Opcode Address
How many addresses that might need in an instruction
or mostly used by the computers?
Opcode Address
- 0 address
- 1 address
- 2 addresses
- 3 addresses
- 4 addresses
 Generally, instruction processing becomes fast if all
information are in one instruction or one instruction format

Operation Operand1 Operand2 Result Next Instruction Address

Code Address Address Address

opcode address

problem : instruction will be long (will take a few words

in the main memory just to store 1 instruction)
solution : create a few types of instruction format (1,2
or 3 addresses) and also addressing mode (the way of
addressing operand)
3.3 Types of Instruction Format
1) 3 Address Instruction
Operation Result Operand1 Operand2
Code Address Address Address

Address Field ( 3 addresses)

Example: SUB Y A B Y A B
- Resultwill be stored in Y
- operand 1 is in A and operand 2 is in B
- the operation is subtraction operation
- Problem : Instruction format long
- Question : how to acquire the next address of the
following instruction? => in the PC (Program Counter)
2) 2 Address Instruction
Operation Operand 1 & Result Operand2
Code Address

Address Field ( 2 addresses)

Example: SUB Y B Y Y B

- Operand 1 is in Y and this location is also used to store

the result
- Operand 2 is in B
- at the end, the value of operand 1 will be replaced with the
operation result (Y B)
- like in 3 addresses instructions, the address of the
following instruction is in the PC (Program Counter)
3) 1 Address Instruction
Operation Operand2
Code Address

Address Field ( 1 address)

Example:
LOAD A AC A
ADD B ACAC + B
SUB B AC AC - B

- address field is refer to Operand2 address

-Operand 1 and result are stored in a special register called
Accumulator (AC)
 1 address instructions are the most
commonly used as the instructions
are short (require less bits) but to solve
an arithmetic more instructions are
needed
1 address instruction format also use
the PC to determine the address of the
next instruction
EXAMPLE 1: Write the following instructions to
execute Y = (A B) (D * E) [ T-temp storage ]

lnstruction Comment
SUB Y, A, B YAB
MPY T, D, E TDxE
DIV Y, Y, T Y Y T

(a) Three-Address Instructions

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 Instructions Comment
MOVE Y,A YA
SUB Y,B YY-B
MOVE T,D TD
MPY T,E TT*E
DIV Y,T YYT

(b) Two-Address Instructions

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 Instruction Comment
LOAD D AC D
MPY E AC AC * E
STOR T T AC
LOAD A AC A
SUB B AC AC B
DIV T AC AC T
STOR Y Y AC

(c) One-Address Instructions

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EXAMPLE 2: Write the following instructions to
execute Y = (A B) 5D [ T-temp storage ]

lnstruction Comment
SUB Y, A, B YAB
MPY T, 5, D T 5x D
DIV Y, Y, T Y Y T

(a) Three-Address Instructions

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 Instructions Comment
MOVE Y,A YA
SUB Y,B YY-B
MOVE T,5 T5
MPY T,D TT*D
DIV Y,T YYT

(b) Two-Address Instructions

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 Instruction Comment
LOAD 5 AC 5
MPY D AC AC * D
STOR T T AC
LOAD A AC A
SUB B AC AC B
DIV T AC AC T
STOR Y Y AC

(c) One-Address Instructions

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